From 435349977cad43f4635ca39e0171d7a0d3092a57 Mon Sep 17 00:00:00 2001
From: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Date: Thu, 25 Oct 2018 17:11:02 +0100
Subject: [PATCH] Fix MISRA defects in workaround and errata framework
No functional changes.
Change-Id: Iaab0310848be587b635ce5339726e92a50f534e0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
---
include/lib/cpus/aarch64/cortex_a75.h | 12 +++++++-----
include/lib/cpus/aarch64/cortex_ares.h | 12 +++++++-----
include/lib/cpus/errata_report.h | 7 +++----
include/lib/cpus/wa_cve_2017_5715.h | 6 +++---
include/lib/cpus/wa_cve_2018_3639.h | 6 +++---
include/lib/el3_runtime/cpu_data.h | 6 +++---
lib/cpus/aarch64/cortex_a75_pubsub.c | 6 ++++--
lib/cpus/aarch64/cortex_ares_pubsub.c | 6 ++++--
lib/cpus/errata_report.c | 11 ++++++-----
9 files changed, 40 insertions(+), 32 deletions(-)
diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h
index 493c7d472..f68f98f63 100644
--- a/include/lib/cpus/aarch64/cortex_a75.h
+++ b/include/lib/cpus/aarch64/cortex_a75.h
@@ -4,11 +4,13 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __CORTEX_A75_H__
-#define __CORTEX_A75_H__
+#ifndef CORTEX_A75_H
+#define CORTEX_A75_H
+
+#include <utils_def.h>
/* Cortex-A75 MIDR */
-#define CORTEX_A75_MIDR 0x410fd0a0
+#define CORTEX_A75_MIDR U(0x410fd0a0)
/*******************************************************************************
* CPU Extended Control register specific definitions.
@@ -24,7 +26,7 @@
#define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (1 << 35)
/* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */
-#define CORTEX_A75_CORE_PWRDN_EN_MASK 0x1
+#define CORTEX_A75_CORE_PWRDN_EN_MASK U(0x1)
#define CORTEX_A75_ACTLR_AMEN_BIT (U(1) << 4)
@@ -50,4 +52,4 @@ void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask);
void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask);
#endif /* __ASSEMBLY__ */
-#endif /* __CORTEX_A75_H__ */
+#endif /* CORTEX_A75_H */
diff --git a/include/lib/cpus/aarch64/cortex_ares.h b/include/lib/cpus/aarch64/cortex_ares.h
index 84955b181..4f3e81296 100644
--- a/include/lib/cpus/aarch64/cortex_ares.h
+++ b/include/lib/cpus/aarch64/cortex_ares.h
@@ -4,11 +4,13 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __CORTEX_ARES_H__
-#define __CORTEX_ARES_H__
+#ifndef CORTEX_ARES_H
+#define CORTEX_ARES_H
+
+#include <utils_def.h>
/* Cortex-ARES MIDR for revision 0 */
-#define CORTEX_ARES_MIDR 0x410fd0c0
+#define CORTEX_ARES_MIDR U(0x410fd0c0)
/*******************************************************************************
* CPU Extended Control register specific definitions.
@@ -17,7 +19,7 @@
#define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4
/* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */
-#define CORTEX_ARES_CORE_PWRDN_EN_MASK 0x1
+#define CORTEX_ARES_CORE_PWRDN_EN_MASK U(0x1)
#define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4)
@@ -30,4 +32,4 @@
#define CPUPOR_EL3 S3_6_C15_C8_2
#define CPUPMR_EL3 S3_6_C15_C8_3
-#endif /* __CORTEX_ARES_H__ */
+#endif /* CORTEX_ARES_H */
diff --git a/include/lib/cpus/errata_report.h b/include/lib/cpus/errata_report.h
index d2138bf55..c97d4c247 100644
--- a/include/lib/cpus/errata_report.h
+++ b/include/lib/cpus/errata_report.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __ERRATA_H__
-#define __ERRATA_H__
+#ifndef ERRATA_REPORT_H
+#define ERRATA_REPORT_H
#ifndef __ASSEMBLY__
@@ -30,5 +30,4 @@ int errata_needs_reporting(spinlock_t *lock, uint32_t *reported);
#define ERRATA_APPLIES 1
#define ERRATA_MISSING 2
-#endif /* __ERRATA_H__ */
-
+#endif /* ERRATA_REPORT_H */
diff --git a/include/lib/cpus/wa_cve_2017_5715.h b/include/lib/cpus/wa_cve_2017_5715.h
index 0a65a5692..940fc659e 100644
--- a/include/lib/cpus/wa_cve_2017_5715.h
+++ b/include/lib/cpus/wa_cve_2017_5715.h
@@ -4,9 +4,9 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __WA_CVE_2017_5715_H__
-#define __WA_CVE_2017_5715_H__
+#ifndef WA_CVE_2017_5715_H
+#define WA_CVE_2017_5715_H
int check_wa_cve_2017_5715(void);
-#endif /* __WA_CVE_2017_5715_H__ */
+#endif /* WA_CVE_2017_5715_H */
diff --git a/include/lib/cpus/wa_cve_2018_3639.h b/include/lib/cpus/wa_cve_2018_3639.h
index 36546f70d..e37db377e 100644
--- a/include/lib/cpus/wa_cve_2018_3639.h
+++ b/include/lib/cpus/wa_cve_2018_3639.h
@@ -4,9 +4,9 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __WA_CVE_2018_3639_H__
-#define __WA_CVE_2018_3639_H__
+#ifndef WA_CVE_2018_3639_H
+#define WA_CVE_2018_3639_H
void *wa_cve_2018_3639_get_disable_ptr(void);
-#endif /* __WA_CVE_2018_3639_H__ */
+#endif /* WA_CVE_2018_3639_H */
diff --git a/include/lib/el3_runtime/cpu_data.h b/include/lib/el3_runtime/cpu_data.h
index 15d34ebf8..b6959509c 100644
--- a/include/lib/el3_runtime/cpu_data.h
+++ b/include/lib/el3_runtime/cpu_data.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __CPU_DATA_H__
-#define __CPU_DATA_H__
+#ifndef CPU_DATA_H
+#define CPU_DATA_H
#include <ehf.h>
#include <platform_def.h> /* CACHE_WRITEBACK_GRANULE required */
@@ -161,4 +161,4 @@ void init_cpu_ops(void);
#endif /* __ASSEMBLY__ */
-#endif /* __CPU_DATA_H__ */
+#endif /* CPU_DATA_H */
diff --git a/lib/cpus/aarch64/cortex_a75_pubsub.c b/lib/cpus/aarch64/cortex_a75_pubsub.c
index 16f62f472..f4ca48606 100644
--- a/lib/cpus/aarch64/cortex_a75_pubsub.c
+++ b/lib/cpus/aarch64/cortex_a75_pubsub.c
@@ -12,14 +12,16 @@ static void *cortex_a75_context_save(const void *arg)
{
if (midr_match(CORTEX_A75_MIDR) != 0)
cpuamu_context_save(CORTEX_A75_AMU_NR_COUNTERS);
- return 0;
+
+ return (void *)0;
}
static void *cortex_a75_context_restore(const void *arg)
{
if (midr_match(CORTEX_A75_MIDR) != 0)
cpuamu_context_restore(CORTEX_A75_AMU_NR_COUNTERS);
- return 0;
+
+ return (void *)0;
}
SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, cortex_a75_context_save);
diff --git a/lib/cpus/aarch64/cortex_ares_pubsub.c b/lib/cpus/aarch64/cortex_ares_pubsub.c
index c7d850a00..9566223f2 100644
--- a/lib/cpus/aarch64/cortex_ares_pubsub.c
+++ b/lib/cpus/aarch64/cortex_ares_pubsub.c
@@ -12,14 +12,16 @@ static void *cortex_ares_context_save(const void *arg)
{
if (midr_match(CORTEX_ARES_MIDR) != 0)
cpuamu_context_save(CORTEX_ARES_AMU_NR_COUNTERS);
- return 0;
+
+ return (void *)0;
}
static void *cortex_ares_context_restore(const void *arg)
{
if (midr_match(CORTEX_ARES_MIDR) != 0)
cpuamu_context_restore(CORTEX_ARES_AMU_NR_COUNTERS);
- return 0;
+
+ return (void *)0;
}
SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, cortex_ares_context_save);
diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c
index c679336c1..42603cb6d 100644
--- a/lib/cpus/errata_report.c
+++ b/lib/cpus/errata_report.c
@@ -12,6 +12,7 @@
#include <debug.h>
#include <errata_report.h>
#include <spinlock.h>
+#include <stdbool.h>
#include <utils.h>
#ifdef IMAGE_BL1
@@ -35,10 +36,10 @@
*/
int errata_needs_reporting(spinlock_t *lock, uint32_t *reported)
{
- int report_now;
+ bool report_now;
/* If already reported, return false. */
- if (*reported)
+ if (*reported != 0U)
return 0;
/*
@@ -46,7 +47,7 @@ int errata_needs_reporting(spinlock_t *lock, uint32_t *reported)
* report status to true.
*/
spin_lock(lock);
- report_now = !(*reported);
+ report_now = (*reported == 0U);
if (report_now)
*reported = 1;
spin_unlock(lock);
@@ -75,8 +76,8 @@ void errata_print_msg(unsigned int status, const char *cpu, const char *id)
assert(status < ARRAY_SIZE(errata_status_str));
- assert(cpu);
- assert(id);
+ assert(cpu != NULL);
+ assert(id != NULL);
msg = errata_status_str[status];
--
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