From 46e88703852958f9a212080724f2c6fdfb21fa1c Mon Sep 17 00:00:00 2001 From: Joel Hutton <joel.hutton@arm.com> Date: Wed, 10 Jan 2018 16:06:07 +0000 Subject: [PATCH] Add initial CPU support for Cortex-Helios Change-Id: Ic0486131c493632eadf329f80b0b5904aed5e4ef Signed-off-by: Joel Hutton <joel.hutton@arm.com> Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> --- include/lib/cpus/aarch64/cortex_helios.h | 29 ++++++++++++++++++++ lib/cpus/aarch64/cortex_helios.S | 34 ++++++++++++++++++++++++ 2 files changed, 63 insertions(+) create mode 100644 include/lib/cpus/aarch64/cortex_helios.h create mode 100644 lib/cpus/aarch64/cortex_helios.S diff --git a/include/lib/cpus/aarch64/cortex_helios.h b/include/lib/cpus/aarch64/cortex_helios.h new file mode 100644 index 000000000..1098a124e --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_helios.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CORTEX_HELIOS_H__ +#define __CORTEX_HELIOS_H__ + +#define CORTEX_HELIOS_MIDR U(0x410FD060) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_HELIOS_ECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_HELIOS_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions. + ******************************************************************************/ + +#define CORTEX_HELIOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* __CORTEX_HELIOS_H__ */ diff --git a/lib/cpus/aarch64/cortex_helios.S b/lib/cpus/aarch64/cortex_helios.S new file mode 100644 index 000000000..bcda74114 --- /dev/null +++ b/lib/cpus/aarch64/cortex_helios.S @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <arch.h> +#include <asm_macros.S> +#include <bl_common.h> +#include <cortex_helios.h> +#include <cpu_macros.S> +#include <debug.h> +#include <plat_macros.S> + +func cortex_helios_cpu_pwr_dwn + mrs x0, CORTEX_HELIOS_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_HELIOS_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_helios_cpu_pwr_dwn + +.section .rodata.cortex_helios_regs, "aS" +cortex_helios_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_helios_cpu_reg_dump + adr x6, cortex_helios_regs + mrs x8, CORTEX_HELIOS_ECTLR_EL1 + ret +endfunc cortex_helios_cpu_reg_dump + +declare_cpu_ops cortex_helios, CORTEX_HELIOS_MIDR, \ + CPU_NO_RESET_FUNC, \ + cortex_helios_cpu_pwr_dwn -- GitLab