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Commit 4731e8f0 authored by danh-arm's avatar danh-arm
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Merge pull request #295 from danh-arm/dh/plat-port-reorg 

ARM platform port reorganization
parents 6403a306 4a75b84a
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plat/arm/board/juno/juno_def.h 0 → 100644
View file @ 4731e8f0
/*
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __JUNO_DEF_H__
#define __JUNO_DEF_H__
/*******************************************************************************
* Juno memory map related constants
******************************************************************************/
/* Board revisions */
#define REV_JUNO_R0 0x1 /* Rev B */
#define REV_JUNO_R1 0x2 /* Rev C */
/* Bypass offset from start of NOR flash */
#define BL1_ROM_BYPASS_OFFSET 0x03EC0000
#define EMMC_BASE 0x0c000000
#define EMMC_SIZE 0x04000000
#define PSRAM_BASE 0x14000000
#define PSRAM_SIZE 0x02000000
/*******************************************************************************
* TZC-400 related constants
******************************************************************************/
#define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */
#define TZC400_NSAID_PCIE 1
#define TZC400_NSAID_HDLCD0 2
#define TZC400_NSAID_HDLCD1 3
#define TZC400_NSAID_USB 4
#define TZC400_NSAID_DMA330 5
#define TZC400_NSAID_THINLINKS 6
#define TZC400_NSAID_AP 9
#define TZC400_NSAID_GPU 10
#define TZC400_NSAID_SCP 11
#define TZC400_NSAID_CORESIGHT 12
/*******************************************************************************
* MMU-401 related constants
******************************************************************************/
#define MMU401_SSD_OFFSET 0x4000
#define MMU401_DMA330_BASE 0x7fb00000
#endif /* __JUNO_DEF_H__ */
plat/arm/board/juno/juno_security.c 0 → 100644
View file @ 4731e8f0
/*
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <mmio.h>
#include <plat_arm.h>
#include <soc_css.h>
#include "juno_def.h"
/*******************************************************************************
* Set up the MMU-401 SSD tables. The power-on configuration has all stream IDs
* assigned to Non-Secure except some for the DMA-330. Assign those back to the
* Non-Secure world as well, otherwise EL1 may end up erroneously generating
* (untranslated) Secure transactions if it turns the SMMU on.
******************************************************************************/
static void init_mmu401(void)
{
uint32_t reg = mmio_read_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET);
reg |= 0x1FF;
mmio_write_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET, reg);
}
/*******************************************************************************
* Initialize the secure environment.
******************************************************************************/
void plat_arm_security_setup(void)
{
/* Initialize the TrustZone Controller */
arm_tzc_setup();
/* Do ARM CSS SoC security setup */
soc_css_security_setup();
/* Initialize the SMMU SSD tables*/
init_mmu401();
}
plat/juno/platform.mk → plat/arm/board/juno/platform.mk
View file @ 4731e8f0
#
# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
......@@ -28,79 +28,18 @@
# POSSIBILITY OF SUCH DAMAGE.
#
# On Juno, the Secure Payload can be loaded either in Trusted SRAM (default) or
# Secure DRAM allocated by the TrustZone Controller.
PLAT_INCLUDES := -Iplat/arm/board/juno/include
PLAT_TSP_LOCATION := tsram
PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/aarch64/juno_helpers.S
ifeq (${PLAT_TSP_LOCATION}, tsram)
PLAT_TSP_LOCATION_ID := PLAT_TRUSTED_SRAM_ID
else ifeq (${PLAT_TSP_LOCATION}, dram)
PLAT_TSP_LOCATION_ID := PLAT_DRAM_ID
else
$(error "Unsupported PLAT_TSP_LOCATION value")
endif
BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S
# Process flags
$(eval $(call add_define,PLAT_TSP_LOCATION_ID))
BL2_SOURCES += plat/arm/board/juno/juno_security.c \
BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S
PLAT_INCLUDES := -Iplat/juno/include/
PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \
drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
lib/aarch64/xlat_tables.c \
plat/common/aarch64/plat_common.c \
plat/common/plat_gic.c \
plat/juno/plat_io_storage.c
BL1_SOURCES += drivers/arm/cci/cci.c \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
plat/common/aarch64/platform_up_stack.S \
plat/juno/bl1_plat_setup.c \
plat/juno/aarch64/bl1_plat_helpers.S \
plat/juno/aarch64/plat_helpers.S \
plat/juno/aarch64/juno_common.c
BL2_SOURCES += drivers/arm/tzc400/tzc400.c \
plat/common/aarch64/platform_up_stack.S \
plat/juno/bl2_plat_setup.c \
plat/juno/mhu.c \
plat/juno/plat_security.c \
plat/juno/aarch64/plat_helpers.S \
plat/juno/aarch64/juno_common.c \
plat/juno/scp_bootloader.c \
plat/juno/scpi.c
BL31_SOURCES += drivers/arm/cci/cci.c \
drivers/arm/gic/arm_gic.c \
drivers/arm/gic/gic_v2.c \
drivers/arm/gic/gic_v3.c \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
plat/common/aarch64/platform_mp_stack.S \
plat/juno/bl31_plat_setup.c \
plat/juno/mhu.c \
plat/juno/aarch64/plat_helpers.S \
plat/juno/aarch64/juno_common.c \
plat/juno/plat_pm.c \
plat/juno/plat_topology.c \
plat/juno/scpi.c
ifneq (${TRUSTED_BOARD_BOOT},0)
BL1_SOURCES += plat/juno/juno_trusted_boot.c
BL2_SOURCES += plat/juno/juno_trusted_boot.c
endif
ifneq (${RESET_TO_BL31},0)
$(error "Using BL3-1 as the reset vector is not supported on Juno. \
Please set RESET_TO_BL31 to 0.")
endif
NEED_BL30 := yes
# Enable workarounds for selected Cortex-A57 erratas.
ERRATA_A57_806969 := 0
......@@ -109,3 +48,8 @@ ERRATA_A57_813420 := 1
# Enable option to skip L1 data cache flush during the Cortex-A57 cluster
# power down sequence
SKIP_A57_L1_FLUSH_PWR_DWN := 1
include plat/arm/board/common/board_css.mk
include plat/arm/common/arm_common.mk
include plat/arm/soc/common/soc_css.mk
include plat/arm/css/common/css_common.mk
plat/juno/tsp/tsp-juno.mk → plat/arm/board/juno/tsp/tsp-juno.mk
View file @ 4731e8f0
#
# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
......@@ -28,10 +28,4 @@
# POSSIBILITY OF SUCH DAMAGE.
#
# TSP source files specific to Juno platform
BL32_SOURCES += drivers/arm/gic/arm_gic.c \
drivers/arm/gic/gic_v2.c \
plat/common/aarch64/platform_mp_stack.S \
plat/juno/aarch64/juno_common.c \
plat/juno/aarch64/plat_helpers.S \
plat/juno/tsp/tsp_plat_setup.c
include plat/arm/common/tsp/arm_tsp.mk
plat/juno/plat_security.c → plat/arm/common/aarch64/arm_common.c
View file @ 4731e8f0
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -27,94 +27,118 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <debug.h>
#include <arch.h>
#include <arch_helpers.h>
#include <cci.h>
#include <mmio.h>
#include <tzc400.h>
#include "juno_def.h"
#include <plat_arm.h>
#include <xlat_tables.h>
/*******************************************************************************
* Initialize the TrustZone Controller. Configure Region 0 with Secure RW access
* and allow Non-Secure masters full access
******************************************************************************/
static void init_tzc400(void)
{
tzc_init(TZC400_BASE);
/* Disable filters. */
tzc_disable_filters();
static const int cci_map[] = {
PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX,
PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX
};
/* Region 1 set to cover Non-Secure DRAM at 0x8000_0000. Apply the
* same configuration to all filters in the TZC. */
tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 1,
DRAM_NS_BASE, DRAM_NS_BASE + DRAM_NS_SIZE - 1,
TZC_REGION_S_NONE,
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT));
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak plat_get_ns_image_entrypoint
/* Region 2 set to cover Secure DRAM */
tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 2,
DRAM_SEC_BASE, DRAM_SEC_BASE + DRAM_SEC_SIZE - 1,
TZC_REGION_S_RDWR,
0);
/* Region 3 set to cover DRAM used by SCP for DDR retraining */
tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 3,
DRAM_SCP_BASE, DRAM_SCP_BASE + DRAM_SCP_SIZE - 1,
TZC_REGION_S_NONE,
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_SCP));
/*******************************************************************************
* Macro generating the code for the function setting up the pagetables as per
* the platform memory map & initialize the mmu, for the given exception level
******************************************************************************/
#if USE_COHERENT_MEM
#define DEFINE_CONFIGURE_MMU_EL(_el) \
void arm_configure_mmu_el##_el(unsigned long total_base, \
unsigned long total_size, \
unsigned long ro_start, \
unsigned long ro_limit, \
unsigned long coh_start, \
unsigned long coh_limit) \
{ \
mmap_add_region(total_base, total_base, \
total_size, \
MT_MEMORY | MT_RW | MT_SECURE); \
mmap_add_region(ro_start, ro_start, \
ro_limit - ro_start, \
MT_MEMORY | MT_RO | MT_SECURE); \
mmap_add_region(coh_start, coh_start, \
coh_limit - coh_start, \
MT_DEVICE | MT_RW | MT_SECURE); \
mmap_add(plat_arm_mmap); \
init_xlat_tables(); \
\
enable_mmu_el##_el(0); \
}
#else
#define DEFINE_CONFIGURE_MMU_EL(_el) \
void arm_configure_mmu_el##_el(unsigned long total_base, \
unsigned long total_size, \
unsigned long ro_start, \
unsigned long ro_limit) \
{ \
mmap_add_region(total_base, total_base, \
total_size, \
MT_MEMORY | MT_RW | MT_SECURE); \
mmap_add_region(ro_start, ro_start, \
ro_limit - ro_start, \
MT_MEMORY | MT_RO | MT_SECURE); \
mmap_add(plat_arm_mmap); \
init_xlat_tables(); \
\
enable_mmu_el##_el(0); \
}
#endif
/* Region 4 set to cover Non-Secure DRAM at 0x8_8000_0000 */
tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 4,
DRAM2_BASE, DRAM2_BASE + DRAM2_SIZE - 1,
TZC_REGION_S_NONE,
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) |
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT));
/* Define EL1 and EL3 variants of the function initialising the MMU */
DEFINE_CONFIGURE_MMU_EL(1)
DEFINE_CONFIGURE_MMU_EL(3)
/* Raise an exception if a NS device tries to access secure memory */
tzc_set_action(TZC_ACTION_ERR);
/* Enable filters. */
tzc_enable_filters();
unsigned long plat_get_ns_image_entrypoint(void)
{
return PLAT_ARM_NS_IMAGE_OFFSET;
}
/*******************************************************************************
* Set up the MMU-401 SSD tables. The power-on configuration has all stream IDs
* assigned to Non-Secure except some for the DMA-330. Assign those back to the
* Non-Secure world as well, otherwise EL1 may end up erroneously generating
* (untranslated) Secure transactions if it turns the SMMU on.
* Gets SPSR for BL32 entry
******************************************************************************/
static void init_mmu401(void)
uint32_t arm_get_spsr_for_bl32_entry(void)
{
uint32_t reg = mmio_read_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET);
reg |= 0x1FF;
mmio_write_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET, reg);
/*
* The Secure Payload Dispatcher service is responsible for
* setting the SPSR prior to entry into the BL3-2 image.
*/
return 0;
}
/*******************************************************************************
* Initialize the secure environment. At this moment only the TrustZone
* Controller is initialized.
* Gets SPSR for BL33 entry
******************************************************************************/
void plat_security_setup(void)
uint32_t arm_get_spsr_for_bl33_entry(void)
{
unsigned long el_status;
unsigned int mode;
uint32_t spsr;
/* Figure out what mode we enter the non-secure world in */
el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
el_status &= ID_AA64PFR0_ELX_MASK;
mode = (el_status) ? MODE_EL2 : MODE_EL1;
/*
* TODO: Consider the possibility of specifying the SPSR in
* the FIP ToC and allowing the platform to have a say as
* well.
*/
spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
return spsr;
}
void arm_cci_init(void)
{
/* Initialize the TrustZone Controller */
init_tzc400();
/* Initialize the SMMU SSD tables*/
init_mmu401();
cci_init(PLAT_ARM_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
}
plat/arm/common/aarch64/arm_helpers.S 0 → 100644
View file @ 4731e8f0
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <asm_macros.S>
#include <platform_def.h>
.globl plat_crash_console_init
.globl plat_crash_console_putc
/* ---------------------------------------------
* int plat_crash_console_init(void)
* Function to initialize the crash console
* without a C Runtime to print crash report.
* Clobber list : x0, x1, x2
* ---------------------------------------------
*/
func plat_crash_console_init
mov_imm x0, PLAT_ARM_CRASH_UART_BASE
mov_imm x1, PLAT_ARM_CRASH_UART_CLK_IN_HZ
mov_imm x2, ARM_CONSOLE_BAUDRATE
b console_core_init
endfunc plat_crash_console_init
/* ---------------------------------------------
* int plat_crash_console_putc(int c)
* Function to print a character on the crash
* console without a C Runtime.
* Clobber list : x1, x2
* ---------------------------------------------
*/
func plat_crash_console_putc
mov_imm x1, PLAT_ARM_CRASH_UART_BASE
b console_core_putc
endfunc plat_crash_console_putc
plat/fvp/bl1_fvp_setup.c → plat/arm/common/arm_bl1_setup.c
View file @ 4731e8f0
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -28,26 +28,17 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch_helpers.h>
#include <assert.h>
#include <arch.h>
#include <arm_def.h>
#include <bl_common.h>
#include <debug.h>
#include <cci.h>
#include <console.h>
#include <mmio.h>
#include <platform.h>
#include <platform_def.h>
#include <plat_arm.h>
#include "../../bl1/bl1_private.h"
#include "fvp_def.h"
#include "fvp_private.h"
#if USE_COHERENT_MEM
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
extern unsigned long __COHERENT_RAM_START__;
extern unsigned long __COHERENT_RAM_END__;
#if USE_COHERENT_MEM
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
......@@ -59,6 +50,15 @@ extern unsigned long __COHERENT_RAM_END__;
#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak bl1_early_platform_setup
#pragma weak bl1_plat_arch_setup
#pragma weak bl1_platform_setup
#pragma weak bl1_plat_sec_mem_layout
#pragma weak bl1_plat_set_bl2_ep_info
/* Data structure which holds the extents of the trusted SRAM for BL1*/
static meminfo_t bl1_tzram_layout;
......@@ -68,54 +68,53 @@ meminfo_t *bl1_plat_sec_mem_layout(void)
}
/*******************************************************************************
* Perform any BL1 specific platform actions.
* BL1 specific platform actions shared between ARM standard platforms.
******************************************************************************/
void bl1_early_platform_setup(void)
void arm_bl1_early_platform_setup(void)
{
const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
/* Initialize the console to provide early debug support */
console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
ARM_CONSOLE_BAUDRATE);
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = FVP_TRUSTED_SRAM_BASE;
bl1_tzram_layout.total_size = FVP_TRUSTED_SRAM_SIZE;
bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
/* Calculate how much RAM BL1 is using and how much remains free */
bl1_tzram_layout.free_base = FVP_TRUSTED_SRAM_BASE;
bl1_tzram_layout.free_size = FVP_TRUSTED_SRAM_SIZE;
bl1_tzram_layout.free_base = ARM_BL_RAM_BASE;
bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE;
reserve_mem(&bl1_tzram_layout.free_base,
&bl1_tzram_layout.free_size,
BL1_RAM_BASE,
bl1_size);
/* Initialize the platform config for future decision making */
fvp_config_setup();
}
/*******************************************************************************
* Function which will evaluate how much of the trusted ram has been gobbled
* up by BL1 and return the base and size of whats available for loading BL2.
* Its called after coherency and the MMU have been turned on.
******************************************************************************/
void bl1_platform_setup(void)
void bl1_early_platform_setup(void)
{
/* Initialise the IO layer and register platform IO devices */
fvp_io_setup();
arm_bl1_early_platform_setup();
/*
* Initialize CCI for this cluster during cold boot.
* No need for locks as no other CPU is active.
*/
arm_cci_init();
/*
* Enable CCI coherency for the primary CPU's cluster.
*/
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
}
/*******************************************************************************
* Perform the very early platform specific architecture setup here. At the
* moment this only does basic initialization. Later architectural setup
* (bl1_arch_setup()) does not do anything platform specific.
******************************************************************************/
void bl1_plat_arch_setup(void)
/******************************************************************************
* Perform the very early platform specific architecture setup shared between
* ARM standard platforms. This only does basic initialization. Later
* architectural setup (bl1_arch_setup()) does not do anything platform
* specific.
*****************************************************************************/
void arm_bl1_plat_arch_setup(void)
{
fvp_cci_init();
fvp_cci_enable();
fvp_configure_mmu_el3(bl1_tzram_layout.total_base,
arm_configure_mmu_el3(bl1_tzram_layout.total_base,
bl1_tzram_layout.total_size,
BL1_RO_BASE,
BL1_RO_LIMIT
......@@ -126,12 +125,31 @@ void bl1_plat_arch_setup(void)
);
}
void bl1_plat_arch_setup(void)
{
arm_bl1_plat_arch_setup();
}
/*
* Perform the platform specific architecture setup shared between
* ARM standard platforms.
*/
void arm_bl1_platform_setup(void)
{
/* Initialise the IO layer and register platform IO devices */
plat_arm_io_setup();
}
void bl1_platform_setup(void)
{
arm_bl1_platform_setup();
}
/*******************************************************************************
* Before calling this function BL2 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
* the entrypoint of BL2 and set SPSR and security state.
* On FVP we are only setting the security state, entrypoint
* On ARM standard platforms we only set the security state of the entrypoint
******************************************************************************/
void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image,
entry_point_info_t *bl2_ep)
......
plat/juno/bl2_plat_setup.c → plat/arm/common/arm_bl2_setup.c
View file @ 4731e8f0
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -29,28 +29,13 @@
*/
#include <arch_helpers.h>
#include <assert.h>
#include <arm_def.h>
#include <bl_common.h>
#include <console.h>
#include <debug.h>
#include <platform.h>
#include <platform_def.h>
#include <plat_arm.h>
#include <string.h>
#include "juno_def.h"
#include "juno_private.h"
#include "scp_bootloader.h"
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
* of trusted RAM
******************************************************************************/
extern unsigned long __RO_START__;
extern unsigned long __RO_END__;
#if USE_COHERENT_MEM
extern unsigned long __COHERENT_RAM_START__;
extern unsigned long __COHERENT_RAM_END__;
#endif
/*
* The next 2 constants identify the extents of the code & RO data region.
......@@ -73,15 +58,45 @@ extern unsigned long __COHERENT_RAM_END__;
#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
/* Data structure which holds the extents of the trusted RAM for BL2 */
static meminfo_t bl2_tzram_layout
__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE)));
/* Data structure which holds the extents of the trusted SRAM for BL2 */
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
/*******************************************************************************
* Structure which holds the arguments which need to be passed to BL3-1
* This structure represents the superset of information that is passed to
* BL3-1, e.g. while passing control to it from BL2, bl31_params
* and other platform specific params
******************************************************************************/
typedef struct bl2_to_bl31_params_mem {
bl31_params_t bl31_params;
image_info_t bl31_image_info;
image_info_t bl32_image_info;
image_info_t bl33_image_info;
entry_point_info_t bl33_ep_info;
entry_point_info_t bl32_ep_info;
entry_point_info_t bl31_ep_info;
} bl2_to_bl31_params_mem_t;
static bl2_to_bl31_params_mem_t bl31_params_mem;
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak bl2_early_platform_setup
#pragma weak bl2_platform_setup
#pragma weak bl2_plat_arch_setup
#pragma weak bl2_plat_sec_mem_layout
#pragma weak bl2_plat_get_bl31_params
#pragma weak bl2_plat_get_bl31_ep_info
#pragma weak bl2_plat_flush_bl31_params
#pragma weak bl2_plat_set_bl31_ep_info
#pragma weak bl2_plat_get_bl30_meminfo
#pragma weak bl2_plat_get_bl32_meminfo
#pragma weak bl2_plat_set_bl32_ep_info
#pragma weak bl2_plat_get_bl33_meminfo
#pragma weak bl2_plat_set_bl33_ep_info
meminfo_t *bl2_plat_sec_mem_layout(void)
{
return &bl2_tzram_layout;
......@@ -140,6 +155,13 @@ bl31_params_t *bl2_plat_get_bl31_params(void)
return bl2_to_bl31_params;
}
/* Flush the TF params and the TF plat params */
void bl2_plat_flush_bl31_params(void)
{
flush_dcache_range((unsigned long)&bl31_params_mem,
sizeof(bl2_to_bl31_params_mem_t));
}
/*******************************************************************************
* This function returns a pointer to the shared memory that the platform
* has kept to point to entry point information of BL31 to BL2
......@@ -147,179 +169,146 @@ bl31_params_t *bl2_plat_get_bl31_params(void)
struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
{
#if DEBUG
bl31_params_mem.bl31_ep_info.args.arg1 = JUNO_BL31_PLAT_PARAM_VAL;
bl31_params_mem.bl31_ep_info.args.arg1 = ARM_BL31_PLAT_PARAM_VAL;
#endif
return &bl31_params_mem.bl31_ep_info;
}
/*******************************************************************************
* BL1 has passed the extents of the trusted RAM that should be visible to BL2
* in x0. This memory layout is sitting at the base of the free trusted RAM.
* Copy it to a safe loaction before its reclaimed by later BL2 functionality.
* BL1 has passed the extents of the trusted SRAM that should be visible to BL2
* in x0. This memory layout is sitting at the base of the free trusted SRAM.
* Copy it to a safe location before its reclaimed by later BL2 functionality.
******************************************************************************/
void bl2_early_platform_setup(meminfo_t *mem_layout)
void arm_bl2_early_platform_setup(meminfo_t *mem_layout)
{
/* Initialize the console to provide early debug support */
console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE);
console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
ARM_CONSOLE_BAUDRATE);
/* Setup the BL2 memory layout */
bl2_tzram_layout = *mem_layout;
/* Initialise the IO layer and register platform IO devices */
io_setup();
plat_arm_io_setup();
}
/*******************************************************************************
* Perform platform specific setup, i.e. initialize the IO layer, load BL3-0
* image and initialise the memory location to use for passing arguments to
* BL3-1.
******************************************************************************/
void bl2_platform_setup(void)
void bl2_early_platform_setup(meminfo_t *mem_layout)
{
arm_bl2_early_platform_setup(mem_layout);
}
/*
* Perform ARM standard platform setup.
*/
void arm_bl2_platform_setup(void)
{
/* Initialize the secure environment */
plat_security_setup();
plat_arm_security_setup();
}
/* Flush the TF params and the TF plat params */
void bl2_plat_flush_bl31_params(void)
void bl2_platform_setup(void)
{
flush_dcache_range((unsigned long)&bl31_params_mem,
sizeof(bl2_to_bl31_params_mem_t));
arm_bl2_platform_setup();
}
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way.
* moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/
void bl2_plat_arch_setup(void)
void arm_bl2_plat_arch_setup(void)
{
configure_mmu_el1(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
BL2_RO_BASE,
BL2_RO_LIMIT
arm_configure_mmu_el1(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
BL2_RO_BASE,
BL2_RO_LIMIT
#if USE_COHERENT_MEM
, BL2_COHERENT_RAM_BASE,
BL2_COHERENT_RAM_LIMIT
, BL2_COHERENT_RAM_BASE,
BL2_COHERENT_RAM_LIMIT
#endif
);
);
}
/*******************************************************************************
* Populate the extents of memory available for loading BL3-0, i.e. anywhere
* in trusted RAM as long as it doesn't overwrite BL2.
******************************************************************************/
void bl2_plat_get_bl30_meminfo(meminfo_t *bl30_meminfo)
void bl2_plat_arch_setup(void)
{
*bl30_meminfo = bl2_tzram_layout;
arm_bl2_plat_arch_setup();
}
/*******************************************************************************
* Transfer BL3-0 from Trusted RAM using the SCP Download protocol.
* Return 0 on success, -1 otherwise.
* Populate the extents of memory available for loading BL3-0 (if used),
* i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2.
******************************************************************************/
int bl2_plat_handle_bl30(image_info_t *bl30_image_info)
void bl2_plat_get_bl30_meminfo(meminfo_t *bl30_meminfo)
{
int ret;
ret = scp_bootloader_transfer((void *)bl30_image_info->image_base,
bl30_image_info->image_size);
if (ret == 0)
INFO("BL2: BL3-0 transferred to SCP\n\r");
else
ERROR("BL2: BL3-0 transfer failure\n\r");
return ret;
*bl30_meminfo = bl2_tzram_layout;
}
/*******************************************************************************
* Before calling this function BL31 is loaded in memory and its entrypoint
* Before calling this function BL3-1 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
* the entrypoint of BL31 and set SPSR and security state.
* On Juno we are only setting the security state, entrypoint
* the entrypoint of BL3-1 and set SPSR and security state.
* On ARM standard platforms we only set the security state of the entrypoint
******************************************************************************/
void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
entry_point_info_t *bl31_ep_info)
entry_point_info_t *bl31_ep_info)
{
SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);
DISABLE_ALL_EXCEPTIONS);
}
/*******************************************************************************
* Before calling this function BL32 is loaded in memory and its entrypoint
* Before calling this function BL3-2 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
* the entrypoint of BL32 and set SPSR and security state.
* On Juno we are only setting the security state, entrypoint
* the entrypoint of BL3-2 and set SPSR and security state.
* On ARM standard platforms we only set the security state of the entrypoint
******************************************************************************/
void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
entry_point_info_t *bl32_ep_info)
entry_point_info_t *bl32_ep_info)
{
SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
/*
* The Secure Payload Dispatcher service is responsible for
* setting the SPSR prior to entry into the BL32 image.
*/
bl32_ep_info->spsr = 0;
bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry();
}
/*******************************************************************************
* Before calling this function BL33 is loaded in memory and its entrypoint
* Before calling this function BL3-3 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
* the entrypoint of BL33 and set SPSR and security state.
* On Juno we are only setting the security state, entrypoint
* the entrypoint of BL3-3 and set SPSR and security state.
* On ARM standard platforms we only set the security state of the entrypoint
******************************************************************************/
void bl2_plat_set_bl33_ep_info(image_info_t *image,
entry_point_info_t *bl33_ep_info)
entry_point_info_t *bl33_ep_info)
{
unsigned long el_status;
unsigned int mode;
/* Figure out what mode we enter the non-secure world in */
el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
el_status &= ID_AA64PFR0_ELX_MASK;
if (el_status)
mode = MODE_EL2;
else
mode = MODE_EL1;
/*
* TODO: Consider the possibility of specifying the SPSR in
* the FIP ToC and allowing the platform to have a say as
* well.
*/
bl33_ep_info->spsr = SPSR_64(mode, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);
SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry();
}
/*******************************************************************************
* Populate the extents of memory available for loading BL3-2
* Populate the extents of memory available for loading BL32
******************************************************************************/
void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
{
/*
* Populate the extents of memory available for loading BL3-2.
* Populate the extents of memory available for loading BL32.
*/
bl32_meminfo->total_base = BL32_BASE;
bl32_meminfo->free_base = BL32_BASE;
bl32_meminfo->total_size =
(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
bl32_meminfo->free_size =
(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
}
/*******************************************************************************
* Populate the extents of memory available for loading BL3-3
* Populate the extents of memory available for loading BL33
******************************************************************************/
void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
{
bl33_meminfo->total_base = DRAM_NS_BASE;
bl33_meminfo->total_size = DRAM_NS_SIZE;
bl33_meminfo->free_base = DRAM_NS_BASE;
bl33_meminfo->free_size = DRAM_NS_SIZE;
bl33_meminfo->total_base = ARM_NS_DRAM1_BASE;
bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE;
bl33_meminfo->free_base = ARM_NS_DRAM1_BASE;
bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE;
}
plat/fvp/bl31_fvp_setup.c → plat/arm/common/arm_bl31_setup.c
View file @ 4731e8f0
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -30,30 +30,17 @@
#include <arch.h>
#include <arch_helpers.h>
#include <arm_def.h>
#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <bl31.h>
#include <cci.h>
#include <console.h>
#include <debug.h>
#include <mmio.h>
#include <plat_arm.h>
#include <platform.h>
#include <stddef.h>
#include "drivers/pwrc/fvp_pwrc.h"
#include "fvp_def.h"
#include "fvp_private.h"
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
extern unsigned long __RO_START__;
extern unsigned long __RO_END__;
extern unsigned long __BL31_END__;
#if USE_COHERENT_MEM
extern unsigned long __COHERENT_RAM_START__;
extern unsigned long __COHERENT_RAM_END__;
#endif
/*
* The next 3 constants identify the extents of the code, RO data region and the
......@@ -78,82 +65,65 @@ extern unsigned long __COHERENT_RAM_END__;
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
#if RESET_TO_BL31
/*
* Placeholder variables for copying the arguments that have been passed to
* BL3-1 from BL2.
*/
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
#else
/*******************************************************************************
* Reference to structure which holds the arguments that have been passed to
* BL31 from BL2.
******************************************************************************/
static bl31_params_t *bl2_to_bl31_params;
#endif
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak bl31_early_platform_setup
#pragma weak bl31_platform_setup
#pragma weak bl31_plat_arch_setup
#pragma weak bl31_plat_get_next_image_ep_info
#pragma weak plat_get_syscnt_freq
/*******************************************************************************
* Return a pointer to the 'entry_point_info' structure of the next image for the
* security state specified. BL33 corresponds to the non-secure image type
* while BL32 corresponds to the secure image type. A NULL pointer is returned
* security state specified. BL3-3 corresponds to the non-secure image type
* while BL3-2 corresponds to the secure image type. A NULL pointer is returned
* if the image does not exist.
******************************************************************************/
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
{
#if RESET_TO_BL31
assert(sec_state_is_valid(type));
if (type == NON_SECURE)
return &bl33_image_ep_info;
else
return &bl32_image_ep_info;
#else
entry_point_info_t *next_image_info;
assert(sec_state_is_valid(type));
next_image_info = (type == NON_SECURE) ?
bl2_to_bl31_params->bl33_ep_info :
bl2_to_bl31_params->bl32_ep_info;
/* None of the images on this platform can have 0x0 as the entrypoint */
next_image_info = (type == NON_SECURE)
? &bl33_image_ep_info : &bl32_image_ep_info;
/*
* None of the images on the ARM development platforms can have 0x0
* as the entrypoint
*/
if (next_image_info->pc)
return next_image_info;
else
return NULL;
#endif
}
/*******************************************************************************
* Perform any BL31 specific platform actions. Here is an opportunity to copy
* parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
* are lost (potentially). This needs to be done before the MMU is initialized
* so that the memory layout can be used while creating page tables. On the FVP
* we know that BL2 has populated the parameters in secure DRAM. So we just use
* the reference passed in 'from_bl2' instead of copying. The 'data' parameter
* is not used since all the information is contained in 'from_bl2'. Also, BL2
* has flushed this information to memory, so we are guaranteed to pick up good
* data
* Perform any BL3-1 early platform setup common to ARM standard platforms.
* Here is an opportunity to copy parameters passed by the calling EL (S-EL1
* in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be
* done before the MMU is initialized so that the memory layout can be used
* while creating page tables. BL2 has flushed this information to memory, so
* we are guaranteed to pick up good data.
******************************************************************************/
void bl31_early_platform_setup(bl31_params_t *from_bl2,
void arm_bl31_early_platform_setup(bl31_params_t *from_bl2,
void *plat_params_from_bl2)
{
/* Initialize the console to provide early debug support */
console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
/* Initialize the platform config for future decision making */
fvp_config_setup();
console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
ARM_CONSOLE_BAUDRATE);
#if RESET_TO_BL31
/* There are no parameters from BL2 if BL31 is a reset vector */
/* There are no parameters from BL2 if BL3-1 is a reset vector */
assert(from_bl2 == NULL);
assert(plat_params_from_bl2 == NULL);
/*
* Do initial security configuration to allow DRAM/device access. On
* Base FVP only DRAM security is programmable (via TrustZone), but
* other platforms might have more programmable security devices
* present.
*/
fvp_security_setup();
/* Populate entry point information for BL3-2 and BL3-3 */
SET_PARAM_HEAD(&bl32_image_ep_info,
PARAM_EP,
......@@ -161,86 +131,118 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
0);
SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
bl32_image_ep_info.pc = BL32_BASE;
bl32_image_ep_info.spsr = fvp_get_spsr_for_bl32_entry();
bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
SET_PARAM_HEAD(&bl33_image_ep_info,
PARAM_EP,
VERSION_1,
0);
/*
* Tell BL31 where the non-trusted software image
* Tell BL3-1 where the non-trusted software image
* is located and the entry state information
*/
bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
bl33_image_ep_info.spsr = fvp_get_spsr_for_bl33_entry();
bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
#else
/* Check params passed from BL2 should not be NULL,
* We are not checking plat_params_from_bl2 as NULL as we are not
* using it on FVP
/*
* Check params passed from BL2 should not be NULL,
*/
assert(from_bl2 != NULL);
assert(from_bl2->h.type == PARAM_BL31);
assert(from_bl2->h.version >= VERSION_1);
/*
* In debug builds, we pass a special value in 'plat_params_from_bl2'
* to verify platform parameters from BL2 to BL3-1.
* In release builds, it's not used.
*/
assert(((unsigned long long)plat_params_from_bl2) ==
ARM_BL31_PLAT_PARAM_VAL);
bl2_to_bl31_params = from_bl2;
assert(((unsigned long)plat_params_from_bl2) == FVP_BL31_PLAT_PARAM_VAL);
/*
* Copy BL3-2 and BL3-3 entry point information.
* They are stored in Secure RAM, in BL2's address space.
*/
bl32_image_ep_info = *from_bl2->bl32_ep_info;
bl33_image_ep_info = *from_bl2->bl33_ep_info;
#endif
}
void bl31_early_platform_setup(bl31_params_t *from_bl2,
void *plat_params_from_bl2)
{
arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2);
/*
* Initialize CCI for this cluster during cold boot.
* No need for locks as no other CPU is active.
*/
arm_cci_init();
#if RESET_TO_BL31
/*
* Enable CCI coherency for the primary CPU's cluster
* (if earlier BL has not already done so).
* Platform specific PSCI code will enable coherency for other
* clusters.
*/
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
#endif /* RESET_TO_BL31 */
}
/*******************************************************************************
* Initialize the gic, configure the CLCD and zero out variables needed by the
* secondaries to boot up correctly.
* Perform any BL3-1 platform setup common to ARM standard platforms
******************************************************************************/
void bl31_platform_setup(void)
void arm_bl31_platform_setup(void)
{
unsigned int reg_val;
/* Initialize the gic cpu and distributor interfaces */
fvp_gic_init();
plat_arm_gic_init();
arm_gic_setup();
#if RESET_TO_BL31
/*
* TODO: Configure the CLCD before handing control to
* linux. Need to see if a separate driver is needed
* instead.
* Do initial security configuration to allow DRAM/device access
* (if earlier BL has not already done so).
*/
mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGDATA, 0);
mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL,
(1ull << 31) | (1 << 30) | (7 << 20) | (0 << 16));
plat_arm_security_setup();
#endif /* RESET_TO_BL31 */
/* Enable and initialize the System level generic timer */
mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN);
mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
CNTCR_FCREQ(0) | CNTCR_EN);
/* Allow access to the System counter timer module */
reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val);
mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
reg_val = (1 << CNTNSAR_NS_SHIFT(0)) | (1 << CNTNSAR_NS_SHIFT(1));
mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val);
reg_val = (1 << CNTNSAR_NS_SHIFT(1));
mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
/* Intialize the power controller */
fvp_pwrc_setup();
/* Initialize power controller before setting up topology */
plat_arm_pwrc_setup();
/* Topologies are best known to the platform. */
fvp_setup_topology();
plat_arm_topology_setup();
}
void bl31_platform_setup(void)
{
arm_bl31_platform_setup();
}
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
void arm_bl31_plat_arch_setup(void)
{
fvp_cci_init();
#if RESET_TO_BL31
fvp_cci_enable();
#endif
fvp_configure_mmu_el3(BL31_RO_BASE,
arm_configure_mmu_el3(BL31_RO_BASE,
(BL31_END - BL31_RO_BASE),
BL31_RO_BASE,
BL31_RO_LIMIT
......@@ -250,3 +252,22 @@ void bl31_plat_arch_setup(void)
#endif
);
}
void bl31_plat_arch_setup(void)
{
arm_bl31_plat_arch_setup();
}
uint64_t plat_get_syscnt_freq(void)
{
uint64_t counter_base_frequency;
/* Read the frequency from Frequency modes table */
counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
/* The first entry of the frequency modes table must not be 0 */
if (counter_base_frequency == 0)
panic();
return counter_base_frequency;
}
plat/fvp/platform.mk → plat/arm/common/arm_common.mk
View file @ 4731e8f0
#
# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
......@@ -28,69 +28,58 @@
# POSSIBILITY OF SUCH DAMAGE.
#
# On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
# On ARM standard platorms, the TSP can execute from Trusted SRAM, Trusted
# DRAM (if available) or the TZC secured area of DRAM.
# Trusted SRAM is the default.
FVP_TSP_RAM_LOCATION := tsram
ifeq (${FVP_TSP_RAM_LOCATION}, tsram)
FVP_TSP_RAM_LOCATION_ID := FVP_TRUSTED_SRAM_ID
else ifeq (${FVP_TSP_RAM_LOCATION}, tdram)
FVP_TSP_RAM_LOCATION_ID := FVP_TRUSTED_DRAM_ID
else ifeq (${FVP_TSP_RAM_LOCATION}, dram)
FVP_TSP_RAM_LOCATION_ID := FVP_DRAM_ID
ARM_TSP_RAM_LOCATION := tsram
ifeq (${ARM_TSP_RAM_LOCATION}, tsram)
ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_SRAM_ID
else ifeq (${ARM_TSP_RAM_LOCATION}, tdram)
ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_DRAM_ID
else ifeq (${ARM_TSP_RAM_LOCATION}, dram)
ARM_TSP_RAM_LOCATION_ID = ARM_DRAM_ID
else
$(error "Unsupported FVP_TSP_RAM_LOCATION value")
$(error "Unsupported ARM_TSP_RAM_LOCATION value")
endif
# Process flags
$(eval $(call add_define,FVP_TSP_RAM_LOCATION_ID))
$(eval $(call add_define,ARM_TSP_RAM_LOCATION_ID))
PLAT_INCLUDES += -Iinclude/plat/arm/common \
-Iinclude/plat/arm/common/aarch64
PLAT_INCLUDES := -Iplat/fvp/include/
PLAT_BL_COMMON_SOURCES += lib/aarch64/xlat_tables.c \
plat/arm/common/aarch64/arm_common.c \
plat/arm/common/aarch64/arm_helpers.S \
plat/common/aarch64/plat_common.c
PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \
BL1_SOURCES += drivers/arm/cci/cci.c \
drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_semihosting.c \
drivers/io/io_storage.c \
lib/aarch64/xlat_tables.c \
lib/semihosting/semihosting.c \
lib/semihosting/aarch64/semihosting_call.S \
plat/common/aarch64/plat_common.c \
plat/fvp/fvp_io_storage.c
BL1_SOURCES += drivers/arm/cci/cci.c \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
plat/common/aarch64/platform_up_stack.S \
plat/fvp/bl1_fvp_setup.c \
plat/fvp/aarch64/fvp_common.c \
plat/fvp/aarch64/fvp_helpers.S
plat/arm/common/arm_bl1_setup.c \
plat/arm/common/arm_io_storage.c \
plat/common/aarch64/platform_up_stack.S
BL2_SOURCES += drivers/arm/tzc400/tzc400.c \
plat/common/aarch64/platform_up_stack.S \
plat/fvp/bl2_fvp_setup.c \
plat/fvp/fvp_security.c \
plat/fvp/aarch64/fvp_common.c
drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
plat/arm/common/arm_bl2_setup.c \
plat/arm/common/arm_io_storage.c \
plat/arm/common/arm_security.c \
plat/common/aarch64/platform_up_stack.S
BL31_SOURCES += drivers/arm/cci/cci.c \
drivers/arm/gic/arm_gic.c \
drivers/arm/gic/gic_v2.c \
drivers/arm/gic/gic_v3.c \
drivers/arm/tzc400/tzc400.c \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
plat/arm/common/arm_bl31_setup.c \
plat/arm/common/arm_pm.c \
plat/arm/common/arm_security.c \
plat/arm/common/arm_topology.c \
plat/common/plat_gic.c \
plat/common/aarch64/platform_mp_stack.S \
plat/fvp/bl31_fvp_setup.c \
plat/fvp/fvp_pm.c \
plat/fvp/fvp_security.c \
plat/fvp/fvp_topology.c \
plat/fvp/aarch64/fvp_helpers.S \
plat/fvp/aarch64/fvp_common.c \
plat/fvp/drivers/pwrc/fvp_pwrc.c
ifneq (${TRUSTED_BOARD_BOOT},0)
BL1_SOURCES += plat/fvp/fvp_trusted_boot.c
BL2_SOURCES += plat/fvp/fvp_trusted_boot.c
endif
plat/common/aarch64/platform_mp_stack.S
plat/juno/plat_io_storage.c → plat/arm/common/arm_io_storage.c
View file @ 4731e8f0
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -27,7 +27,6 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <assert.h>
#include <debug.h>
#include <io_driver.h>
......@@ -40,16 +39,13 @@
/* IO devices */
static const io_dev_connector_t *fip_dev_con;
static uintptr_t fip_dev_spec;
static uintptr_t fip_dev_handle;
static const io_dev_connector_t *memmap_dev_con;
static uintptr_t memmap_dev_spec;
static uintptr_t memmap_init_params;
static uintptr_t memmap_dev_handle;
static const io_block_spec_t fip_block_spec = {
.offset = FLASH_BASE,
.length = FLASH_SIZE
.offset = PLAT_ARM_FIP_BASE,
.length = PLAT_ARM_FIP_MAX_SIZE
};
static const io_file_spec_t bl2_file_spec = {
......@@ -228,15 +224,24 @@ static const struct plat_io_policy policies[] = {
};
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak plat_arm_io_setup
#pragma weak plat_arm_get_alt_image_source
static int open_fip(const uintptr_t spec)
{
int result = IO_FAIL;
int result;
uintptr_t local_image_handle;
/* See if a Firmware Image Package is available */
result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_NAME);
if (result == IO_SUCCESS) {
INFO("Using FIP\n");
/*TODO: Check image defined in spec is present in FIP. */
result = io_open(fip_dev_handle, spec, &local_image_handle);
if (result == IO_SUCCESS) {
VERBOSE("Using FIP\n");
io_close(local_image_handle);
}
}
return result;
}
......@@ -244,25 +249,25 @@ static int open_fip(const uintptr_t spec)
static int open_memmap(const uintptr_t spec)
{
int result = IO_FAIL;
int result;
uintptr_t local_image_handle;
result = io_dev_init(memmap_dev_handle, memmap_init_params);
result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL);
if (result == IO_SUCCESS) {
result = io_open(memmap_dev_handle, spec, &local_image_handle);
if (result == IO_SUCCESS) {
/* INFO("Using Memmap IO\n"); */
VERBOSE("Using Memmap\n");
io_close(local_image_handle);
}
}
return result;
}
void io_setup(void)
void arm_io_setup(void)
{
int io_result = IO_FAIL;
int io_result;
/* Register the IO devices on this platform */
io_result = register_io_dev_fip(&fip_dev_con);
assert(io_result == IO_SUCCESS);
......@@ -270,10 +275,11 @@ void io_setup(void)
assert(io_result == IO_SUCCESS);
/* Open connections to devices and cache the handles */
io_result = io_dev_open(fip_dev_con, fip_dev_spec, &fip_dev_handle);
io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
&fip_dev_handle);
assert(io_result == IO_SUCCESS);
io_result = io_dev_open(memmap_dev_con, memmap_dev_spec,
io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
&memmap_dev_handle);
assert(io_result == IO_SUCCESS);
......@@ -281,6 +287,18 @@ void io_setup(void)
(void)io_result;
}
void plat_arm_io_setup(void)
{
arm_io_setup();
}
int plat_arm_get_alt_image_source(
const uintptr_t image_spec __attribute__((unused)),
uintptr_t *dev_handle __attribute__((unused)))
{
/* By default do not try an alternative */
return IO_FAIL;
}
/* Return an IO device handle and specification which can be used to access
* an image. Use this to enforce platform load policy */
......@@ -301,6 +319,14 @@ int plat_get_image_source(const char *image_name, uintptr_t *dev_handle,
*dev_handle = *(policy->dev_handle);
break;
}
VERBOSE("Trying alternative IO\n");
result = plat_arm_get_alt_image_source(
policy->image_spec,
dev_handle);
if (result == IO_SUCCESS) {
*image_spec = policy->image_spec;
break;
}
}
policy++;
}
......
plat/arm/common/arm_pm.c 0 → 100644
View file @ 4731e8f0
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch_helpers.h>
#include <assert.h>
#include <errno.h>
#include <psci.h>
/*******************************************************************************
* ARM standard platform utility function which is used to determine if any
* platform actions should be performed for the specified affinity instance
* given its state. Nothing needs to be done if the 'state' is not off or if
* this is not the highest affinity level which will enter the 'state'.
******************************************************************************/
int32_t arm_do_affinst_actions(unsigned int afflvl, unsigned int state)
{
unsigned int max_phys_off_afflvl;
assert(afflvl <= MPIDR_AFFLVL1);
if (state != PSCI_STATE_OFF)
return -EAGAIN;
/*
* Find the highest affinity level which will be suspended and postpone
* all the platform specific actions until that level is hit.
*/
max_phys_off_afflvl = psci_get_max_phys_off_afflvl();
assert(max_phys_off_afflvl != PSCI_INVALID_DATA);
if (afflvl != max_phys_off_afflvl)
return -EAGAIN;
return 0;
}
/*******************************************************************************
* ARM standard platform handler called to check the validity of the power state
* parameter.
******************************************************************************/
int arm_validate_power_state(unsigned int power_state)
{
/* Sanity check the requested state */
if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) {
/*
* It's possible to enter standby only on affinity level 0
* (i.e. a CPU on ARM standard platforms).
* Ignore any other affinity level.
*/
if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0)
return PSCI_E_INVALID_PARAMS;
}
/*
* We expect the 'state id' to be zero.
*/
if (psci_get_pstate_id(power_state))
return PSCI_E_INVALID_PARAMS;
return PSCI_E_SUCCESS;
}
plat/arm/common/arm_security.c 0 → 100644
View file @ 4731e8f0
/*
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arm_def.h>
#include <debug.h>
#include <platform_def.h>
#include <tzc400.h>
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak plat_arm_security_setup
/*******************************************************************************
* Initialize the TrustZone Controller for ARM standard platforms.
* Configure Region 0 with no access, Region 1 with secure access only, and
* the remaining DRAM regions access from the given Non-Secure masters.
******************************************************************************/
void arm_tzc_setup(void)
{
INFO("Configuring TrustZone Controller\n");
tzc_init(ARM_TZC_BASE);
/* Disable filters. */
tzc_disable_filters();
/* Region 0 set to no access by default */
tzc_configure_region0(TZC_REGION_S_NONE, 0);
/* Region 1 set to cover Secure part of DRAM */
tzc_configure_region(PLAT_ARM_TZC_FILTERS, 1,
ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END,
TZC_REGION_S_RDWR,
0);
/* Region 2 set to cover Non-Secure access to 1st DRAM address range.
* Apply the same configuration to given filters in the TZC. */
tzc_configure_region(PLAT_ARM_TZC_FILTERS, 2,
ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END,
TZC_REGION_S_NONE,
PLAT_ARM_TZC_NS_DEV_ACCESS);
/* Region 3 set to cover Non-Secure access to 2nd DRAM address range */
tzc_configure_region(PLAT_ARM_TZC_FILTERS, 3,
ARM_DRAM2_BASE, ARM_DRAM2_END,
TZC_REGION_S_NONE,
PLAT_ARM_TZC_NS_DEV_ACCESS);
/*
* Raise an exception if a NS device tries to access secure memory
* TODO: Add interrupt handling support.
*/
tzc_set_action(TZC_ACTION_ERR);
/* Enable filters. */
tzc_enable_filters();
}
void plat_arm_security_setup(void)
{
arm_tzc_setup();
}
plat/juno/plat_topology.c → plat/arm/common/arm_topology.c
View file @ 4731e8f0
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -28,8 +28,18 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <platform_def.h>
#include <arch.h>
#include <psci.h>
#include <platform_def.h>
/*
* Weak definitions use fixed topology. Strong definitions could make topology
* configurable
*/
#pragma weak plat_get_aff_count
#pragma weak plat_get_aff_state
#pragma weak plat_arm_topology_setup
unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr)
{
......@@ -38,9 +48,10 @@ unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr)
return 1;
if (aff_lvl == MPIDR_AFFLVL1)
return 2; /* We have two clusters */
return ARM_CLUSTER_COUNT;
return mpidr & 0x100 ? 4 : 2; /* 4 cpus in cluster 1, 2 in cluster 0 */
return mpidr & 0x100 ? PLAT_ARM_CLUSTER1_CORE_COUNT :
PLAT_ARM_CLUSTER0_CORE_COUNT;
}
unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr)
......@@ -48,8 +59,6 @@ unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr)
return aff_lvl <= MPIDR_AFFLVL1 ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT;
}
int plat_setup_topology(void)
void plat_arm_topology_setup(void)
{
/* Juno todo: Make topology configurable via SCC */
return 0;
}
plat/arm/common/tsp/arm_tsp.mk 0 → 100644
View file @ 4731e8f0
#
# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# Redistributions of source code must retain the above copyright notice, this
# list of conditions and the following disclaimer.
#
# Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# Neither the name of ARM nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific
# prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# TSP source files common to ARM standard platforms
BL32_SOURCES += drivers/arm/gic/arm_gic.c \
drivers/arm/gic/gic_v2.c \
plat/arm/common/tsp/arm_tsp_setup.c \
plat/common/aarch64/platform_mp_stack.S \
plat/common/plat_gic.c
plat/fvp/tsp/tsp_fvp_setup.c → plat/arm/common/tsp/arm_tsp_setup.c
View file @ 4731e8f0
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -28,24 +28,13 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arm_def.h>
#include <bl_common.h>
#include <console.h>
#include <platform_def.h>
#include <platform_tsp.h>
#include "../fvp_def.h"
#include "../fvp_private.h"
#include <plat_arm.h>
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
extern unsigned long __RO_START__;
extern unsigned long __RO_END__;
extern unsigned long __BL32_END__;
#if USE_COHERENT_MEM
extern unsigned long __COHERENT_RAM_START__;
extern unsigned long __COHERENT_RAM_END__;
#endif
/*
* The next 3 constants identify the extents of the code & RO data region and
......@@ -70,19 +59,29 @@ extern unsigned long __COHERENT_RAM_END__;
#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak tsp_early_platform_setup
#pragma weak tsp_platform_setup
#pragma weak tsp_plat_arch_setup
/*******************************************************************************
* Initialize the UART
******************************************************************************/
void tsp_early_platform_setup(void)
void arm_tsp_early_platform_setup(void)
{
/*
* Initialize a different console than already in use to display
* messages from TSP
*/
console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE);
console_init(PLAT_ARM_TSP_UART_BASE, PLAT_ARM_TSP_UART_CLK_IN_HZ,
ARM_CONSOLE_BAUDRATE);
}
/* Initialize the platform config for future decision making */
fvp_config_setup();
void tsp_early_platform_setup(void)
{
arm_tsp_early_platform_setup();
}
/*******************************************************************************
......@@ -90,7 +89,7 @@ void tsp_early_platform_setup(void)
******************************************************************************/
void tsp_platform_setup(void)
{
fvp_gic_init();
plat_arm_gic_init();
}
/*******************************************************************************
......@@ -99,7 +98,7 @@ void tsp_platform_setup(void)
******************************************************************************/
void tsp_plat_arch_setup(void)
{
fvp_configure_mmu_el1(BL32_RO_BASE,
arm_configure_mmu_el1(BL32_RO_BASE,
(BL32_END - BL32_RO_BASE),
BL32_RO_BASE,
BL32_RO_LIMIT
......
plat/juno/aarch64/bl1_plat_helpers.S → plat/arm/css/common/aarch64/css_helpers.S
View file @ 4731e8f0
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -27,33 +27,17 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <asm_macros.S>
#include "../juno_def.h"
#include <cpu_macros.S>
#include <css_def.h>
.globl platform_is_primary_cpu
.globl platform_get_entrypoint
.globl platform_cold_boot_init
.globl plat_secondary_cold_boot_setup
.weak plat_secondary_cold_boot_setup
.weak platform_get_entrypoint
.weak platform_mem_init
.globl platform_get_core_pos
.weak platform_is_primary_cpu
/* -----------------------------------------------------
* unsigned int platform_is_primary_cpu (unsigned int mpid);
*
* Given the mpidr say whether this cpu is the primary
* cpu (applicable ony after a cold boot)
* -----------------------------------------------------
*/
func platform_is_primary_cpu
mov x9, x30
bl platform_get_core_pos
ldr x1, =SCP_BOOT_CFG_ADDR
ldr x1, [x1]
ubfx x1, x1, #PRIMARY_CPU_SHIFT, #PRIMARY_CPU_MASK
cmp x0, x1
cset x0, eq
ret x9
endfunc platform_is_primary_cpu
/* -----------------------------------------------------
* void plat_secondary_cold_boot_setup (void);
......@@ -65,12 +49,11 @@ endfunc platform_is_primary_cpu
* -----------------------------------------------------
*/
func plat_secondary_cold_boot_setup
/* Juno todo: Implement secondary CPU cold boot setup on Juno */
/* todo: Implement secondary CPU cold boot setup on CSS platforms */
cb_panic:
b cb_panic
endfunc plat_secondary_cold_boot_setup
/* -----------------------------------------------------
* void platform_get_entrypoint (unsigned int mpid);
*
......@@ -95,52 +78,45 @@ func platform_get_entrypoint
ret x9
endfunc platform_get_entrypoint
/*
* Override the default implementation to swap the cluster order.
* This is necessary in order to match the format of the boot
* information passed by the SCP and read in platform_is_primary_cpu
* below.
*/
func platform_get_core_pos
and x1, x0, #MPIDR_CPU_MASK
and x0, x0, #MPIDR_CLUSTER_MASK
eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order
add x0, x1, x0, LSR #6
ret
endfunc platform_get_core_pos
/* -----------------------------------------------------
* void platform_cold_boot_init (bl1_main function);
* void platform_mem_init(void);
*
* Routine called only by the primary cpu after a cold
* boot to perform early platform initialization
* We don't need to carry out any memory initialization
* on CSS platforms. The Secure RAM is accessible straight away.
* -----------------------------------------------------
*/
func platform_cold_boot_init
mov x20, x0
/* ---------------------------------------------
* Give ourselves a small coherent stack to
* ease the pain of initializing the MMU and
* CCI in assembler
* ---------------------------------------------
*/
mrs x0, mpidr_el1
bl platform_set_coherent_stack
func platform_mem_init
ret
endfunc platform_mem_init
/* ---------------------------------------------
* Architectural init. can be generic e.g.
* enabling stack alignment and platform spec-
* ific e.g. MMU & page table setup as per the
* platform memory map. Perform the latter here
* and the former in bl1_main.
* ---------------------------------------------
*/
bl bl1_early_platform_setup
bl bl1_plat_arch_setup
/* ---------------------------------------------
* Give ourselves a stack allocated in Normal
* -IS-WBWA memory
* ---------------------------------------------
*/
mrs x0, mpidr_el1
bl platform_set_stack
/* ---------------------------------------------
* Jump to the main function. Returning from it
* is a terminal error.
* ---------------------------------------------
/* -----------------------------------------------------
* unsigned int platform_is_primary_cpu (unsigned int mpid);
*
* Given the mpidr say whether this cpu is the primary
* cpu (applicable ony after a cold boot)
* -----------------------------------------------------
*/
blr x20
cb_init_panic:
b cb_init_panic
endfunc platform_cold_boot_init
func platform_is_primary_cpu
mov x9, x30
bl platform_get_core_pos
ldr x1, =SCP_BOOT_CFG_ADDR
ldr x1, [x1]
ubfx x1, x1, #PRIMARY_CPU_SHIFT, #PRIMARY_CPU_MASK
cmp x0, x1
cset x0, eq
ret x9
endfunc platform_is_primary_cpu
plat/arm/css/common/css_bl2_setup.c 0 → 100644
View file @ 4731e8f0
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <bl_common.h>
#include <debug.h>
#include "css_scp_bootloader.h"
/* Weak definition may be overridden in specific CSS based platform */
#pragma weak bl2_plat_handle_bl30
/*******************************************************************************
* Transfer BL3-0 from Trusted RAM using the SCP Download protocol.
* Return 0 on success, -1 otherwise.
******************************************************************************/
int bl2_plat_handle_bl30(image_info_t *bl30_image_info)
{
int ret;
ret = scp_bootloader_transfer((void *)bl30_image_info->image_base,
bl30_image_info->image_size);
if (ret == 0)
INFO("BL2: BL3-0 transferred to SCP\n\r");
else
ERROR("BL2: BL3-0 transfer failure\n\r");
return ret;
}
plat/arm/css/common/css_common.c 0 → 100644
View file @ 4731e8f0
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arm_gic.h>
#include <bl_common.h>
#include <platform_def.h>
#if IMAGE_BL31 || IMAGE_BL32
const unsigned int irq_sec_array[] = {
PLAT_CSS_IRQ_SEC_LIST,
ARM_IRQ_SEC_PHY_TIMER,
ARM_IRQ_SEC_SGI_0,
ARM_IRQ_SEC_SGI_1,
ARM_IRQ_SEC_SGI_2,
ARM_IRQ_SEC_SGI_3,
ARM_IRQ_SEC_SGI_4,
ARM_IRQ_SEC_SGI_5,
ARM_IRQ_SEC_SGI_6,
ARM_IRQ_SEC_SGI_7
};
/* Weak definitions may be overridden in specific CSS based platform */
#pragma weak plat_arm_gic_init
void plat_arm_gic_init(void)
{
arm_gic_init(PLAT_CSS_GICC_BASE,
PLAT_CSS_GICD_BASE,
PLAT_CSS_GICR_BASE,
irq_sec_array,
ARRAY_SIZE(irq_sec_array));
}
#endif /* IMAGE_BL31 || IMAGE_BL32 */
plat/arm/css/common/css_common.mk 0 → 100644
View file @ 4731e8f0
#
# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# Redistributions of source code must retain the above copyright notice, this
# list of conditions and the following disclaimer.
#
# Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# Neither the name of ARM nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific
# prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
PLAT_INCLUDES += -Iinclude/plat/arm/css/common \
-Iinclude/plat/arm/css/common/aarch64
PLAT_BL_COMMON_SOURCES += plat/arm/css/common/aarch64/css_helpers.S \
plat/arm/css/common/css_common.c
#BL1_SOURCES +=
BL2_SOURCES += plat/arm/css/common/css_bl2_setup.c \
plat/arm/css/common/css_mhu.c \
plat/arm/css/common/css_scp_bootloader.c \
plat/arm/css/common/css_scpi.c
BL31_SOURCES += plat/arm/css/common/css_mhu.c \
plat/arm/css/common/css_pm.c \
plat/arm/css/common/css_scpi.c
ifneq (${RESET_TO_BL31},0)
$(error "Using BL3-1 as the reset vector is not supported on CSS platforms. \
Please set RESET_TO_BL31 to 0.")
endif
NEED_BL30 := yes
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