Merge pull request #295 from danh-arm/dh/plat-port-reorg

ARM platform port reorganization

include/plat/arm/board/common/board_arm_def.h

+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __BOARD_ARM_DEF_H__
+#define __BOARD_ARM_DEF_H__
+
+#include <v2m_def.h>
+
+
+/*
+ * Required platform porting definitions common to all ARM
+ * development platforms
+ */
+
+/* Size of cacheable stacks */
+#if DEBUG_XLAT_TABLE
+# define PLATFORM_STACK_SIZE 0x800
+#elif IMAGE_BL1
+#if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE 0x1000
+#else
+# define PLATFORM_STACK_SIZE 0x440
+#endif
+#elif IMAGE_BL2
+# if TRUSTED_BOARD_BOOT
+#  define PLATFORM_STACK_SIZE 0x1000
+# else
+#  define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif IMAGE_BL31
+# define PLATFORM_STACK_SIZE 0x400
+#elif IMAGE_BL32
+# define PLATFORM_STACK_SIZE 0x440
+#endif
+
+/*
+ * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
+ * plat_arm_mmap array defined for each BL stage.
+ */
+#if IMAGE_BL1
+# define PLAT_ARM_MMAP_ENTRIES		6
+#endif
+#if IMAGE_BL2
+# define PLAT_ARM_MMAP_ENTRIES		8
+#endif
+#if IMAGE_BL31
+# define PLAT_ARM_MMAP_ENTRIES		5
+#endif
+#if IMAGE_BL32
+# define PLAT_ARM_MMAP_ENTRIES		4
+#endif
+
+/*
+ * Platform specific page table and MMU setup constants
+ */
+#if IMAGE_BL1
+# if PLAT_fvp || PLAT_juno
+#  define MAX_XLAT_TABLES		2
+# else
+#  define MAX_XLAT_TABLES		3
+# endif /* PLAT_ */
+#elif IMAGE_BL2
+# define MAX_XLAT_TABLES		3
+#elif IMAGE_BL31
+# define MAX_XLAT_TABLES		2
+#elif IMAGE_BL32
+# if ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
+#  define MAX_XLAT_TABLES		3
+# else
+#  define MAX_XLAT_TABLES		2
+# endif
+#endif
+
+
+#define MAX_IO_DEVICES			3
+#define MAX_IO_HANDLES			4
+
+#define PLAT_ARM_TRUSTED_SRAM_SIZE	0x00040000	/* 256 KB */
+
+#define PLAT_ARM_FIP_BASE		V2M_FLASH0_BASE
+#define PLAT_ARM_FIP_MAX_SIZE		V2M_FLASH0_SIZE
+
+
+#endif /* __BOARD_ARM_DEF_H__ */

plat/fvp/include/platform_oid.h → include/plat/arm/board/common/board_arm_oid.h

@@ -28,8 +28,8 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef PLATFORM_OID_H_
-#define PLATFORM_OID_H_
+#ifndef __BOARD_ARM_OID_H__
+#define __BOARD_ARM_OID_H__
 
 /*
  * This is the list of the different extensions containing relevant information
@@ -66,4 +66,5 @@
 #define BL33_CONTENT_CERT_PK_OID	"1.2.3.12"
 #define BL33_HASH_OID			"1.2.3.13"
 
-#endif /* PLATFORM_OID_H_ */
+
+#endif /* __BOARD_ARM_OID_H__ */

include/plat/arm/board/common/board_css_def.h

+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __BOARD_CSS_DEF_H__
+#define __BOARD_CSS_DEF_H__
+
+#include <common_def.h>
+#include <soc_css_def.h>
+#include <v2m_def.h>
+
+/*
+ * Definitions common to all ARM CSS-based development platforms
+ */
+
+/* Platform ID address */
+#define BOARD_CSS_PLAT_ID_REG_ADDR		0x7ffe00e0
+
+/* Platform ID related accessors */
+#define BOARD_CSS_PLAT_ID_REG_ID_MASK		0x0f
+#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT		0x0
+#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK	0xf00
+#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT	0x8
+#define BOARD_CSS_PLAT_TYPE_RTL			0x00
+#define BOARD_CSS_PLAT_TYPE_FPGA		0x01
+#define BOARD_CSS_PLAT_TYPE_EMULATOR		0x02
+#define BOARD_CSS_PLAT_TYPE_FVP			0x03
+
+#ifndef __ASSEMBLY__
+
+#include <mmio.h>
+
+#define BOARD_CSS_GET_PLAT_TYPE(addr)					\
+	((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK)		\
+	>> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
+
+#endif /* __ASSEMBLY__ */
+
+
+/*
+ * Required platform porting definitions common to all ARM CSS-based
+ * development platforms
+ */
+
+#define PLAT_ARM_DRAM2_SIZE			MAKE_ULL(0x180000000)
+
+/* UART related constants */
+#define PLAT_ARM_BOOT_UART_BASE			SOC_CSS_UART0_BASE
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ		SOC_CSS_UART0_CLK_IN_HZ
+
+#define PLAT_ARM_CRASH_UART_BASE		SOC_CSS_UART1_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ		SOC_CSS_UART1_CLK_IN_HZ
+
+#define PLAT_ARM_TSP_UART_BASE			V2M_IOFPGA_UART0_BASE
+#define PLAT_ARM_TSP_UART_CLK_IN_HZ		V2M_IOFPGA_UART0_CLK_IN_HZ
+
+
+#endif /* __BOARD_CSS_DEF_H__ */
+

include/plat/arm/board/common/v2m_def.h

+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __V2M_DEF_H__
+#define __V2M_DEF_H__
+
+#include <xlat_tables.h>
+
+
+/* V2M motherboard system registers & offsets */
+#define V2M_SYSREGS_BASE		0x1c010000
+#define V2M_SYS_ID			0x0
+#define V2M_SYS_SWITCH			0x4
+#define V2M_SYS_LED			0x8
+#define V2M_SYS_CFGDATA			0xa0
+#define V2M_SYS_CFGCTRL			0xa4
+#define V2M_SYS_CFGSTATUS		0xa8
+
+#define V2M_CFGCTRL_START		(1 << 31)
+#define V2M_CFGCTRL_RW			(1 << 30)
+#define V2M_CFGCTRL_FUNC_SHIFT		20
+#define V2M_CFGCTRL_FUNC(fn)		(fn << V2M_CFGCTRL_FUNC_SHIFT)
+#define V2M_FUNC_CLK_GEN		0x01
+#define V2M_FUNC_TEMP			0x04
+#define V2M_FUNC_DB_RESET		0x05
+#define V2M_FUNC_SCC_CFG		0x06
+#define V2M_FUNC_SHUTDOWN		0x08
+#define V2M_FUNC_REBOOT			0x09
+
+/*
+ * V2M sysled bit definitions. The values written to this
+ * register are defined in arch.h & runtime_svc.h. Only
+ * used by the primary cpu to diagnose any cold boot issues.
+ *
+ * SYS_LED[0]   - Security state (S=0/NS=1)
+ * SYS_LED[2:1] - Exception Level (EL3-EL0)
+ * SYS_LED[7:3] - Exception Class (Sync/Async & origin)
+ *
+ */
+#define V2M_SYS_LED_SS_SHIFT		0x0
+#define V2M_SYS_LED_EL_SHIFT		0x1
+#define V2M_SYS_LED_EC_SHIFT		0x3
+
+#define V2M_SYS_LED_SS_MASK		0x1
+#define V2M_SYS_LED_EL_MASK		0x3
+#define V2M_SYS_LED_EC_MASK		0x1f
+
+/* V2M sysid register bits */
+#define V2M_SYS_ID_REV_SHIFT		28
+#define V2M_SYS_ID_HBI_SHIFT		16
+#define V2M_SYS_ID_BLD_SHIFT		12
+#define V2M_SYS_ID_ARCH_SHIFT		8
+#define V2M_SYS_ID_FPGA_SHIFT		0
+
+#define V2M_SYS_ID_REV_MASK		0xf
+#define V2M_SYS_ID_HBI_MASK		0xfff
+#define V2M_SYS_ID_BLD_MASK		0xf
+#define V2M_SYS_ID_ARCH_MASK		0xf
+#define V2M_SYS_ID_FPGA_MASK		0xff
+
+#define V2M_SYS_ID_BLD_LENGTH		4
+
+
+/* NOR Flash */
+#define V2M_FLASH0_BASE			0x08000000
+#define V2M_FLASH0_SIZE			0x04000000
+
+#define V2M_IOFPGA_BASE			0x1c000000
+#define V2M_IOFPGA_SIZE			0x03000000
+
+/* PL011 UART related constants */
+#define V2M_IOFPGA_UART0_BASE		0x1c090000
+#define V2M_IOFPGA_UART1_BASE		0x1c0a0000
+#define V2M_IOFPGA_UART2_BASE		0x1c0b0000
+#define V2M_IOFPGA_UART3_BASE		0x1c0c0000
+
+#define V2M_IOFPGA_UART0_CLK_IN_HZ	24000000
+#define V2M_IOFPGA_UART1_CLK_IN_HZ	24000000
+#define V2M_IOFPGA_UART2_CLK_IN_HZ	24000000
+#define V2M_IOFPGA_UART3_CLK_IN_HZ	24000000
+
+
+#define V2M_MAP_FLASH0			MAP_REGION_FLAT(V2M_FLASH0_BASE,\
+						V2M_FLASH0_SIZE,	\
+						MT_MEMORY | MT_RO | MT_SECURE)
+
+#define V2M_MAP_IOFPGA			MAP_REGION_FLAT(V2M_IOFPGA_BASE,\
+						V2M_IOFPGA_SIZE,		\
+						MT_DEVICE | MT_RW | MT_SECURE)
+
+
+
+#endif /* __V2M_DEF_H__ */

plat/juno/include/plat_macros.S → include/plat/arm/common/aarch64/arm_macros.S

 /*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -27,33 +27,33 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
+#ifndef __ARM_MACROS_S__
+#define __ARM_MACROS_S__
 
 #include <cci.h>
 #include <gic_v2.h>
-#include "platform_def.h"
-#include "../juno_def.h"
+#include <platform_def.h>
 
 .section .rodata.gic_reg_name, "aS"
 gicc_regs:
 	.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
 gicd_pend_reg:
-	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
+	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n"	\
+		" Offset:\t\t\tvalue\n"
 newline:
 	.asciz "\n"
 spacer:
 	.asciz ":\t\t0x"
 
-
 	/* ---------------------------------------------
-	 * The below macro prints out relevant GIC
+	 * The below utility macro prints out relevant GIC
 	 * registers whenever an unhandled exception is
-	 * taken in BL3-1.
-	 * Clobbers: x0 - x10, x16, sp
+	 * taken in BL3-1 on ARM standard platforms.
+	 * Expects: GICD base in x16, GICC base in x17
+	 * Clobbers: x0 - x10, sp
 	 * ---------------------------------------------
 	 */
-	.macro plat_print_gic_regs
-	mov_imm	x16, GICD_BASE
-	mov_imm	x17, GICC_BASE
+	.macro arm_print_gic_regs
 	/* Load the gicc reg list to x6 */
 	adr	x6, gicc_regs
 	/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
@@ -85,25 +85,31 @@ gicd_ispendr_loop:
 exit_print_gic_regs:
 	.endm
 
+
 .section .rodata.cci_reg_name, "aS"
 cci_iface_regs:
 	.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
 
 	/* ------------------------------------------------
-	 * The below macro prints out relevant interconnect
-	 * registers whenever an unhandled exception is
-	 * taken in BL3-1.
+	 * The below required platform porting macro prints
+	 * out relevant interconnect registers whenever an
+	 * unhandled exception is taken in BL3-1.
 	 * Clobbers: x0 - x9, sp
 	 * ------------------------------------------------
 	 */
 	.macro plat_print_interconnect_regs
 	adr	x6, cci_iface_regs
 	/* Store in x7 the base address of the first interface */
-	mov_imm	x7, (CCI400_BASE + SLAVE_IFACE3_OFFSET)
+	mov_imm	x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET(	\
+			PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX))
 	ldr	w8, [x7, #SNOOP_CTRL_REG]
 	/* Store in x7 the base address of the second interface */
-	mov_imm	x7, (CCI400_BASE + SLAVE_IFACE4_OFFSET)
+	mov_imm	x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET(	\
+			PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX))
 	ldr	w9, [x7, #SNOOP_CTRL_REG]
 	/* Store to the crash buf and print to console */
 	bl	str_in_crash_buf_print
 	.endm
+
+
+#endif /* __ARM_MACROS_S__ */

include/plat/common/plat_config.h → include/plat/arm/common/arm_config.h

 /*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -27,27 +27,20 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
-#ifndef __PLAT_CONFIG_H__
-#define __PLAT_CONFIG_H__
+#ifndef __ARM_CONFIG_H__
+#define __ARM_CONFIG_H__
 
-#define CONFIG_GICC_BASE_OFFSET		0x4
 
-
-#ifndef __ASSEMBLY__
-
-#include <cassert.h>
-
-
-enum plat_config_flags {
-	/* Whether Base FVP memory map is in use */
-	CONFIG_BASE_MMAP		= 0x1,
+enum arm_config_flags {
+	/* Whether Base memory map is in use */
+	ARM_CONFIG_BASE_MMAP		= 0x1,
 	/* Whether CCI should be enabled */
-	CONFIG_HAS_CCI			= 0x2,
+	ARM_CONFIG_HAS_CCI		= 0x2,
 	/* Whether TZC should be configured */
-	CONFIG_HAS_TZC			= 0x4
+	ARM_CONFIG_HAS_TZC		= 0x4
 };
 
-typedef struct plat_config {
+typedef struct arm_config {
 	unsigned int gicd_base;
 	unsigned int gicc_base;
 	unsigned int gich_base;
@@ -55,24 +48,16 @@ typedef struct plat_config {
 	unsigned int max_aff0;
 	unsigned int max_aff1;
 	unsigned long flags;
-} plat_config_t;
+} arm_config_t;
 
-inline const plat_config_t *get_plat_config();
 
+/* If used, arm_config must be defined and populated in the platform port */
+extern arm_config_t arm_config;
 
-CASSERT(CONFIG_GICC_BASE_OFFSET == __builtin_offsetof(
-	plat_config_t, gicc_base),
-	assert_gicc_base_offset_mismatch);
-
-/* If used, plat_config must be defined and populated in the platform port*/
-extern plat_config_t plat_config;
-
-inline const plat_config_t *get_plat_config()
+inline const arm_config_t *get_arm_config(void)
 {
-	return &plat_config;
+	return &arm_config;
 }
 
 
-#endif /* __ASSEMBLY__ */
-
-#endif /* __PLAT_CONFIG_H__ */
+#endif /* __ARM_CONFIG_H__ */

plat/fvp/include/platform_def.h → include/plat/arm/common/arm_def.h

 /*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -27,109 +27,186 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
+#ifndef __ARM_DEF_H__
+#define __ARM_DEF_H__
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#include <common_def.h>
+#include <platform_def.h>
+#include <xlat_tables.h>
 
-#include <arch.h>
-#include "../fvp_def.h"
 
+/******************************************************************************
+ * Definitions common to all ARM standard platforms
+ *****************************************************************************/
 
-/*******************************************************************************
- * Platform binary types for linking
- ******************************************************************************/
-#define PLATFORM_LINKER_FORMAT          "elf64-littleaarch64"
-#define PLATFORM_LINKER_ARCH            aarch64
+/* Special value used to verify platform parameters from BL2 to BL3-1 */
+#define ARM_BL31_PLAT_PARAM_VAL		0x0f1e2d3c4b5a6978ULL
 
-/*******************************************************************************
- * Generic platform constants
- ******************************************************************************/
+#define ARM_CLUSTER_COUNT		2ull
 
-/* Size of cacheable stacks */
-#if DEBUG_XLAT_TABLE
-#define PLATFORM_STACK_SIZE 0x800
-#elif IMAGE_BL1
-#if TRUSTED_BOARD_BOOT
-#define PLATFORM_STACK_SIZE 0x1000
-#else
-#define PLATFORM_STACK_SIZE 0x440
-#endif
-#elif IMAGE_BL2
-#if TRUSTED_BOARD_BOOT
-#define PLATFORM_STACK_SIZE 0x1000
+#define ARM_CACHE_WRITEBACK_SHIFT	6
+
+/* Memory location options for TSP */
+#define ARM_TRUSTED_SRAM_ID		0
+#define ARM_TRUSTED_DRAM_ID		1
+#define ARM_DRAM_ID			2
+
+/* The first 4KB of Trusted SRAM are used as shared memory */
+#define ARM_TRUSTED_SRAM_BASE		0x04000000
+#define ARM_SHARED_RAM_BASE		ARM_TRUSTED_SRAM_BASE
+#define ARM_SHARED_RAM_SIZE		0x00001000	/* 4 KB */
+
+/* The remaining Trusted SRAM is used to load the BL images */
+#define ARM_BL_RAM_BASE			(ARM_SHARED_RAM_BASE +	\
+					 ARM_SHARED_RAM_SIZE)
+#define ARM_BL_RAM_SIZE			(PLAT_ARM_TRUSTED_SRAM_SIZE -	\
+					 ARM_SHARED_RAM_SIZE)
+
+/*
+ * The top 16MB of DRAM1 is configured as secure access only using the TZC
+ *   - SCP TZC DRAM: If present, DRAM reserved for SCP use
+ *   - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
+ */
+#define ARM_TZC_DRAM1_SIZE		MAKE_ULL(0x01000000)
+
+#define ARM_SCP_TZC_DRAM1_BASE		(ARM_DRAM1_BASE +		\
+					 ARM_DRAM1_SIZE -		\
+					 ARM_SCP_TZC_DRAM1_SIZE)
+#define ARM_SCP_TZC_DRAM1_SIZE		PLAT_ARM_SCP_TZC_DRAM1_SIZE
+#define ARM_SCP_TZC_DRAM1_END		(ARM_SCP_TZC_DRAM1_BASE +	\
+					 ARM_SCP_TZC_DRAM1_SIZE - 1)
+
+#define ARM_AP_TZC_DRAM1_BASE		(ARM_DRAM1_BASE +		\
+					 ARM_DRAM1_SIZE -		\
+					 ARM_TZC_DRAM1_SIZE)
+#define ARM_AP_TZC_DRAM1_SIZE		(ARM_TZC_DRAM1_SIZE -		\
+					 ARM_SCP_TZC_DRAM1_SIZE)
+#define ARM_AP_TZC_DRAM1_END		(ARM_AP_TZC_DRAM1_BASE +	\
+					 ARM_AP_TZC_DRAM1_SIZE - 1)
+
+
+#define ARM_NS_DRAM1_BASE		ARM_DRAM1_BASE
+#define ARM_NS_DRAM1_SIZE		(ARM_DRAM1_SIZE -		\
+					 ARM_TZC_DRAM1_SIZE)
+#define ARM_NS_DRAM1_END		(ARM_NS_DRAM1_BASE +		\
+					 ARM_NS_DRAM1_SIZE - 1)
+
+#define ARM_DRAM1_BASE			MAKE_ULL(0x80000000)
+#define ARM_DRAM1_SIZE			MAKE_ULL(0x80000000)
+#define ARM_DRAM1_END			(ARM_DRAM1_BASE +		\
+					 ARM_DRAM1_SIZE - 1)
+
+#define ARM_DRAM2_BASE			MAKE_ULL(0x880000000)
+#define ARM_DRAM2_SIZE			PLAT_ARM_DRAM2_SIZE
+#define ARM_DRAM2_END			(ARM_DRAM2_BASE +		\
+					 ARM_DRAM2_SIZE - 1)
+
+#define ARM_IRQ_SEC_PHY_TIMER		29
+
+#define ARM_IRQ_SEC_SGI_0		8
+#define ARM_IRQ_SEC_SGI_1		9
+#define ARM_IRQ_SEC_SGI_2		10
+#define ARM_IRQ_SEC_SGI_3		11
+#define ARM_IRQ_SEC_SGI_4		12
+#define ARM_IRQ_SEC_SGI_5		13
+#define ARM_IRQ_SEC_SGI_6		14
+#define ARM_IRQ_SEC_SGI_7		15
+
+#define ARM_SHARED_RAM_ATTR		((PLAT_ARM_SHARED_RAM_CACHED ?	\
+						MT_MEMORY : MT_DEVICE)	\
+						| MT_RW | MT_SECURE)
+
+#define ARM_MAP_SHARED_RAM		MAP_REGION_FLAT(		\
+						ARM_SHARED_RAM_BASE,	\
+						ARM_SHARED_RAM_SIZE,	\
+						ARM_SHARED_RAM_ATTR)
+
+#define ARM_MAP_NS_DRAM1		MAP_REGION_FLAT(		\
+						ARM_NS_DRAM1_BASE,	\
+						ARM_NS_DRAM1_SIZE,	\
+						MT_MEMORY | MT_RW | MT_NS)
+
+#define ARM_MAP_TSP_SEC_MEM		MAP_REGION_FLAT(		\
+						TSP_SEC_MEM_BASE,	\
+						TSP_SEC_MEM_SIZE,	\
+						MT_MEMORY | MT_RW | MT_SECURE)
+
+
+/*
+ * The number of regions like RO(code), coherent and data required by
+ * different BL stages which need to be mapped in the MMU.
+ */
+#if USE_COHERENT_MEM
+#define ARM_BL_REGIONS			3
 #else
-#define PLATFORM_STACK_SIZE 0x400
-#endif
-#elif IMAGE_BL31
-#define PLATFORM_STACK_SIZE 0x400
-#elif IMAGE_BL32
-#define PLATFORM_STACK_SIZE 0x440
+#define ARM_BL_REGIONS			2
 #endif
 
-#define FIRMWARE_WELCOME_STR		"Booting Trusted Firmware\n"
+#define MAX_MMAP_REGIONS		(PLAT_ARM_MMAP_ENTRIES +	\
+					 ARM_BL_REGIONS)
 
-/* Trusted Boot Firmware BL2 */
-#define BL2_IMAGE_NAME			"bl2.bin"
+/* Memory mapped Generic timer interfaces  */
+#define ARM_SYS_CNTCTL_BASE		0x2a430000
+#define ARM_SYS_CNTREAD_BASE		0x2a800000
+#define ARM_SYS_TIMCTL_BASE		0x2a810000
 
-/* EL3 Runtime Firmware BL31 */
-#define BL31_IMAGE_NAME			"bl31.bin"
+#define ARM_CONSOLE_BAUDRATE		115200
 
-/* Secure Payload BL32 (Trusted OS) */
-#define BL32_IMAGE_NAME			"bl32.bin"
+/* TZC related constants */
+#define ARM_TZC_BASE			0x2a4a0000
 
-/* Non-Trusted Firmware BL33 */
-#define BL33_IMAGE_NAME			"bl33.bin" /* e.g. UEFI */
 
-#if TRUSTED_BOARD_BOOT
-/* Certificates */
-# define BL2_CERT_NAME			"bl2.crt"
-# define TRUSTED_KEY_CERT_NAME		"trusted_key.crt"
-
-# define BL30_KEY_CERT_NAME		"bl30_key.crt"
-# define BL31_KEY_CERT_NAME		"bl31_key.crt"
-# define BL32_KEY_CERT_NAME		"bl32_key.crt"
-# define BL33_KEY_CERT_NAME		"bl33_key.crt"
-
-# define BL30_CERT_NAME			"bl30.crt"
-# define BL31_CERT_NAME			"bl31.crt"
-# define BL32_CERT_NAME			"bl32.crt"
-# define BL33_CERT_NAME			"bl33.crt"
-#endif /* TRUSTED_BOARD_BOOT */
-
-#define PLATFORM_CACHE_LINE_SIZE	64
-#define PLATFORM_CLUSTER_COUNT		2ull
-#define PLATFORM_CLUSTER0_CORE_COUNT	4
-#define PLATFORM_CLUSTER1_CORE_COUNT	4
-#define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER1_CORE_COUNT + \
-						PLATFORM_CLUSTER0_CORE_COUNT)
-#define PLATFORM_MAX_CPUS_PER_CLUSTER	4
-#define PLATFORM_NUM_AFFS		(PLATFORM_CLUSTER_COUNT + \
+/******************************************************************************
+ * Required platform porting definitions common to all ARM standard platforms
+ *****************************************************************************/
+
+#define ADDR_SPACE_SIZE			(1ull << 32)
+
+#define PLATFORM_NUM_AFFS		(ARM_CLUSTER_COUNT + \
 					 PLATFORM_CORE_COUNT)
 #define PLATFORM_MAX_AFFLVL		MPIDR_AFFLVL1
-#define MAX_IO_DEVICES			3
-#define MAX_IO_HANDLES			4
+
+#define PLATFORM_CORE_COUNT		(PLAT_ARM_CLUSTER0_CORE_COUNT + \
+					 PLAT_ARM_CLUSTER1_CORE_COUNT)
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ */
+#define CACHE_WRITEBACK_GRANULE		(1 << ARM_CACHE_WRITEBACK_SHIFT)
+
+#if !USE_COHERENT_MEM
+/*
+ * Size of the per-cpu data in bytes that should be reserved in the generic
+ * per-cpu data structure for the ARM platform port.
+ */
+#define PLAT_PCPU_DATA_SIZE		2
+#endif
+
 
 /*******************************************************************************
  * BL1 specific defines.
  * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
  * addresses.
  ******************************************************************************/
-#define BL1_RO_BASE			FVP_TRUSTED_ROM_BASE
-#define BL1_RO_LIMIT			(FVP_TRUSTED_ROM_BASE \
-					+ FVP_TRUSTED_ROM_SIZE)
+#define BL1_RO_BASE			PLAT_ARM_TRUSTED_ROM_BASE
+#define BL1_RO_LIMIT			(PLAT_ARM_TRUSTED_ROM_BASE	\
+					 + PLAT_ARM_TRUSTED_ROM_SIZE)
 /*
  * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using
  * the current BL1 RW debug size plus a little space for growth.
  */
 #if TRUSTED_BOARD_BOOT
-#define BL1_RW_BASE			(FVP_TRUSTED_SRAM_BASE \
-					+ FVP_TRUSTED_SRAM_SIZE - 0x8000)
+#define BL1_RW_BASE			(ARM_BL_RAM_BASE +		\
+						ARM_BL_RAM_SIZE -	\
+						0x8000)
 #else
-#define BL1_RW_BASE			(FVP_TRUSTED_SRAM_BASE \
-					+ FVP_TRUSTED_SRAM_SIZE - 0x6000)
+#define BL1_RW_BASE			(ARM_BL_RAM_BASE +		\
+						ARM_BL_RAM_SIZE -	\
+						0x6000)
 #endif
-#define BL1_RW_LIMIT			(FVP_TRUSTED_SRAM_BASE \
-					+ FVP_TRUSTED_SRAM_SIZE)
+#define BL1_RW_LIMIT			(ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
 
 /*******************************************************************************
  * BL2 specific defines.
@@ -146,89 +223,52 @@
 #define BL2_LIMIT			BL31_BASE
 
 /*******************************************************************************
- * BL31 specific defines.
+ * BL3-1 specific defines.
  ******************************************************************************/
 /*
  * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
  * current BL3-1 debug size plus a little space for growth.
  */
-#define BL31_BASE			(FVP_TRUSTED_SRAM_BASE \
-					+ FVP_TRUSTED_SRAM_SIZE - 0x1D000)
+#define BL31_BASE			(ARM_BL_RAM_BASE +		\
+						ARM_BL_RAM_SIZE -	\
+						0x1D000)
 #define BL31_PROGBITS_LIMIT		BL1_RW_BASE
-#define BL31_LIMIT			(FVP_TRUSTED_SRAM_BASE \
-					+ FVP_TRUSTED_SRAM_SIZE)
+#define BL31_LIMIT			(ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
 
 /*******************************************************************************
- * BL32 specific defines.
+ * BL3-2 specific defines.
  ******************************************************************************/
 /*
- * On FVP, the TSP can execute from Trusted SRAM, Trusted DRAM or the DRAM
- * region secured by the TrustZone controller.
+ * On ARM standard platforms, the TSP can execute from Trusted SRAM,
+ * Trusted DRAM (if available) or the DRAM region secured by the TrustZone
+ * controller.
  */
-#if FVP_TSP_RAM_LOCATION_ID == FVP_TRUSTED_SRAM_ID
-# define TSP_SEC_MEM_BASE		FVP_TRUSTED_SRAM_BASE
-# define TSP_SEC_MEM_SIZE		FVP_TRUSTED_SRAM_SIZE
+#if ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
+# define TSP_SEC_MEM_BASE		ARM_BL_RAM_BASE
+# define TSP_SEC_MEM_SIZE		ARM_BL_RAM_SIZE
 # define TSP_PROGBITS_LIMIT		BL2_BASE
-# define BL32_BASE			FVP_TRUSTED_SRAM_BASE
+# define BL32_BASE			ARM_BL_RAM_BASE
 # define BL32_LIMIT			BL31_BASE
-#elif FVP_TSP_RAM_LOCATION_ID == FVP_TRUSTED_DRAM_ID
-# define TSP_SEC_MEM_BASE		FVP_TRUSTED_DRAM_BASE
-# define TSP_SEC_MEM_SIZE		FVP_TRUSTED_DRAM_SIZE
-# define BL32_BASE			FVP_TRUSTED_DRAM_BASE
-# define BL32_LIMIT			(FVP_TRUSTED_DRAM_BASE + (1 << 21))
-#elif FVP_TSP_RAM_LOCATION_ID == FVP_DRAM_ID
-# define TSP_SEC_MEM_BASE		DRAM1_SEC_BASE
-# define TSP_SEC_MEM_SIZE		DRAM1_SEC_SIZE
-# define BL32_BASE			DRAM1_SEC_BASE
-# define BL32_LIMIT			(DRAM1_SEC_BASE + DRAM1_SEC_SIZE)
+#elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
+# define TSP_SEC_MEM_BASE		PLAT_ARM_TRUSTED_DRAM_BASE
+# define TSP_SEC_MEM_SIZE		PLAT_ARM_TRUSTED_DRAM_SIZE
+# define BL32_BASE			PLAT_ARM_TRUSTED_DRAM_BASE
+# define BL32_LIMIT			(PLAT_ARM_TRUSTED_DRAM_BASE	\
+						+ (1 << 21))
+#elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
+# define TSP_SEC_MEM_BASE		ARM_AP_TZC_DRAM1_BASE
+# define TSP_SEC_MEM_SIZE		ARM_AP_TZC_DRAM1_SIZE
+# define BL32_BASE			ARM_AP_TZC_DRAM1_BASE
+# define BL32_LIMIT			(ARM_AP_TZC_DRAM1_BASE +	\
+						ARM_AP_TZC_DRAM1_SIZE)
 #else
-# error "Unsupported FVP_TSP_RAM_LOCATION_ID value"
+# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
 #endif
 
 /*
  * ID of the secure physical generic timer interrupt used by the TSP.
  */
-#define TSP_IRQ_SEC_PHY_TIMER		IRQ_SEC_PHY_TIMER
+#define TSP_IRQ_SEC_PHY_TIMER		ARM_IRQ_SEC_PHY_TIMER
 
-/*******************************************************************************
- * Platform specific page table and MMU setup constants
- ******************************************************************************/
-#define ADDR_SPACE_SIZE			(1ull << 32)
-
-#if IMAGE_BL1
-# define MAX_XLAT_TABLES		2
-#elif IMAGE_BL2
-# define MAX_XLAT_TABLES		3
-#elif IMAGE_BL31
-# define MAX_XLAT_TABLES		2
-#elif IMAGE_BL32
-# if FVP_TSP_RAM_LOCATION_ID == FVP_DRAM_ID
-#  define MAX_XLAT_TABLES		3
-# else
-#  define MAX_XLAT_TABLES		2
-# endif
-#endif
-
-#define MAX_MMAP_REGIONS		(FVP_MMAP_ENTRIES + FVP_BL_REGIONS)
-
-/*******************************************************************************
- * Declarations and constants to access the mailboxes safely. Each mailbox is
- * aligned on the biggest cache line size in the platform. This is known only
- * to the platform as it might have a combination of integrated and external
- * caches. Such alignment ensures that two maiboxes do not sit on the same cache
- * line at any cache level. They could belong to different cpus/clusters &
- * get written while being protected by different locks causing corruption of
- * a valid mailbox address.
- ******************************************************************************/
-#define CACHE_WRITEBACK_SHIFT   6
-#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
-
-#if !USE_COHERENT_MEM
-/*******************************************************************************
- * Size of the per-cpu data in bytes that should be reserved in the generic
- * per-cpu data structure for the FVP port.
- ******************************************************************************/
-#define PLAT_PCPU_DATA_SIZE	2
-#endif
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* __ARM_DEF_H__ */

plat/fvp/fvp_private.h → include/plat/arm/common/plat_arm.h

 /*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -27,43 +27,65 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
-
-#ifndef __FVP_PRIVATE_H__
-#define __FVP_PRIVATE_H__
+#ifndef __PLAT_ARM_H__
+#define __PLAT_ARM_H__
 
 #include <bakery_lock.h>
 #include <bl_common.h>
+#include <cassert.h>
 #include <cpu_data.h>
-#include <platform_def.h>
+#include <stdint.h>
 
 
-typedef volatile struct mailbox {
-	unsigned long value
-	__attribute__((__aligned__(CACHE_WRITEBACK_GRANULE)));
-} mailbox_t;
+/*
+ * Extern declarations common to ARM standard platforms
+ */
+extern const mmap_region_t plat_arm_mmap[];
 
-/*******************************************************************************
- * This structure represents the superset of information that is passed to
- * BL31 e.g. while passing control to it from BL2 which is bl31_params
- * and bl31_plat_params and its elements
- ******************************************************************************/
-typedef struct bl2_to_bl31_params_mem {
-	bl31_params_t bl31_params;
-	image_info_t bl31_image_info;
-	image_info_t bl32_image_info;
-	image_info_t bl33_image_info;
-	entry_point_info_t bl33_ep_info;
-	entry_point_info_t bl32_ep_info;
-	entry_point_info_t bl31_ep_info;
-} bl2_to_bl31_params_mem_t;
+#define ARM_CASSERT_MMAP						\
+	CASSERT((ARRAY_SIZE(plat_arm_mmap) + ARM_BL_REGIONS)		\
+		<= MAX_MMAP_REGIONS,					\
+		assert_max_mmap_regions);
+
+/*
+ * Utility functions common to ARM standard platforms
+ */
+
+void arm_configure_mmu_el1(unsigned long total_base,
+			unsigned long total_size,
+			unsigned long ro_start,
+			unsigned long ro_limit
+#if USE_COHERENT_MEM
+			, unsigned long coh_start,
+			unsigned long coh_limit
+#endif
+);
+void arm_configure_mmu_el3(unsigned long total_base,
+			unsigned long total_size,
+			unsigned long ro_start,
+			unsigned long ro_limit
+#if USE_COHERENT_MEM
+			, unsigned long coh_start,
+			unsigned long coh_limit
+#endif
+);
 
+#if IMAGE_BL31
 #if USE_COHERENT_MEM
+
+/*
+ * Use this macro to instantiate lock before it is used in below
+ * arm_lock_xxx() macros
+ */
+#define ARM_INSTANTIATE_LOCK	bakery_lock_t arm_lock	\
+	__attribute__ ((section("tzfw_coherent_mem")));
+
 /*
  * These are wrapper macros to the Coherent Memory Bakery Lock API.
  */
-#define fvp_lock_init(_lock_arg)	bakery_lock_init(_lock_arg)
-#define fvp_lock_get(_lock_arg)		bakery_lock_get(_lock_arg)
-#define fvp_lock_release(_lock_arg)	bakery_lock_release(_lock_arg)
+#define arm_lock_init()		bakery_lock_init(&arm_lock)
+#define arm_lock_get()		bakery_lock_get(&arm_lock)
+#define arm_lock_release()	bakery_lock_release(&arm_lock)
 
 #else
 
@@ -72,90 +94,111 @@ typedef struct bl2_to_bl31_params_mem {
  * are used if the platform chooses not to use coherent memory for bakery lock
  * data structures.
  ******************************************************************************/
-#define FVP_MAX_BAKERIES	1
-#define FVP_PWRC_BAKERY_ID	0
+#define ARM_MAX_BAKERIES	1
+#define ARM_PWRC_BAKERY_ID	0
+
+/* Empty definition */
+#define ARM_INSTANTIATE_LOCK
 
 /*******************************************************************************
  * Definition of structure which holds platform specific per-cpu data. Currently
- * it holds only the bakery lock information for each cpu. Constants to
- * specify how many bakeries this platform implements and bakery ids are
- * specified in fvp_def.h
+ * it holds only the bakery lock information for each cpu.
  ******************************************************************************/
-typedef struct fvp_cpu_data {
-	bakery_info_t pcpu_bakery_info[FVP_MAX_BAKERIES];
-} fvp_cpu_data_t;
+typedef struct arm_cpu_data {
+	bakery_info_t pcpu_bakery_info[ARM_MAX_BAKERIES];
+} arm_cpu_data_t;
 
-/* Macro to define the offset of bakery_info_t in fvp_cpu_data_t */
-#define FVP_CPU_DATA_LOCK_OFFSET	__builtin_offsetof\
-					    (fvp_cpu_data_t, pcpu_bakery_info)
+/* Macro to define the offset of bakery_info_t in arm_cpu_data_t */
+#define ARM_CPU_DATA_LOCK_OFFSET	__builtin_offsetof\
+					    (arm_cpu_data_t, pcpu_bakery_info)
 
 
 /*******************************************************************************
- * Helper macros for bakery lock api when using the above fvp_cpu_data_t for
+ * Helper macros for bakery lock api when using the above arm_cpu_data_t for
  * bakery lock data structures. It assumes that the bakery_info is at the
  * beginning of the platform specific per-cpu data.
  ******************************************************************************/
-#define fvp_lock_init(_lock_arg)	/* No init required */
-#define fvp_lock_get(_lock_arg)		bakery_lock_get(_lock_arg,  	    \
-						CPU_DATA_PLAT_PCPU_OFFSET + \
-						FVP_CPU_DATA_LOCK_OFFSET)
-#define fvp_lock_release(_lock_arg)	bakery_lock_release(_lock_arg,	    \
-						CPU_DATA_PLAT_PCPU_OFFSET + \
-						FVP_CPU_DATA_LOCK_OFFSET)
+#define arm_lock_init()		/* No init required */
+#define arm_lock_get()		bakery_lock_get(ARM_PWRC_BAKERY_ID,	\
+					CPU_DATA_PLAT_PCPU_OFFSET +	\
+					ARM_CPU_DATA_LOCK_OFFSET)
+#define arm_lock_release()	bakery_lock_release(ARM_PWRC_BAKERY_ID,	\
+					CPU_DATA_PLAT_PCPU_OFFSET +	\
+					ARM_CPU_DATA_LOCK_OFFSET)
 
 /*
- * Ensure that the size of the FVP specific per-cpu data structure and the size
- * of the memory allocated in generic per-cpu data for the platform are the same.
+ * Ensure that the size of the platform specific per-cpu data structure and
+ * the size of the memory allocated in generic per-cpu data for the platform
+ * are the same.
  */
-CASSERT(PLAT_PCPU_DATA_SIZE == sizeof(fvp_cpu_data_t),	\
-	fvp_pcpu_data_size_mismatch);
+CASSERT(PLAT_PCPU_DATA_SIZE == sizeof(arm_cpu_data_t),
+	arm_pcpu_data_size_mismatch);
 
-#endif /* __USE_COHERENT_MEM__ */
+#endif /* USE_COHERENT_MEM */
 
-/*******************************************************************************
- * Function and variable prototypes
- ******************************************************************************/
-void fvp_configure_mmu_el1(unsigned long total_base,
-			   unsigned long total_size,
-			   unsigned long,
-			   unsigned long
-#if USE_COHERENT_MEM
-			   , unsigned long,
-			   unsigned long
-#endif
-			   );
-void fvp_configure_mmu_el3(unsigned long total_base,
-			   unsigned long total_size,
-			   unsigned long,
-			   unsigned long
-#if USE_COHERENT_MEM
-			   , unsigned long,
-			   unsigned long
-#endif
-			   );
+#else
+
+/*
+* Dummy macros for all other BL stages other than BL3-1
+*/
+#define ARM_INSTANTIATE_LOCK
+#define arm_lock_init()
+#define arm_lock_get()
+#define arm_lock_release()
 
-int fvp_config_setup(void);
+#endif /* IMAGE_BL31 */
 
-void fvp_cci_init(void);
-void fvp_cci_enable(void);
-void fvp_cci_disable(void);
 
-void fvp_gic_init(void);
+/* CCI utility functions */
+void arm_cci_init(void);
 
-/* Declarations for fvp_topology.c */
-int fvp_setup_topology(void);
+/* IO storage utility functions */
+void arm_io_setup(void);
 
-/* Declarations for fvp_io_storage.c */
-void fvp_io_setup(void);
+/* Security utility functions */
+void arm_tzc_setup(void);
 
-/* Declarations for fvp_security.c */
-void fvp_security_setup(void);
+/* PM utility functions */
+int32_t arm_do_affinst_actions(unsigned int afflvl, unsigned int state);
+int arm_validate_power_state(unsigned int power_state);
 
-/* Gets the SPR for BL32 entry */
-uint32_t fvp_get_spsr_for_bl32_entry(void);
+/* BL1 utility functions */
+void arm_bl1_early_platform_setup(void);
+void arm_bl1_platform_setup(void);
+void arm_bl1_plat_arch_setup(void);
 
-/* Gets the SPSR for BL33 entry */
-uint32_t fvp_get_spsr_for_bl33_entry(void);
+/* BL2 utility functions */
+void arm_bl2_early_platform_setup(meminfo_t *mem_layout);
+void arm_bl2_platform_setup(void);
+void arm_bl2_plat_arch_setup(void);
+uint32_t arm_get_spsr_for_bl32_entry(void);
+uint32_t arm_get_spsr_for_bl33_entry(void);
+
+/* BL3-1 utility functions */
+void arm_bl31_early_platform_setup(bl31_params_t *from_bl2,
+				void *plat_params_from_bl2);
+void arm_bl31_platform_setup(void);
+void arm_bl31_plat_arch_setup(void);
+
+/* TSP utility functions */
+void arm_tsp_early_platform_setup(void);
+
+
+/*
+ * Mandatory functions required in ARM standard platforms
+ */
+void plat_arm_gic_init(void);
+void plat_arm_security_setup(void);
+void plat_arm_pwrc_setup(void);
+
+/*
+ * Optional functions required in ARM standard platforms
+ */
+void plat_arm_io_setup(void);
+int plat_arm_get_alt_image_source(
+	const uintptr_t image_spec,
+	uintptr_t *dev_handle);
+void plat_arm_topology_setup(void);
 
 
-#endif /* __FVP_PRIVATE_H__ */
+#endif /* __PLAT_ARM_H__ */

include/plat/arm/css/common/aarch64/css_macros.S

+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __CSS_MACROS_S__
+#define __CSS_MACROS_S__
+
+#include <arm_macros.S>
+#include <platform_def.h>
+
+	/* ---------------------------------------------
+	 * The below required platform porting macro
+	 * prints out relevant GIC registers whenever an
+	 * unhandled exception is taken in BL3-1.
+	 * Clobbers: x0 - x10, x16, x17, sp
+	 * ---------------------------------------------
+	 */
+	.macro plat_print_gic_regs
+	mov_imm	x16, PLAT_CSS_GICD_BASE
+	mov_imm	x17, PLAT_CSS_GICC_BASE
+	arm_print_gic_regs
+	.endm
+
+
+#endif /* __CSS_MACROS_S__ */

include/plat/arm/css/common/css_def.h

+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CSS_DEF_H__
+#define __CSS_DEF_H__
+
+#include <arm_def.h>
+#include <tzc400.h>
+
+/*************************************************************************
+ * Definitions common to all ARM Compute SubSystems (CSS)
+ *************************************************************************/
+#define MHU_SECURE_BASE			ARM_SHARED_RAM_BASE
+#define MHU_SECURE_SIZE			ARM_SHARED_RAM_SIZE
+#define MHU_PAYLOAD_CACHED		0
+
+#define TRUSTED_MAILBOXES_BASE		MHU_SECURE_BASE
+#define TRUSTED_MAILBOX_SHIFT		4
+
+#define NSROM_BASE			0x1f000000
+#define NSROM_SIZE			0x00001000
+
+/* Following covers CSS Peripherals excluding NSROM and NSRAM  */
+#define CSS_DEVICE_BASE			0x20000000
+#define CSS_DEVICE_SIZE			0x0e000000
+#define MHU_BASE			0x2b1f0000
+
+#define NSRAM_BASE			0x2e000000
+#define NSRAM_SIZE			0x00008000
+
+/* The slave_bootsecure controls access to GPU, DMC and CS. */
+#define CSS_NIC400_SLAVE_BOOTSECURE	8
+
+/* Interrupt handling constants */
+#define CSS_IRQ_MHU			69
+#define CSS_IRQ_GPU_SMMU_0		71
+#define CSS_IRQ_GPU_SMMU_1		73
+#define CSS_IRQ_ETR_SMMU		75
+#define CSS_IRQ_TZC			80
+#define CSS_IRQ_TZ_WDOG			86
+
+/* SCP <=> AP boot configuration */
+#define SCP_BOOT_CFG_ADDR		0x04000080
+#define PRIMARY_CPU_SHIFT		8
+#define PRIMARY_CPU_MASK		0xf
+
+
+#define CSS_MAP_DEVICE			MAP_REGION_FLAT(		\
+						CSS_DEVICE_BASE,	\
+						CSS_DEVICE_SIZE,	\
+						MT_DEVICE | MT_RW | MT_SECURE)
+
+
+/*************************************************************************
+ * Required platform porting definitions common to all
+ * ARM Compute SubSystems (CSS)
+ ************************************************************************/
+
+/*
+ * Load address of BL3-0 in CSS platform ports
+ * BL3-0 is loaded to the same place as BL3-1.  Once BL3-0 is transferred to the
+ * SCP, it is discarded and BL3-1 is loaded over the top.
+ */
+#define BL30_BASE			BL31_BASE
+
+#define PLAT_ARM_SHARED_RAM_CACHED	MHU_PAYLOAD_CACHED
+
+/* Load address of Non-Secure Image for CSS platform ports */
+#define PLAT_ARM_NS_IMAGE_OFFSET	0xE0000000
+
+/* TZC related constants */
+#define PLAT_ARM_TZC_FILTERS		REG_ATTR_FILTER_BIT_ALL
+
+
+#endif /* __CSS_DEF_H__ */

plat/fvp/fvp_trusted_boot.c → include/plat/arm/soc/common/soc_css.h

@@ -28,18 +28,20 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <assert.h>
-#include <debug.h>
-#include "fvp_def.h"
-#include "fvp_private.h"
+#ifndef __SOC_CSS_H__
+#define __SOC_CSS_H__
 
 /*
- * Check the validity of the key
- *
- * 0 = success, Otherwise = error
+ * Utility functions for ARM CSS SoCs
  */
-int plat_match_rotpk(const unsigned char *key_buf, unsigned int key_len)
+void soc_css_init_nic400(void);
+void soc_css_init_pcie(void);
+
+inline void soc_css_security_setup(void)
 {
-	/* TODO: check against the ROT key stored in the platform */
-	return 0;
+	soc_css_init_nic400();
+	soc_css_init_pcie();
 }
+
+
+#endif /* __SOC_CSS_H__ */

include/plat/arm/soc/common/soc_css_def.h

+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SOC_CSS_DEF_H__
+#define __SOC_CSS_DEF_H__
+
+#include <common_def.h>
+#include <xlat_tables.h>
+
+
+/*
+ * Definitions common to all ARM CSS SoCs
+ */
+
+/* Following covers ARM CSS SoC Peripherals and PCIe expansion area */
+#define SOC_CSS_DEVICE_BASE		0x40000000
+#define SOC_CSS_DEVICE_SIZE		0x40000000
+#define SOC_CSS_PCIE_CONTROL_BASE	0x7ff20000
+
+/* PL011 UART related constants */
+#define SOC_CSS_UART0_BASE		0x7ff80000
+#define SOC_CSS_UART1_BASE		0x7ff70000
+
+#define SOC_CSS_UART0_CLK_IN_HZ		7273800
+#define SOC_CSS_UART1_CLK_IN_HZ		7273800
+
+/* SoC NIC-400 Global Programmers View (GPV) */
+#define SOC_CSS_NIC400_BASE		0x7fd00000
+
+#define SOC_CSS_NIC400_USB_EHCI		0
+#define SOC_CSS_NIC400_TLX_MASTER	1
+#define SOC_CSS_NIC400_USB_OHCI		2
+#define SOC_CSS_NIC400_PL354_SMC	3
+/*
+ * The apb4_bridge controls access to:
+ *   - the PCIe configuration registers
+ *   - the MMU units for USB, HDLCD and DMA
+ */
+#define SOC_CSS_NIC400_APB4_BRIDGE	4
+
+
+#define SOC_CSS_MAP_DEVICE		MAP_REGION_FLAT(		\
+						SOC_CSS_DEVICE_BASE,	\
+						SOC_CSS_DEVICE_SIZE,	\
+						MT_DEVICE | MT_RW | MT_SECURE)
+
+
+/*
+ * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs.
+ */
+#define SOC_CSS_NIC400_BOOTSEC_BRIDGE	5
+#define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1	(1 << 12)
+
+/*
+ * Required platform porting definitions common to all ARM CSS SoCs
+ */
+
+/* 2MB used for SCP DDR retraining */
+#define PLAT_ARM_SCP_TZC_DRAM1_SIZE	MAKE_ULL(0x00200000)
+
+
+#endif /* __SOC_CSS_DEF_H__ */

include/plat/common/common_def.h

+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __COMMON_DEF_H__
+#define __COMMON_DEF_H__
+
+/******************************************************************************
+ * Required platform porting definitions that are expected to be common to
+ * all platforms
+ *****************************************************************************/
+
+/*
+ * Platform binary types for linking
+ */
+#define PLATFORM_LINKER_FORMAT          "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH            aarch64
+
+
+/*
+ * Generic platform constants
+ */
+#define FIRMWARE_WELCOME_STR		"Booting Trusted Firmware\n"
+
+/* Trusted Boot Firmware BL2 */
+#define BL2_IMAGE_NAME			"bl2.bin"
+
+/* SCP Firmware BL3-0 */
+#define BL30_IMAGE_NAME			"bl30.bin"
+
+/* EL3 Runtime Firmware BL31 */
+#define BL31_IMAGE_NAME			"bl31.bin"
+
+/* Secure Payload BL32 (Trusted OS) */
+#define BL32_IMAGE_NAME			"bl32.bin"
+
+/* Non-Trusted Firmware BL33 */
+#define BL33_IMAGE_NAME			"bl33.bin"
+
+/* Firmware Image Package */
+#define FIP_IMAGE_NAME			"fip.bin"
+
+#if TRUSTED_BOARD_BOOT
+/* Certificates */
+# define BL2_CERT_NAME			"bl2.crt"
+# define TRUSTED_KEY_CERT_NAME		"trusted_key.crt"
+
+# define BL30_KEY_CERT_NAME		"bl30_key.crt"
+# define BL31_KEY_CERT_NAME		"bl31_key.crt"
+# define BL32_KEY_CERT_NAME		"bl32_key.crt"
+# define BL33_KEY_CERT_NAME		"bl33_key.crt"
+
+# define BL30_CERT_NAME			"bl30.crt"
+# define BL31_CERT_NAME			"bl31.crt"
+# define BL32_CERT_NAME			"bl32.crt"
+# define BL33_CERT_NAME			"bl33.crt"
+#endif /* TRUSTED_BOARD_BOOT */
+
+/*
+ * Some of the platform porting definitions use the 'ull' suffix in order to
+ * avoid subtle integer overflow errors due to implicit integer type promotion
+ * when working with 32-bit values.
+ *
+ * The TSP linker script includes some of these definitions to define the BL3-2
+ * memory map, but the GNU LD does not support the 'ull' suffix, causing the
+ * build process to fail. To solve this problem, the auxiliary macro MAKE_ULL(x)
+ * will add the 'ull' suffix only when the macro __LINKER__  is not defined
+ * (__LINKER__ is defined in the command line to preprocess the linker script).
+ * Constants in the linker script will not have the 'ull' suffix, but this is
+ * not a problem since the linker evaluates all constant expressions to 64 bit
+ * (assuming the target architecture is 64 bit).
+ */
+#ifndef __LINKER__
+  #define MAKE_ULL(x)			x##ull
+#else
+  #define MAKE_ULL(x)			x
+#endif
+
+
+#endif /* __COMMON_DEF_H__ */
+

plat/arm/board/common/aarch64/board_arm_helpers.S

+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <asm_macros.S>
+#include <bl_common.h>
+#include <v2m_def.h>
+
+	.globl  plat_report_exception
+
+
+	/* ---------------------------------------------
+	 * void plat_report_exception(unsigned int type)
+	 * Function to report an unhandled exception
+	 * with platform-specific means.
+	 * On FVP platform, it updates the LEDs
+	 * to indicate where we are
+	 * ---------------------------------------------
+	 */
+func plat_report_exception
+	mrs	x1, CurrentEl
+	lsr	x1, x1, #MODE_EL_SHIFT
+	lsl	x1, x1, #V2M_SYS_LED_EL_SHIFT
+	lsl	x0, x0, #V2M_SYS_LED_EC_SHIFT
+	mov	x2, #(SECURE << V2M_SYS_LED_SS_SHIFT)
+	orr	x0, x0, x2
+	orr	x0, x0, x1
+	mov	x1, #V2M_SYSREGS_BASE
+	add	x1, x1, #V2M_SYS_LED
+	str	w0, [x1]
+	ret
+endfunc plat_report_exception

plat/juno/juno_trusted_boot.c → plat/arm/board/common/board_arm_trusted_boot.c

@@ -28,11 +28,8 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <assert.h>
-#include <debug.h>
-#include "juno_def.h"
-#include "juno_private.h"
-
+/* Weak definition may be overridden in specific platform */
+#pragma weak plat_match_rotpk
 /*
  * Check the validity of the key
  *

plat/arm/board/common/board_css.mk

+#
+# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of ARM nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+PLAT_INCLUDES		+=	-Iinclude/plat/arm/board/common/
+
+PLAT_BL_COMMON_SOURCES	+=	drivers/arm/pl011/pl011_console.S			\
+				plat/arm/board/common/aarch64/board_arm_helpers.S	\
+				plat/arm/board/common/board_css_common.c
+
+
+#BL1_SOURCES		+=
+
+#BL2_SOURCES		+=
+
+#BL31_SOURCES		+=
+
+ifneq (${TRUSTED_BOARD_BOOT},0)
+  BL1_SOURCES		+=	plat/arm/board/common/board_arm_trusted_boot.c
+  BL2_SOURCES		+=	plat/arm/board/common/board_arm_trusted_boot.c
+endif

plat/juno/include/platform_oid.h → plat/arm/board/common/board_css_common.c

@@ -27,43 +27,53 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
-
-#ifndef PLATFORM_OID_H_
-#define PLATFORM_OID_H_
+#include <arm_def.h>
+#include <plat_arm.h>
 
 /*
- * This is the list of the different extensions containing relevant information
- * to establish the chain of trust.
- *
- * The OIDs shown here are just an example. Real OIDs should be obtained from
- * the ITU-T.
+ * Table of regions for different BL stages to map using the MMU.
+ * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
+ * arm_configure_mmu_elx() will give the available subset of that,
  */
+#if IMAGE_BL1
+const mmap_region_t plat_arm_mmap[] = {
+	ARM_MAP_SHARED_RAM,
+	V2M_MAP_FLASH0,
+	V2M_MAP_IOFPGA,
+	CSS_MAP_DEVICE,
+	SOC_CSS_MAP_DEVICE,
+	{0}
+};
+#endif
+#if IMAGE_BL2
+const mmap_region_t plat_arm_mmap[] = {
+	ARM_MAP_SHARED_RAM,
+	V2M_MAP_FLASH0,
+	V2M_MAP_IOFPGA,
+	CSS_MAP_DEVICE,
+	SOC_CSS_MAP_DEVICE,
+	ARM_MAP_NS_DRAM1,
+	ARM_MAP_TSP_SEC_MEM,
+	{0}
+};
+#endif
+#if IMAGE_BL31
+const mmap_region_t plat_arm_mmap[] = {
+	ARM_MAP_SHARED_RAM,
+	V2M_MAP_IOFPGA,
+	CSS_MAP_DEVICE,
+	SOC_CSS_MAP_DEVICE,
+	{0}
+};
+#endif
+#if IMAGE_BL32
+const mmap_region_t plat_arm_mmap[] = {
+	V2M_MAP_IOFPGA,
+	CSS_MAP_DEVICE,
+	SOC_CSS_MAP_DEVICE,
+	{0}
+};
+#endif
 
-/* Non-volatile counter extensions */
-#define TZ_FW_NVCOUNTER_OID		"1.2.3.1"
-#define NTZ_FW_NVCOUNTER_OID		"1.2.3.2"
-
-/* BL2 extensions */
-#define BL2_HASH_OID			"1.2.3.3"
-
-/* Trusted Key extensions */
-#define TZ_WORLD_PK_OID			"1.2.3.4"
-#define NTZ_WORLD_PK_OID		"1.2.3.5"
-
-/* BL3-1 extensions */
-#define BL31_CONTENT_CERT_PK_OID	"1.2.3.6"
-#define BL31_HASH_OID			"1.2.3.7"
-
-/* BL3-0 extensions */
-#define BL30_CONTENT_CERT_PK_OID	"1.2.3.8"
-#define BL30_HASH_OID			"1.2.3.9"
-
-/* BL3-2 extensions */
-#define BL32_CONTENT_CERT_PK_OID	"1.2.3.10"
-#define BL32_HASH_OID			"1.2.3.11"
-
-/* BL3-3 extensions */
-#define BL33_CONTENT_CERT_PK_OID	"1.2.3.12"
-#define BL33_HASH_OID			"1.2.3.13"
+ARM_CASSERT_MMAP
 
-#endif /* PLATFORM_OID_H_ */

plat/fvp/aarch64/fvp_common.c → plat/arm/board/fvp/aarch64/fvp_common.c

 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -28,35 +28,24 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <arch.h>
-#include <arch_helpers.h>
+#include <arm_config.h>
+#include <arm_def.h>
 #include <arm_gic.h>
-#include <bl_common.h>
 #include <cci.h>
 #include <debug.h>
 #include <mmio.h>
-#include <platform.h>
-#include <platform_def.h>
-#include <plat_config.h>
-#include <xlat_tables.h>
+#include <plat_arm.h>
+#include <v2m_def.h>
 #include "../fvp_def.h"
 
 /*******************************************************************************
- * plat_config holds the characteristics of the differences between the three
- * FVP platforms (Base, A53_A57 & Foundation). It will be populated during cold
- * boot at each boot stage by the primary before enabling the MMU (to allow cci
+ * arm_config holds the characteristics of the differences between the three FVP
+ * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
+ * at each boot stage by the primary before enabling the MMU (to allow cci
  * configuration) & used thereafter. Each BL will have its own copy to allow
  * independent operation.
  ******************************************************************************/
-plat_config_t plat_config;
-
-#define MAP_SHARED_RAM	MAP_REGION_FLAT(FVP_SHARED_MEM_BASE,		\
-					FVP_SHARED_MEM_SIZE,		\
-					MT_MEMORY | MT_RW | MT_SECURE)
-
-#define MAP_FLASH0	MAP_REGION_FLAT(FLASH0_BASE,			\
-					FLASH0_SIZE,			\
-					MT_MEMORY | MT_RO | MT_SECURE)
+arm_config_t arm_config;
 
 #define MAP_DEVICE0	MAP_REGION_FLAT(DEVICE0_BASE,			\
 					DEVICE0_SIZE,			\
@@ -66,122 +55,79 @@ plat_config_t plat_config;
 					DEVICE1_SIZE,			\
 					MT_DEVICE | MT_RW | MT_SECURE)
 
-#define MAP_DRAM1_NS	MAP_REGION_FLAT(DRAM1_NS_BASE,			\
-					DRAM1_NS_SIZE,			\
-					MT_MEMORY | MT_RW | MT_NS)
-
-#define MAP_TSP_SEC_MEM	MAP_REGION_FLAT(TSP_SEC_MEM_BASE,		\
-					TSP_SEC_MEM_SIZE,		\
-					MT_MEMORY | MT_RW | MT_SECURE)
-
 /*
  * Table of regions for various BL stages to map using the MMU.
  * This doesn't include TZRAM as the 'mem_layout' argument passed to
- * configure_mmu_elx() will give the available subset of that,
+ * arm_configure_mmu_elx() will give the available subset of that,
  */
 #if IMAGE_BL1
-const mmap_region_t fvp_mmap[] = {
-	MAP_SHARED_RAM,
-	MAP_FLASH0,
+const mmap_region_t plat_arm_mmap[] = {
+	ARM_MAP_SHARED_RAM,
+	V2M_MAP_FLASH0,
+	V2M_MAP_IOFPGA,
 	MAP_DEVICE0,
 	MAP_DEVICE1,
 	{0}
 };
 #endif
 #if IMAGE_BL2
-const mmap_region_t fvp_mmap[] = {
-	MAP_SHARED_RAM,
-	MAP_FLASH0,
+const mmap_region_t plat_arm_mmap[] = {
+	ARM_MAP_SHARED_RAM,
+	V2M_MAP_FLASH0,
+	V2M_MAP_IOFPGA,
 	MAP_DEVICE0,
 	MAP_DEVICE1,
-	MAP_DRAM1_NS,
-	MAP_TSP_SEC_MEM,
+	ARM_MAP_NS_DRAM1,
+	ARM_MAP_TSP_SEC_MEM,
 	{0}
 };
 #endif
 #if IMAGE_BL31
-const mmap_region_t fvp_mmap[] = {
-	MAP_SHARED_RAM,
+const mmap_region_t plat_arm_mmap[] = {
+	ARM_MAP_SHARED_RAM,
+	V2M_MAP_IOFPGA,
 	MAP_DEVICE0,
 	MAP_DEVICE1,
 	{0}
 };
 #endif
 #if IMAGE_BL32
-const mmap_region_t fvp_mmap[] = {
+const mmap_region_t plat_arm_mmap[] = {
+	V2M_MAP_IOFPGA,
 	MAP_DEVICE0,
 	MAP_DEVICE1,
 	{0}
 };
 #endif
 
-CASSERT(ARRAY_SIZE(fvp_mmap) + FVP_BL_REGIONS \
-		<= MAX_MMAP_REGIONS, assert_max_mmap_regions);
+ARM_CASSERT_MMAP
 
+
+#if IMAGE_BL31 || IMAGE_BL32
 /* Array of secure interrupts to be configured by the gic driver */
 const unsigned int irq_sec_array[] = {
 	IRQ_TZ_WDOG,
-	IRQ_SEC_PHY_TIMER,
-	IRQ_SEC_SGI_0,
-	IRQ_SEC_SGI_1,
-	IRQ_SEC_SGI_2,
-	IRQ_SEC_SGI_3,
-	IRQ_SEC_SGI_4,
-	IRQ_SEC_SGI_5,
-	IRQ_SEC_SGI_6,
-	IRQ_SEC_SGI_7
+	ARM_IRQ_SEC_PHY_TIMER,
+	ARM_IRQ_SEC_SGI_0,
+	ARM_IRQ_SEC_SGI_1,
+	ARM_IRQ_SEC_SGI_2,
+	ARM_IRQ_SEC_SGI_3,
+	ARM_IRQ_SEC_SGI_4,
+	ARM_IRQ_SEC_SGI_5,
+	ARM_IRQ_SEC_SGI_6,
+	ARM_IRQ_SEC_SGI_7
 };
 
-/*******************************************************************************
- * Macro generating the code for the function setting up the pagetables as per
- * the platform memory map & initialize the mmu, for the given exception level
- ******************************************************************************/
-#if USE_COHERENT_MEM
-#define DEFINE_CONFIGURE_MMU_EL(_el)				\
-	void fvp_configure_mmu_el##_el(unsigned long total_base,	\
-				   unsigned long total_size,		\
-				   unsigned long ro_start,		\
-				   unsigned long ro_limit,		\
-				   unsigned long coh_start,		\
-				   unsigned long coh_limit)		\
-	{								\
-		mmap_add_region(total_base, total_base,			\
-				total_size,				\
-				MT_MEMORY | MT_RW | MT_SECURE);		\
-		mmap_add_region(ro_start, ro_start,			\
-				ro_limit - ro_start,			\
-				MT_MEMORY | MT_RO | MT_SECURE);		\
-		mmap_add_region(coh_start, coh_start,			\
-				coh_limit - coh_start,			\
-				MT_DEVICE | MT_RW | MT_SECURE);		\
-		mmap_add(fvp_mmap);					\
-		init_xlat_tables();					\
-									\
-		enable_mmu_el##_el(0);					\
-	}
-#else
-#define DEFINE_CONFIGURE_MMU_EL(_el)				\
-	void fvp_configure_mmu_el##_el(unsigned long total_base,	\
-				   unsigned long total_size,		\
-				   unsigned long ro_start,		\
-				   unsigned long ro_limit)		\
-	{								\
-		mmap_add_region(total_base, total_base,			\
-				total_size,				\
-				MT_MEMORY | MT_RW | MT_SECURE);		\
-		mmap_add_region(ro_start, ro_start,			\
-				ro_limit - ro_start,			\
-				MT_MEMORY | MT_RO | MT_SECURE);		\
-		mmap_add(fvp_mmap);					\
-		init_xlat_tables();					\
-									\
-		enable_mmu_el##_el(0);					\
-	}
-#endif
+void plat_arm_gic_init(void)
+{
+	arm_gic_init(arm_config.gicc_base,
+		arm_config.gicd_base,
+		BASE_GICR_BASE,
+		irq_sec_array,
+		ARRAY_SIZE(irq_sec_array));
+}
 
-/* Define EL1 and EL3 variants of the function initialising the MMU */
-DEFINE_CONFIGURE_MMU_EL(1)
-DEFINE_CONFIGURE_MMU_EL(3)
+#endif
 
 /*******************************************************************************
  * A single boot loader stack is expected to work on both the Foundation FVP
@@ -190,15 +136,15 @@ DEFINE_CONFIGURE_MMU_EL(3)
  * these platforms. This information is stored in a per-BL array to allow the
  * code to take the correct path.Per BL platform configuration.
  ******************************************************************************/
-int fvp_config_setup(void)
+void fvp_config_setup(void)
 {
 	unsigned int rev, hbi, bld, arch, sys_id;
 
-	sys_id = mmio_read_32(VE_SYSREGS_BASE + V2M_SYS_ID);
-	rev = (sys_id >> SYS_ID_REV_SHIFT) & SYS_ID_REV_MASK;
-	hbi = (sys_id >> SYS_ID_HBI_SHIFT) & SYS_ID_HBI_MASK;
-	bld = (sys_id >> SYS_ID_BLD_SHIFT) & SYS_ID_BLD_MASK;
-	arch = (sys_id >> SYS_ID_ARCH_SHIFT) & SYS_ID_ARCH_MASK;
+	sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
+	rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
+	hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
+	bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
+	arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
 
 	if (arch != ARCH_MODEL) {
 		ERROR("This firmware is for FVP models\n");
@@ -211,16 +157,16 @@ int fvp_config_setup(void)
 	 */
 	switch (bld) {
 	case BLD_GIC_VE_MMAP:
-		plat_config.gicd_base = VE_GICD_BASE;
-		plat_config.gicc_base = VE_GICC_BASE;
-		plat_config.gich_base = VE_GICH_BASE;
-		plat_config.gicv_base = VE_GICV_BASE;
+		arm_config.gicd_base = VE_GICD_BASE;
+		arm_config.gicc_base = VE_GICC_BASE;
+		arm_config.gich_base = VE_GICH_BASE;
+		arm_config.gicv_base = VE_GICV_BASE;
 		break;
 	case BLD_GIC_A53A57_MMAP:
-		plat_config.gicd_base = BASE_GICD_BASE;
-		plat_config.gicc_base = BASE_GICC_BASE;
-		plat_config.gich_base = BASE_GICH_BASE;
-		plat_config.gicv_base = BASE_GICV_BASE;
+		arm_config.gicd_base = BASE_GICD_BASE;
+		arm_config.gicc_base = BASE_GICC_BASE;
+		arm_config.gich_base = BASE_GICH_BASE;
+		arm_config.gicv_base = BASE_GICV_BASE;
 		break;
 	default:
 		ERROR("Unsupported board build %x\n", bld);
@@ -232,36 +178,37 @@ int fvp_config_setup(void)
 	 * for the Foundation FVP.
 	 */
 	switch (hbi) {
-	case HBI_FOUNDATION:
-		plat_config.max_aff0 = 4;
-		plat_config.max_aff1 = 1;
-		plat_config.flags = 0;
+	case HBI_FOUNDATION_FVP:
+		arm_config.max_aff0 = 4;
+		arm_config.max_aff1 = 1;
+		arm_config.flags = 0;
 
 		/*
 		 * Check for supported revisions of Foundation FVP
 		 * Allow future revisions to run but emit warning diagnostic
 		 */
 		switch (rev) {
-		case REV_FOUNDATION_V2_0:
-		case REV_FOUNDATION_V2_1:
+		case REV_FOUNDATION_FVP_V2_0:
+		case REV_FOUNDATION_FVP_V2_1:
+		case REV_FOUNDATION_FVP_v9_1:
 			break;
 		default:
 			WARN("Unrecognized Foundation FVP revision %x\n", rev);
 			break;
 		}
 		break;
-	case HBI_FVP_BASE:
-		plat_config.max_aff0 = 4;
-		plat_config.max_aff1 = 2;
-		plat_config.flags |= CONFIG_BASE_MMAP | CONFIG_HAS_CCI |
-			CONFIG_HAS_TZC;
+	case HBI_BASE_FVP:
+		arm_config.max_aff0 = 4;
+		arm_config.max_aff1 = 2;
+		arm_config.flags |= ARM_CONFIG_BASE_MMAP |
+			ARM_CONFIG_HAS_CCI | ARM_CONFIG_HAS_TZC;
 
 		/*
 		 * Check for supported revisions
 		 * Allow future revisions to run but emit warning diagnostic
 		 */
 		switch (rev) {
-		case REV_FVP_BASE_V0:
+		case REV_BASE_FVP_V0:
 			break;
 		default:
 			WARN("Unrecognized Base FVP revision %x\n", rev);
@@ -272,103 +219,26 @@ int fvp_config_setup(void)
 		ERROR("Unsupported board HBI number 0x%x\n", hbi);
 		panic();
 	}
-
-	return 0;
-}
-
-unsigned long plat_get_ns_image_entrypoint(void)
-{
-	return NS_IMAGE_OFFSET;
-}
-
-uint64_t plat_get_syscnt_freq(void)
-{
-	uint64_t counter_base_frequency;
-
-	/* Read the frequency from Frequency modes table */
-	counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
-
-	/* The first entry of the frequency modes table must not be 0 */
-	if (counter_base_frequency == 0)
-		panic();
-
-	return counter_base_frequency;
 }
 
-/* Map of CCI masters with the slave interfaces they are connected */
-static const int cci_map[] = {
-	CCI400_CLUSTER0_SL_IFACE_IX,
-	CCI400_CLUSTER1_SL_IFACE_IX
-};
 
 void fvp_cci_init(void)
 {
 	/*
 	 * Initialize CCI-400 driver
 	 */
-	if (plat_config.flags & CONFIG_HAS_CCI)
-		cci_init(CCI400_BASE,
-			cci_map,
-			ARRAY_SIZE(cci_map));
+	if (arm_config.flags & ARM_CONFIG_HAS_CCI)
+		arm_cci_init();
 }
 
 void fvp_cci_enable(void)
 {
-	if (plat_config.flags & CONFIG_HAS_CCI)
+	if (arm_config.flags & ARM_CONFIG_HAS_CCI)
 		cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
 }
 
 void fvp_cci_disable(void)
 {
-	if (plat_config.flags & CONFIG_HAS_CCI)
+	if (arm_config.flags & ARM_CONFIG_HAS_CCI)
 		cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
 }
-
-void fvp_gic_init(void)
-{
-	arm_gic_init(plat_config.gicc_base,
-		plat_config.gicd_base,
-		BASE_GICR_BASE,
-		irq_sec_array,
-		ARRAY_SIZE(irq_sec_array));
-}
-
-
-/*******************************************************************************
- * Gets SPSR for BL32 entry
- ******************************************************************************/
-uint32_t fvp_get_spsr_for_bl32_entry(void)
-{
-	/*
-	 * The Secure Payload Dispatcher service is responsible for
-	 * setting the SPSR prior to entry into the BL32 image.
-	 */
-	return 0;
-}
-
-/*******************************************************************************
- * Gets SPSR for BL33 entry
- ******************************************************************************/
-uint32_t fvp_get_spsr_for_bl33_entry(void)
-{
-	unsigned long el_status;
-	unsigned int mode;
-	uint32_t spsr;
-
-	/* Figure out what mode we enter the non-secure world in */
-	el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
-	el_status &= ID_AA64PFR0_ELX_MASK;
-
-	if (el_status)
-		mode = MODE_EL2;
-	else
-		mode = MODE_EL1;
-
-	/*
-	 * TODO: Consider the possibility of specifying the SPSR in
-	 * the FIP ToC and allowing the platform to have a say as
-	 * well.
-	 */
-	spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
-	return spsr;
-}

plat/fvp/aarch64/fvp_helpers.S → plat/arm/board/fvp/aarch64/fvp_helpers.S

 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -30,24 +30,21 @@
 
 #include <arch.h>
 #include <asm_macros.S>
-#include <bl_common.h>
 #include <gic_v2.h>
 #include <platform_def.h>
-#include <pl011.h>
+#include <v2m_def.h>
 #include "../drivers/pwrc/fvp_pwrc.h"
+#include "../fvp_def.h"
 
-	.globl	platform_get_entrypoint
 	.globl	plat_secondary_cold_boot_setup
+	.globl	platform_get_entrypoint
 	.globl	platform_mem_init
-	.globl	plat_report_exception
 	.globl	platform_is_primary_cpu
-	.globl	plat_crash_console_init
-	.globl	plat_crash_console_putc
 
 	.macro	fvp_choose_gicmmap  param1, param2, x_tmp, w_tmp, res
-	ldr	\x_tmp, =VE_SYSREGS_BASE + V2M_SYS_ID
+	ldr	\x_tmp, =V2M_SYSREGS_BASE + V2M_SYS_ID
 	ldr	\w_tmp, [\x_tmp]
-	ubfx	\w_tmp, \w_tmp, #SYS_ID_BLD_SHIFT, #SYS_ID_BLD_LENGTH
+	ubfx	\w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH
 	cmp	\w_tmp, #BLD_GIC_VE_MMAP
 	csel	\res, \param1, \param2, eq
 	.endm
@@ -143,7 +140,7 @@ warm_reset:
 	 */
 	ldr	x10, =MBOX_BASE
 	bl	platform_get_core_pos
-	lsl	x0, x0, #CACHE_WRITEBACK_SHIFT
+	lsl	x0, x0, #ARM_CACHE_WRITEBACK_SHIFT
 	ldr	x0, [x10, x0]
 	cbz	x0, _panic
 exit:
@@ -174,27 +171,6 @@ loop:
 	ret
 endfunc platform_mem_init
 
-	/* ---------------------------------------------
-	 * void plat_report_exception(unsigned int type)
-	 * Function to report an unhandled exception
-	 * with platform-specific means.
-	 * On FVP platform, it updates the LEDs
-	 * to indicate where we are
-	 * ---------------------------------------------
-	 */
-func plat_report_exception
-	mrs	x1, CurrentEl
-	lsr	x1, x1, #MODE_EL_SHIFT
-	lsl	x1, x1, #SYS_LED_EL_SHIFT
-	lsl	x0, x0, #SYS_LED_EC_SHIFT
-	mov	x2, #(SECURE << SYS_LED_SS_SHIFT)
-	orr	x0, x0, x2
-	orr	x0, x0, x1
-	mov	x1, #VE_SYSREGS_BASE
-	add	x1, x1, #V2M_SYS_LED
-	str	w0, [x1]
-	ret
-endfunc plat_report_exception
 
 func platform_is_primary_cpu
 	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
@@ -202,32 +178,3 @@ func platform_is_primary_cpu
 	cset	x0, eq
 	ret
 endfunc platform_is_primary_cpu
-
-	/* Define a crash console for the plaform */
-#define FVP_CRASH_CONSOLE_BASE		PL011_UART1_BASE
-
-	/* ---------------------------------------------
-	 * int plat_crash_console_init(void)
-	 * Function to initialize the crash console
-	 * without a C Runtime to print crash report.
-	 * Clobber list : x0, x1, x2
-	 * ---------------------------------------------
-	 */
-func plat_crash_console_init
-	mov_imm	x0, FVP_CRASH_CONSOLE_BASE
-	mov_imm	x1, PL011_UART1_CLK_IN_HZ
-	mov_imm	x2, PL011_BAUDRATE
-	b	console_core_init
-endfunc plat_crash_console_init
-
-	/* ---------------------------------------------
-	 * int plat_crash_console_putc(int c)
-	 * Function to print a character on the crash
-	 * console without a C Runtime.
-	 * Clobber list : x1, x2
-	 * ---------------------------------------------
-	 */
-func plat_crash_console_putc
-	mov_imm	x1, FVP_CRASH_CONSOLE_BASE
-	b	console_core_putc
-endfunc plat_crash_console_putc

plat/fvp/drivers/pwrc/fvp_pwrc.c → plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c

 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -30,6 +30,7 @@
 
 #include <bakery_lock.h>
 #include <mmio.h>
+#include <plat_arm.h>
 #include "../../fvp_def.h"
 #include "../../fvp_private.h"
 #include "fvp_pwrc.h"
@@ -38,12 +39,7 @@
  * TODO: Someday there will be a generic power controller api. At the moment
  * each platform has its own pwrc so just exporting functions is fine.
  */
-#if USE_COHERENT_MEM
-static bakery_lock_t pwrc_lock __attribute__ ((section("tzfw_coherent_mem")));
-#define LOCK_ARG	&pwrc_lock
-#else
-#define LOCK_ARG	FVP_PWRC_BAKERY_ID
-#endif
+ARM_INSTANTIATE_LOCK
 
 unsigned int fvp_pwrc_get_cpu_wkr(unsigned long mpidr)
 {
@@ -53,56 +49,54 @@ unsigned int fvp_pwrc_get_cpu_wkr(unsigned long mpidr)
 unsigned int fvp_pwrc_read_psysr(unsigned long mpidr)
 {
 	unsigned int rc;
-	fvp_lock_get(LOCK_ARG);
+	arm_lock_get();
 	mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr);
 	rc = mmio_read_32(PWRC_BASE + PSYSR_OFF);
-	fvp_lock_release(LOCK_ARG);
+	arm_lock_release();
 	return rc;
 }
 
 void fvp_pwrc_write_pponr(unsigned long mpidr)
 {
-	fvp_lock_get(LOCK_ARG);
+	arm_lock_get();
 	mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr);
-	fvp_lock_release(LOCK_ARG);
+	arm_lock_release();
 }
 
 void fvp_pwrc_write_ppoffr(unsigned long mpidr)
 {
-	fvp_lock_get(LOCK_ARG);
+	arm_lock_get();
 	mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr);
-	fvp_lock_release(LOCK_ARG);
+	arm_lock_release();
 }
 
 void fvp_pwrc_set_wen(unsigned long mpidr)
 {
-	fvp_lock_get(LOCK_ARG);
+	arm_lock_get();
 	mmio_write_32(PWRC_BASE + PWKUPR_OFF,
 		      (unsigned int) (PWKUPR_WEN | mpidr));
-	fvp_lock_release(LOCK_ARG);
+	arm_lock_release();
 }
 
 void fvp_pwrc_clr_wen(unsigned long mpidr)
 {
-	fvp_lock_get(LOCK_ARG);
+	arm_lock_get();
 	mmio_write_32(PWRC_BASE + PWKUPR_OFF,
 		      (unsigned int) mpidr);
-	fvp_lock_release(LOCK_ARG);
+	arm_lock_release();
 }
 
 void fvp_pwrc_write_pcoffr(unsigned long mpidr)
 {
-	fvp_lock_get(LOCK_ARG);
+	arm_lock_get();
 	mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr);
-	fvp_lock_release(LOCK_ARG);
+	arm_lock_release();
 }
 
 /* Nothing else to do here apart from initializing the lock */
-int fvp_pwrc_setup(void)
+void plat_arm_pwrc_setup(void)
 {
-	fvp_lock_init(LOCK_ARG);
-
-	return 0;
+	arm_lock_init();
 }