From 474970535552b1e28b33461429b5492a1f1dd7cd Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 28 Dec 2016 16:11:41 +0900
Subject: [PATCH] Move BL_COHERENT_RAM_BASE/END defines to common_def.h
We have lots of duplicated defines (and comment blocks too).
Move them to include/plat/common/common_def.h.
While we are here, suffix the end address with _END instead of
_LIMIT. The _END is a better fit to indicate the linker-derived
real end address.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
include/plat/common/common_def.h | 10 ++++++++++
plat/arm/common/arm_bl1_setup.c | 18 ++----------------
plat/arm/common/arm_bl2_setup.c | 16 ++--------------
plat/arm/common/arm_bl2u_setup.c | 16 ++--------------
plat/arm/common/arm_bl31_setup.c | 16 ++--------------
plat/arm/common/sp_min/arm_sp_min_setup.c | 17 ++---------------
plat/arm/common/tsp/arm_tsp_setup.c | 17 ++---------------
plat/mediatek/mt6795/bl31_plat_setup.c | 18 +++---------------
plat/mediatek/mt8173/bl31_plat_setup.c | 20 ++++----------------
plat/nvidia/tegra/common/tegra_bl31_setup.c | 21 ++-------------------
plat/qemu/qemu_bl1_setup.c | 14 +-------------
plat/qemu/qemu_bl2_setup.c | 12 +-----------
plat/qemu/qemu_bl31_setup.c | 12 +-----------
plat/rockchip/common/bl31_plat_setup.c | 19 +++----------------
plat/xilinx/zynqmp/bl31_zynqmp_setup.c | 14 ++------------
plat/xilinx/zynqmp/tsp/tsp_plat_setup.c | 14 ++------------
16 files changed, 41 insertions(+), 213 deletions(-)
diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h
index 8f50622f1..65f31e7fd 100644
--- a/include/plat/common/common_def.h
+++ b/include/plat/common/common_def.h
@@ -137,4 +137,14 @@
#define BL1_RO_DATA_END 0
#endif /* SEPARATE_CODE_AND_RODATA */
+/*
+ * The next 2 constants identify the extents of the coherent memory region.
+ * These addresses are used by the MMU setup code and therefore they must be
+ * page-aligned. It is the responsibility of the linker script to ensure that
+ * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
+ * page-aligned addresses.
+ */
+#define BL_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
+#define BL_COHERENT_RAM_END (unsigned long)(&__COHERENT_RAM_END__)
+
#endif /* __COMMON_DEF_H__ */
diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index 91809fb48..81a87c440 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -39,20 +39,6 @@
#include <xlat_tables.h>
#include "../../../bl1/bl1_private.h"
-
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#endif
-
-
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak bl1_early_platform_setup
#pragma weak bl1_plat_arch_setup
@@ -128,8 +114,8 @@ void arm_bl1_plat_arch_setup(void)
BL1_RO_DATA_BASE,
BL1_RO_DATA_END
#if USE_COHERENT_MEM
- , BL1_COHERENT_RAM_BASE,
- BL1_COHERENT_RAM_LIMIT
+ , BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END
#endif
);
#ifdef AARCH32
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 293e5e517..5f3070809 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -39,18 +39,6 @@
#include <platform_def.h>
#include <string.h>
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#endif
-
/* Data structure which holds the extents of the trusted SRAM for BL2 */
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
@@ -242,8 +230,8 @@ void arm_bl2_plat_arch_setup(void)
BL_RO_DATA_BASE,
BL_RO_DATA_END
#if USE_COHERENT_MEM
- , BL2_COHERENT_RAM_BASE,
- BL2_COHERENT_RAM_LIMIT
+ , BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END
#endif
);
diff --git a/plat/arm/common/arm_bl2u_setup.c b/plat/arm/common/arm_bl2u_setup.c
index cad42f074..86317f656 100644
--- a/plat/arm/common/arm_bl2u_setup.c
+++ b/plat/arm/common/arm_bl2u_setup.c
@@ -36,18 +36,6 @@
#include <plat_arm.h>
#include <string.h>
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL2U_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL2U_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#endif
-
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak bl2u_platform_setup
#pragma weak bl2u_early_platform_setup
@@ -100,8 +88,8 @@ void arm_bl2u_plat_arch_setup(void)
BL_RO_DATA_END
#if USE_COHERENT_MEM
,
- BL2U_COHERENT_RAM_BASE,
- BL2U_COHERENT_RAM_LIMIT
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END
#endif
);
enable_mmu_el1(0);
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 6b6bae89f..d20d8cdd7 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -41,18 +41,6 @@
#define BL31_END (uintptr_t)(&__BL31_END__)
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__)
-#endif
-
/*
* Placeholder variables for copying the arguments that have been passed to
* BL31 from BL2.
@@ -292,8 +280,8 @@ void arm_bl31_plat_arch_setup(void)
BL_RO_DATA_BASE,
BL_RO_DATA_END
#if USE_COHERENT_MEM
- , BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT
+ , BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END
#endif
);
enable_mmu_el3(0);
diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c
index 40155f4e8..a472ceb98 100644
--- a/plat/arm/common/sp_min/arm_sp_min_setup.c
+++ b/plat/arm/common/sp_min/arm_sp_min_setup.c
@@ -39,19 +39,6 @@
#define BL32_END (uintptr_t)(&__BL32_END__)
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL32_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__)
-#define BL32_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__)
-#endif
-
-
static entry_point_info_t bl33_image_ep_info;
/* Weak definitions may be overridden in specific ARM standard platform */
@@ -206,8 +193,8 @@ void sp_min_plat_arch_setup(void)
BL_RO_DATA_BASE,
BL_RO_DATA_END
#if USE_COHERENT_MEM
- , BL32_COHERENT_RAM_BASE,
- BL32_COHERENT_RAM_LIMIT
+ , BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END
#endif
);
diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c
index 58c2b7ba6..20533ac0f 100644
--- a/plat/arm/common/tsp/arm_tsp_setup.c
+++ b/plat/arm/common/tsp/arm_tsp_setup.c
@@ -37,19 +37,6 @@
#define BL32_END (unsigned long)(&__BL32_END__)
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#endif
-
-
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak tsp_early_platform_setup
#pragma weak tsp_platform_setup
@@ -95,8 +82,8 @@ void tsp_plat_arch_setup(void)
BL_RO_DATA_BASE,
BL_RO_DATA_END
#if USE_COHERENT_MEM
- , BL32_COHERENT_RAM_BASE,
- BL32_COHERENT_RAM_LIMIT
+ , BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END
#endif
);
enable_mmu_el1(0);
diff --git a/plat/mediatek/mt6795/bl31_plat_setup.c b/plat/mediatek/mt6795/bl31_plat_setup.c
index 3a8612d34..af0858f0b 100644
--- a/plat/mediatek/mt6795/bl31_plat_setup.c
+++ b/plat/mediatek/mt6795/bl31_plat_setup.c
@@ -32,6 +32,7 @@
#include <arch_helpers.h>
#include <bl_common.h>
#include <cci.h>
+#include <common_def.h>
#include <console.h>
#include <context_mgmt.h>
#include <debug.h>
@@ -52,9 +53,6 @@
unsigned long __RO_START__;
unsigned long __RO_END__;
-unsigned long __COHERENT_RAM_START__;
-unsigned long __COHERENT_RAM_END__;
-
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
@@ -64,16 +62,6 @@ unsigned long __COHERENT_RAM_END__;
#define BL31_RO_BASE (unsigned long)(&__RO_START__)
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
/*
* Placeholder variables for copying the arguments that have been passed to
* BL3-1 from BL2.
@@ -323,8 +311,8 @@ void bl31_plat_arch_setup(void)
(TZRAM_SIZE & ~(PAGE_SIZE_MASK)),
(BL31_RO_BASE & ~(PAGE_SIZE_MASK)),
BL31_RO_LIMIT,
- BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT);
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
/* Initialize for ATF log buffer */
if (gteearg.atf_log_buf_size != 0) {
gteearg.atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE;
diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c
index 4626f81f3..ef18d0795 100644
--- a/plat/mediatek/mt8173/bl31_plat_setup.c
+++ b/plat/mediatek/mt8173/bl31_plat_setup.c
@@ -30,6 +30,7 @@
#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
+#include <common_def.h>
#include <console.h>
#include <debug.h>
#include <generic_delay_timer.h>
@@ -47,9 +48,6 @@
unsigned long __RO_START__;
unsigned long __RO_END__;
-unsigned long __COHERENT_RAM_START__;
-unsigned long __COHERENT_RAM_END__;
-
/*
* The next 3 constants identify the extents of the code, RO data region and the
* limit of the BL31 image. These addresses are used by the MMU setup code and
@@ -61,16 +59,6 @@ unsigned long __COHERENT_RAM_END__;
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL31_END (unsigned long)(&__BL31_END__)
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
@@ -191,10 +179,10 @@ void bl31_plat_arch_setup(void)
plat_cci_enable();
plat_configure_mmu_el3(BL31_RO_BASE,
- (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
+ BL_COHERENT_RAM_END - BL31_RO_BASE,
BL31_RO_BASE,
BL31_RO_LIMIT,
- BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT);
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
}
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 7e2bebe25..0fd7c8216 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -53,11 +53,6 @@ extern unsigned long __RO_START__;
extern unsigned long __RO_END__;
extern unsigned long __BL31_END__;
-#if USE_COHERENT_MEM
-extern unsigned long __COHERENT_RAM_START__;
-extern unsigned long __COHERENT_RAM_END__;
-#endif
-
extern uint64_t tegra_bl31_phys_base;
/*
@@ -71,18 +66,6 @@ extern uint64_t tegra_bl31_phys_base;
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL31_END (unsigned long)(&__BL31_END__)
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#endif
-
static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
.tzdram_size = (uint64_t)TZDRAM_SIZE
@@ -212,8 +195,8 @@ void bl31_plat_arch_setup(void)
MT_MEMORY | MT_RO | MT_SECURE);
#if USE_COHERENT_MEM
- coh_start = total_base + (BL31_COHERENT_RAM_BASE - BL31_RO_BASE);
- coh_size = BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE;
+ coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
+ coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
mmap_add_region(coh_start, coh_start,
coh_size,
diff --git a/plat/qemu/qemu_bl1_setup.c b/plat/qemu/qemu_bl1_setup.c
index 4438aaccc..21217d70f 100644
--- a/plat/qemu/qemu_bl1_setup.c
+++ b/plat/qemu/qemu_bl1_setup.c
@@ -36,18 +36,6 @@
#include <platform_def.h>
#include "qemu_private.h"
-
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
-
/*******************************************************************************
* Declarations of linker defined symbols which will tell us where BL1 lives
* in Trusted RAM
@@ -98,7 +86,7 @@ void bl1_plat_arch_setup(void)
qemu_configure_mmu_el3(bl1_tzram_layout.total_base,
bl1_tzram_layout.total_size,
BL1_RO_BASE, BL1_RO_LIMIT,
- BL1_COHERENT_RAM_BASE, BL1_COHERENT_RAM_LIMIT);
+ BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
}
void bl1_platform_setup(void)
diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c
index 24da2b6fd..dba3beeb5 100644
--- a/plat/qemu/qemu_bl2_setup.c
+++ b/plat/qemu/qemu_bl2_setup.c
@@ -46,16 +46,6 @@
#define BL2_RO_BASE (unsigned long)(&__RO_START__)
#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
/*******************************************************************************
* This structure represents the superset of information that is passed to
* BL3-1, e.g. while passing control to it from BL2, bl31_params
@@ -216,7 +206,7 @@ void bl2_plat_arch_setup(void)
qemu_configure_mmu_el1(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
BL2_RO_BASE, BL2_RO_LIMIT,
- BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT);
+ BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
}
/*******************************************************************************
diff --git a/plat/qemu/qemu_bl31_setup.c b/plat/qemu/qemu_bl31_setup.c
index 7a48358c1..547e13559 100644
--- a/plat/qemu/qemu_bl31_setup.c
+++ b/plat/qemu/qemu_bl31_setup.c
@@ -46,16 +46,6 @@
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL31_END (unsigned long)(&__BL31_END__)
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
/*
* Placeholder variables for copying the arguments that have been passed to
* BL3-1 from BL2.
@@ -105,7 +95,7 @@ void bl31_plat_arch_setup(void)
{
qemu_configure_mmu_el3(BL31_RO_BASE, (BL31_END - BL31_RO_BASE),
BL31_RO_BASE, BL31_RO_LIMIT,
- BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT);
+ BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
}
static const unsigned int irq_sec_array[] = {
diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c
index b073bde2f..66678d363 100644
--- a/plat/rockchip/common/bl31_plat_setup.c
+++ b/plat/rockchip/common/bl31_plat_setup.c
@@ -46,9 +46,6 @@
unsigned long __RO_START__;
unsigned long __RO_END__;
-unsigned long __COHERENT_RAM_START__;
-unsigned long __COHERENT_RAM_END__;
-
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
@@ -58,16 +55,6 @@ unsigned long __COHERENT_RAM_END__;
#define BL31_RO_BASE (unsigned long)(&__RO_START__)
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
@@ -144,9 +131,9 @@ void bl31_plat_arch_setup(void)
plat_cci_init();
plat_cci_enable();
plat_configure_mmu_el3(BL31_RO_BASE,
- (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
+ BL_COHERENT_RAM_END - BL31_RO_BASE,
BL31_RO_BASE,
BL31_RO_LIMIT,
- BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT);
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
}
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index f6c4b98ea..c70fc3e4c 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -40,16 +40,6 @@
#define BL31_END (unsigned long)(&__BL31_END__)
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
@@ -163,7 +153,7 @@ void bl31_plat_arch_setup(void)
BL_CODE_END,
BL_RO_DATA_BASE,
BL_RO_DATA_END,
- BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT);
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
enable_mmu_el3(0);
}
diff --git a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
index cf9ec6ace..6feb5b9d1 100644
--- a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
+++ b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
@@ -37,16 +37,6 @@
#define BL32_END (unsigned long)(&__BL32_END__)
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
/*******************************************************************************
* Initialize the UART
******************************************************************************/
@@ -84,8 +74,8 @@ void tsp_plat_arch_setup(void)
BL_CODE_END,
BL_RO_DATA_BASE,
BL_RO_DATA_END,
- BL32_COHERENT_RAM_BASE,
- BL32_COHERENT_RAM_LIMIT
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END
);
enable_mmu_el1(0);
}
--
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