diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h index 452afbcc8464d4d736a1a00a8bd78a3305f95bcb..f982b57b48bcf816309f339361612c2bb8b748ba 100644 --- a/include/plat/arm/board/common/board_css_def.h +++ b/include/plat/arm/board/common/board_css_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -54,7 +54,7 @@ * Required platform porting definitions common to all ARM CSS-based * development platforms */ - +#define PLAT_ARM_DRAM2_BASE ULL(0x880000000) #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) /* UART related constants */ diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 62623c1bf0340967b172c6099acd4a763f1dba72..69a9959ad6e057355d0e29348f2079b7d69b6670 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -148,7 +148,7 @@ #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ ARM_DRAM1_SIZE - 1) -#define ARM_DRAM2_BASE UL(0x880000000) +#define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ ARM_DRAM2_SIZE - 1) diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index 2038f318be586ec3ce1527308ff2ebb99dec7ce6..a0babb0ef6af3b9c4bb0347411a110bfa4e9c1a5 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -49,11 +49,31 @@ func check_errata_1043202 b cpu_rev_var_ls endfunc check_errata_1043202 +/* -------------------------------------------------- + * Disable speculative loads if Neoverse N1 supports + * SSBS. + * + * Shall clobber: x0. + * -------------------------------------------------- + */ +func neoverse_n1_disable_speculative_loads + /* Check if the PE implements SSBS */ + mrs x0, id_aa64pfr1_el1 + tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) + b.eq 1f + + /* Disable speculative loads */ + msr SSBS, xzr + isb + +1: + ret +endfunc neoverse_n1_disable_speculative_loads + func neoverse_n1_reset_func mov x19, x30 - /* Disables speculative loads */ - msr SSBS, xzr + bl neoverse_n1_disable_speculative_loads /* Forces all cacheable atomic instructions to be near */ mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 6856a286ff914c521febb542e172167eef005bf7..2313ab0c265dba3e14e4134a6593e41134684244 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -48,6 +48,7 @@ /* No SCP in FVP */ #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) +#define PLAT_ARM_DRAM2_BASE ULL(0x880000000) #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) /* diff --git a/plat/arm/board/fvp_ve/include/platform_def.h b/plat/arm/board/fvp_ve/include/platform_def.h index 1870442f00cc70f6376247d72c3850e93b45445e..1b21c79d12dec8b338d847232fa50e73223536d3 100644 --- a/plat/arm/board/fvp_ve/include/platform_def.h +++ b/plat/arm/board/fvp_ve/include/platform_def.h @@ -25,7 +25,7 @@ #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ ARM_DRAM1_SIZE - 1) -#define ARM_DRAM2_BASE UL(0x880000000) +#define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ ARM_DRAM2_SIZE - 1) @@ -230,6 +230,7 @@ #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ +#define PLAT_ARM_DRAM2_BASE ULL(0x880000000) #define PLAT_ARM_DRAM2_SIZE ULL(0x80000000) /* diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h index adb957e5dd548b851d3aa09549deebd2e85e5085..0964f56889dfe6832e312b79ea400abe160bb040 100644 --- a/plat/arm/board/n1sdp/include/platform_def.h +++ b/plat/arm/board/n1sdp/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,6 +24,7 @@ #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ +#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) #if CSS_USE_SCMI_SDS_DRIVER diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index 0442945b8a1e191383eb25217f698cdb98ea5494..f5ce4d2417657e5521d9f6e409a775054bf0f048 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -127,12 +127,12 @@ void arm_configure_sys_timer(void) */ mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val); -#ifdef PLAT_juno +#if defined(PLAT_juno) || defined(PLAT_n1sdp) /* * Initialize CNTFRQ register in Non-secure CNTBase frame. - * This is only required for Juno, because it doesn't follow ARM ARM - * in that the value updated in CNTFRQ is not reflected in - * CNTBASEN_CNTFRQ. Hence update the value manually. + * This is only required for Juno and N1SDP, because they do not + * follow ARM ARM in that the value updated in CNTFRQ is not + * reflected in CNTBASEN_CNTFRQ. Hence update the value manually. */ mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val); #endif