Tegra194: enable driver for general purpose DMA engine

This patch enables the GPCDMA for all Tegra194 platforms to help
accelerate all the memory copy operations.

Change-Id: I8cbec99be6ebe4da74221245668b321ba9693479
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

plat/nvidia/tegra/include/t194/tegra_def.h

@@ -53,6 +53,11 @@
 #define  BOARD_SHIFT_BITS		U(24)
 #define MISCREG_PFCFG			U(0x200C)
 
+/*******************************************************************************
+ * Tegra General Purpose Centralised DMA constants
+ ******************************************************************************/
+#define TEGRA_GPCDMA_BASE		U(0x02610000)
+
 /*******************************************************************************
  * Tegra Memory Controller constants
  ******************************************************************************/
@@ -248,6 +253,8 @@
 #define TEGRA_GPU_RESET_GPU_SET_OFFSET  U(0x1C)
 #define  GPU_RESET_BIT			(U(1) << 0)
 #define  GPU_SET_BIT			(U(1) << 0)
+#define TEGRA_GPCDMA_RST_SET_REG_OFFSET	U(0x6A0004)
+#define TEGRA_GPCDMA_RST_CLR_REG_OFFSET	U(0x6A0008)
 
 /*******************************************************************************
  * XUSB STREAMIDs

plat/nvidia/tegra/soc/t194/plat_setup.c

@@ -68,6 +68,8 @@ static const mmap_region_t tegra_mmap[] = {
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
 	MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_GPCDMA_BASE, 0x10000U, /* 64KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
 	MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */
 			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
 	MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */

plat/nvidia/tegra/soc/t194/platform_t194.mk

@@ -11,6 +11,9 @@ $(eval $(call add_define,ENABLE_CONSOLE_SPE))
 ENABLE_STRICT_CHECKING_MODE		:= 1
 $(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE))
 
+USE_GPC_DMA				:= 1
+$(eval $(call add_define,USE_GPC_DMA))
+
 RESET_TO_BL31				:= 1
 
 PROGRAMMABLE_RESET_ADDRESS		:= 1
@@ -40,6 +43,7 @@ BL31_SOURCES		+=	drivers/ti/uart/aarch64/16550_console.S \
 				lib/cpus/aarch64/denver.S		\
 				${COMMON_DIR}/drivers/bpmp_ipc/intf.c	\
 				${COMMON_DIR}/drivers/bpmp_ipc/ivc.c	\
+				${COMMON_DIR}/drivers/gpcdma/gpcdma.c	\
 				${COMMON_DIR}/drivers/memctrl/memctrl_v2.c	\
 				${COMMON_DIR}/drivers/smmu/smmu.c	\
 				${SOC_DIR}/drivers/mce/mce.c		\