From 4acd900df6275cd724266157e04e2b75d82cf24a Mon Sep 17 00:00:00 2001
From: Marcin Wojtas <mw@semihalf.com>
Date: Wed, 21 Mar 2018 09:55:47 +0100
Subject: [PATCH] gicv2: enable configuring IRQ trigger type
This patch introduces new helper routines that allow
configuring the individual IRQs to be edge/level-triggered
via GICD_ICFGR registers. This is helpful to modify
the default configuration of the non-secure GIC SPI's, which
are all set during initialization to be level-sensitive.
Change-Id: I23deb4a0381691a686a3cda52405aa1dfd5e56f2
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
---
drivers/arm/gic/v2/gicv2_main.c | 9 +++++++++
include/drivers/arm/gicv2.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c
index 7cf6c76e3..a355659d2 100644
--- a/drivers/arm/gic/v2/gicv2_main.c
+++ b/drivers/arm/gic/v2/gicv2_main.c
@@ -593,3 +593,12 @@ unsigned int gicv2_set_pmr(unsigned int mask)
return old_mask;
}
+
+/*******************************************************************************
+ * This function updates single interrupt configuration to be level/edge
+ * triggered
+ ******************************************************************************/
+void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg)
+{
+ gicd_set_icfgr(driver_data->gicd_base, id, cfg);
+}
diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h
index 925d1c25c..3472c37d7 100644
--- a/include/drivers/arm/gicv2.h
+++ b/include/drivers/arm/gicv2.h
@@ -191,6 +191,7 @@ void gicv2_set_spi_routing(unsigned int id, int proc_num);
void gicv2_set_interrupt_pending(unsigned int id);
void gicv2_clear_interrupt_pending(unsigned int id);
unsigned int gicv2_set_pmr(unsigned int mask);
+void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg);
#endif /* __ASSEMBLY__ */
#endif /* __GICV2_H__ */
--
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