diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index ba6d283eeb959c6ebdbba41f05884a08020b78da..60892b1c8d71de483beb51b7b1a16511cfb56b54 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -293,7 +293,7 @@ static void tegra_memctrl_set_overrides(void)
uint32_t i, val;
/* Get the settings from the platform */
- assert(plat_mc_settings);
+ assert(plat_mc_settings != NULL);
mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg;
num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs;
@@ -357,7 +357,7 @@ void tegra_memctrl_setup(void)
tegra_smmu_init();
#endif
/* Get the settings from the platform */
- assert(plat_mc_settings);
+ assert(plat_mc_settings != NULL);
mc_streamid_override_regs = plat_mc_settings->streamid_override_cfg;
num_streamid_override_regs = plat_mc_settings->num_streamid_override_cfgs;
mc_streamid_sec_cfgs = plat_mc_settings->streamid_security_cfg;
diff --git a/plat/nvidia/tegra/common/drivers/smmu/smmu.c b/plat/nvidia/tegra/common/drivers/smmu/smmu.c
index bff95d7ce2e7321aa6fe4b1d4111a69885c676ac..0bda5e6892653c82892f46aa55b1bce768474a42 100644
--- a/plat/nvidia/tegra/common/drivers/smmu/smmu.c
+++ b/plat/nvidia/tegra/common/drivers/smmu/smmu.c
@@ -94,7 +94,7 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
/* get SMMU context table */
smmu_ctx_regs = plat_get_smmu_ctx();
- assert(smmu_ctx_regs);
+ assert(smmu_ctx_regs != NULL);
/*
* smmu_ctx_regs[0].val contains the size of the context table minus
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index fd5c4619f718efa708761141e7750a1d3bd1b937..26256c2cbf79bca3d29b47775ce3f4f4e9bf9326 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -143,8 +143,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
* Copy BL3-3, BL3-2 entry point information.
* They are stored in Secure RAM, in BL2's address space.
*/
- assert(arg_from_bl2);
- assert(arg_from_bl2->bl33_ep_info);
+ assert(arg_from_bl2 != NULL);
+ assert(arg_from_bl2->bl33_ep_info != NULL);
bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
if (arg_from_bl2->bl32_ep_info != NULL) {
@@ -156,7 +156,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
/*
* Parse platform specific parameters - TZDRAM aperture base and size
*/
- assert(plat_params);
+ assert(plat_params != NULL);
plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
diff --git a/plat/nvidia/tegra/common/tegra_fiq_glue.c b/plat/nvidia/tegra/common/tegra_fiq_glue.c
index 9a43f76956b99962d048c271940456054cf27479..cab2e5ec583ead2c9f70a675d230e1f13ba25aa8 100644
--- a/plat/nvidia/tegra/common/tegra_fiq_glue.c
+++ b/plat/nvidia/tegra/common/tegra_fiq_glue.c
@@ -65,7 +65,7 @@ static uint64_t tegra_fiq_interrupt_handler(uint32_t id,
* Set the new ELR to continue execution in the NS world using the
* FIQ handler registered earlier.
*/
- assert(ns_fiq_handler_addr);
+ assert(ns_fiq_handler_addr != 0ULL);
write_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3), (ns_fiq_handler_addr));
/*
diff --git a/plat/nvidia/tegra/common/tegra_platform.c b/plat/nvidia/tegra/common/tegra_platform.c
index 72da12663ed2b7c849c38a42aed4fde3ddd42984..c1e42095935d7285c333c2891125ee1e8efe63d8 100644
--- a/plat/nvidia/tegra/common/tegra_platform.c
+++ b/plat/nvidia/tegra/common/tegra_platform.c
@@ -15,7 +15,7 @@
* Tegra platforms
******************************************************************************/
typedef enum tegra_platform {
- TEGRA_PLATFORM_SILICON = 0,
+ TEGRA_PLATFORM_SILICON = 0U,
TEGRA_PLATFORM_QT,
TEGRA_PLATFORM_FPGA,
TEGRA_PLATFORM_EMULATION,
@@ -83,7 +83,7 @@ bool tegra_chipid_is_t132(void)
{
uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK);
- return (chip_id == (uint32_t)TEGRA_CHIPID_TEGRA13);
+ return (chip_id == TEGRA_CHIPID_TEGRA13);
}
bool tegra_chipid_is_t186(void)
@@ -97,12 +97,12 @@ bool tegra_chipid_is_t210(void)
{
uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
- return (chip_id == (uint32_t)TEGRA_CHIPID_TEGRA21);
+ return (chip_id == TEGRA_CHIPID_TEGRA21);
}
bool tegra_chipid_is_t210_b01(void)
{
- return (tegra_chipid_is_t210() && (tegra_get_chipid_major() == 0x2UL));
+ return (tegra_chipid_is_t210() && (tegra_get_chipid_major() == 0x2U));
}
/*
diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c
index 626c23ed73a55e56006cd965fc5002a491e9915a..2805272712c0c8f642f7f5b076196a090b432864 100644
--- a/plat/nvidia/tegra/common/tegra_pm.c
+++ b/plat/nvidia/tegra/common/tegra_pm.c
@@ -106,7 +106,7 @@ plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
(void)lvl;
- assert(ncpu);
+ assert(ncpu != 0U);
do {
temp = *local_state;
@@ -335,7 +335,7 @@ __dead2 void tegra_system_reset(void)
int32_t tegra_validate_power_state(uint32_t power_state,
psci_power_state_t *req_state)
{
- assert(req_state);
+ assert(req_state != NULL);
return tegra_soc_validate_power_state(power_state, req_state);
}
diff --git a/plat/nvidia/tegra/common/tegra_sip_calls.c b/plat/nvidia/tegra/common/tegra_sip_calls.c
index e7acecea44d3276e4930028c37eb1ee16964c91e..00695a049aa964a7377f0e954fe67e93d8d84c70 100644
--- a/plat/nvidia/tegra/common/tegra_sip_calls.c
+++ b/plat/nvidia/tegra/common/tegra_sip_calls.c
@@ -69,7 +69,7 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
void *handle,
u_register_t flags)
{
- uint32_t regval;
+ uint32_t regval, local_x2_32 = (uint32_t)x2;
int32_t err;
/* Check if this is a SoC specific SiP */
@@ -84,14 +84,11 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
case TEGRA_SIP_NEW_VIDEOMEM_REGION:
- /* clean up the high bits */
- x2 = (uint32_t)x2;
-
/*
* Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
* or falls outside of the valid DRAM range
*/
- err = bl31_check_ns_address(x1, x2);
+ err = bl31_check_ns_address(x1, local_x2_32);
if (err != 0) {
SMC_RET1(handle, (uint64_t)err);
}
@@ -99,7 +96,7 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
/*
* Check if Video Memory is aligned to 1MB.
*/
- if (((x1 & 0xFFFFFU) != 0U) || ((x2 & 0xFFFFFU) != 0U)) {
+ if (((x1 & 0xFFFFFU) != 0U) || ((local_x2_32 & 0xFFFFFU) != 0U)) {
ERROR("Unaligned Video Memory base address!\n");
SMC_RET1(handle, -ENOTSUP);
}
@@ -117,7 +114,7 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
}
/* new video memory carveout settings */
- tegra_memctrl_videomem_setup(x1, (uint32_t)x2);
+ tegra_memctrl_videomem_setup(x1, local_x2_32);
SMC_RET1(handle, 0);