Tegra194: memctrl: platform handler for TZDRAM setup

This patch provides the platform with flexibility to perform custom
steps during TZDRAM setup. Tegra194 platforms checks if the config
registers are locked and TZDRAM setup has already been done by the
previous bootloaders, before setting up the fence.

Change-Id: Ifee7077d4b46a7031c4568934c63e361c53a12e3
Signed-off-by: Steven Kao <skao@nvidia.com>

plat/nvidia/tegra/include/t194/tegra_def.h

@@ -73,6 +73,9 @@
 #define MC_SECURITY_SIZE_MB_MASK	(U(0x1FFF) << 0)
 #define MC_SECURITY_BOM_HI_MASK		(U(0x3) << 0)
 
+#define MC_SECURITY_CFG_REG_CTRL_0	U(0x154)
+#define  SECURITY_CFG_WRITE_ACCESS_BIT	(U(0x1) << 0)
+
 /* Video Memory carveout configuration registers */
 #define MC_VIDEO_PROTECT_BASE_HI	U(0x978)
 #define MC_VIDEO_PROTECT_BASE_LO	U(0x648)

plat/nvidia/tegra/soc/t194/plat_memctrl.c

@@ -639,3 +639,34 @@ tegra_mc_settings_t *tegra_get_mc_settings(void)
 {
 	return &tegra194_mc_settings;
 }
+
+/*******************************************************************************
+ * Handler to program the scratch registers with TZDRAM settings for the
+ * resume firmware
+ ******************************************************************************/
+void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
+{
+	/*
+	 * Check if the carveout register is already locked, if locked
+	 * no TZDRAM setup
+	 */
+	if ((tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0) &
+		SECURITY_CFG_WRITE_ACCESS_BIT) == SECURITY_CFG_WRITE_ACCESS_BIT) {
+
+		/*
+		 * Setup the Memory controller to allow only secure accesses to
+		 * the TZDRAM carveout
+		 */
+		INFO("Configuring TrustZone DRAM Memory Carveout\n");
+
+		tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base);
+		tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32));
+		tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20));
+
+		/*
+		 * MCE propagates the security configuration values across the
+		 * CCPLEX.
+		 */
+		(void)mce_update_gsc_tzdram();
+	}
+}