diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c
index 067a6751c087192d723e88df1bccd7e63dc02d59..c15528e84a3c1c003d906fce765959b520cb58ba 100644
--- a/plat/rockchip/rk3399/drivers/dram/dfs.c
+++ b/plat/rockchip/rk3399/drivers/dram/dfs.c
@@ -1575,7 +1575,6 @@ static void gen_rk3399_phy_params(struct timing_related_config *timing_config,
 				break;
 		}
 		mmio_clrsetbits_32(PHY_REG(i, 947), 0x7 << 8, tmp << 8);
-		mmio_setbits_32(PHY_REG(i, 927), (1 << 22));
 
 		if (timing_config->dram_type == DDR3) {
 			mem_delay_ps = 0;
diff --git a/plat/rockchip/rk3399/drivers/m0/src/dram.c b/plat/rockchip/rk3399/drivers/m0/src/dram.c
index be6495b7f4a34a6b72770d1c5fc83ee9ecf1a90d..bd46843b2ef675f70e5fa131ad6a925237fc37f9 100644
--- a/plat/rockchip/rk3399/drivers/m0/src/dram.c
+++ b/plat/rockchip/rk3399/drivers/m0/src/dram.c
@@ -81,6 +81,8 @@ static void ddr_set_pll(void)
 
 void handle_dram(void)
 {
+	mmio_setbits_32(PHY_REG(0, 927), (1 << 22));
+	mmio_setbits_32(PHY_REG(1, 927), (1 << 22));
 	idle_port();
 
 	mmio_write_32(CIC_BASE + CIC_CTRL0,
@@ -96,4 +98,6 @@ void handle_dram(void)
 		continue;
 
 	deidle_port();
+	mmio_clrbits_32(PHY_REG(0, 927), (1 << 22));
+	mmio_clrbits_32(PHY_REG(1, 927), (1 << 22));
 }