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Commit 50e91633 authored by Anthony Zhou's avatar Anthony Zhou Committed by Varun Wadekar
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Tegra: fix trivial misra issues 



Not having U or ULL as a suffix for these enums causes
a lot of unnecessary MISRA issues. This patch adds U or
ULL suffix to these common enums to reduce number of
MISRA issues.
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
parent e87dac6b
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plat/nvidia/tegra/include/drivers/flowctrl.h
View file @ 50e91633
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -34,34 +34,34 @@
#include <mmio.h>
#include <tegra_def.h>
#define FLOWCTRL_HALT_CPU0_EVENTS 0x0
#define FLOWCTRL_WAITEVENT (2 << 29)
#define FLOWCTRL_WAIT_FOR_INTERRUPT (4 << 29)
#define FLOWCTRL_JTAG_RESUME (1 << 28)
#define FLOWCTRL_HALT_SCLK (1 << 27)
#define FLOWCTRL_HALT_LIC_IRQ (1 << 11)
#define FLOWCTRL_HALT_LIC_FIQ (1 << 10)
#define FLOWCTRL_HALT_GIC_IRQ (1 << 9)
#define FLOWCTRL_HALT_GIC_FIQ (1 << 8)
#define FLOWCTRL_HALT_BPMP_EVENTS 0x4
#define FLOWCTRL_CPU0_CSR 0x8
#define FLOW_CTRL_CSR_PWR_OFF_STS (1 << 16)
#define FLOWCTRL_CSR_INTR_FLAG (1 << 15)
#define FLOWCTRL_CSR_EVENT_FLAG (1 << 14)
#define FLOWCTRL_CSR_IMMEDIATE_WAKE (1 << 3)
#define FLOWCTRL_CSR_ENABLE (1 << 0)
#define FLOWCTRL_HALT_CPU1_EVENTS 0x14
#define FLOWCTRL_CPU1_CSR 0x18
#define FLOWCTRL_CC4_CORE0_CTRL 0x6c
#define FLOWCTRL_WAIT_WFI_BITMAP 0x100
#define FLOWCTRL_L2_FLUSH_CONTROL 0x94
#define FLOWCTRL_BPMP_CLUSTER_CONTROL 0x98
#define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1 << 2)
#define FLOWCTRL_HALT_CPU0_EVENTS 0x0U
#define FLOWCTRL_WAITEVENT (2U << 29)
#define FLOWCTRL_WAIT_FOR_INTERRUPT (4U << 29)
#define FLOWCTRL_JTAG_RESUME (1U << 28)
#define FLOWCTRL_HALT_SCLK (1U << 27)
#define FLOWCTRL_HALT_LIC_IRQ (1U << 11)
#define FLOWCTRL_HALT_LIC_FIQ (1U << 10)
#define FLOWCTRL_HALT_GIC_IRQ (1U << 9)
#define FLOWCTRL_HALT_GIC_FIQ (1U << 8)
#define FLOWCTRL_HALT_BPMP_EVENTS 0x4U
#define FLOWCTRL_CPU0_CSR 0x8U
#define FLOW_CTRL_CSR_PWR_OFF_STS (1U << 16)
#define FLOWCTRL_CSR_INTR_FLAG (1U << 15)
#define FLOWCTRL_CSR_EVENT_FLAG (1U << 14)
#define FLOWCTRL_CSR_IMMEDIATE_WAKE (1U << 3)
#define FLOWCTRL_CSR_ENABLE (1U << 0)
#define FLOWCTRL_HALT_CPU1_EVENTS 0x14U
#define FLOWCTRL_CPU1_CSR 0x18U
#define FLOWCTRL_CC4_CORE0_CTRL 0x6cU
#define FLOWCTRL_WAIT_WFI_BITMAP 0x100U
#define FLOWCTRL_L2_FLUSH_CONTROL 0x94U
#define FLOWCTRL_BPMP_CLUSTER_CONTROL 0x98U
#define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1U << 2)
#define FLOWCTRL_ENABLE_EXT 12
#define FLOWCTRL_ENABLE_EXT_MASK 3
#define FLOWCTRL_PG_CPU_NONCPU 0x1
#define FLOWCTRL_TURNOFF_CPURAIL 0x2
#define FLOWCTRL_ENABLE_EXT 12U
#define FLOWCTRL_ENABLE_EXT_MASK 3U
#define FLOWCTRL_PG_CPU_NONCPU 0x1U
#define FLOWCTRL_TURNOFF_CPURAIL 0x2U
static inline uint32_t tegra_fc_read_32(uint32_t off)
{
......
plat/nvidia/tegra/include/drivers/mce.h
View file @ 50e91633
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -38,35 +38,35 @@
* MCE commands
******************************************************************************/
typedef enum mce_cmd {
MCE_CMD_ENTER_CSTATE = 0,
MCE_CMD_UPDATE_CSTATE_INFO = 1,
MCE_CMD_UPDATE_CROSSOVER_TIME = 2,
MCE_CMD_READ_CSTATE_STATS = 3,
MCE_CMD_WRITE_CSTATE_STATS = 4,
MCE_CMD_IS_SC7_ALLOWED = 5,
MCE_CMD_ONLINE_CORE = 6,
MCE_CMD_CC3_CTRL = 7,
MCE_CMD_ECHO_DATA = 8,
MCE_CMD_READ_VERSIONS = 9,
MCE_CMD_ENUM_FEATURES = 10,
MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11,
MCE_CMD_ENUM_READ_MCA = 12,
MCE_CMD_ENUM_WRITE_MCA = 13,
MCE_CMD_ROC_FLUSH_CACHE = 14,
MCE_CMD_ROC_CLEAN_CACHE = 15,
MCE_CMD_ENABLE_LATIC = 16,
MCE_CMD_UNCORE_PERFMON_REQ = 17,
MCE_CMD_MISC_CCPLEX = 18,
MCE_CMD_IS_CCX_ALLOWED = 0xFE,
MCE_CMD_MAX = 0xFF,
MCE_CMD_ENTER_CSTATE = 0U,
MCE_CMD_UPDATE_CSTATE_INFO = 1U,
MCE_CMD_UPDATE_CROSSOVER_TIME = 2U,
MCE_CMD_READ_CSTATE_STATS = 3U,
MCE_CMD_WRITE_CSTATE_STATS = 4U,
MCE_CMD_IS_SC7_ALLOWED = 5U,
MCE_CMD_ONLINE_CORE = 6U,
MCE_CMD_CC3_CTRL = 7U,
MCE_CMD_ECHO_DATA = 8U,
MCE_CMD_READ_VERSIONS = 9U,
MCE_CMD_ENUM_FEATURES = 10U,
MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11U,
MCE_CMD_ENUM_READ_MCA = 12U,
MCE_CMD_ENUM_WRITE_MCA = 13U,
MCE_CMD_ROC_FLUSH_CACHE = 14U,
MCE_CMD_ROC_CLEAN_CACHE = 15U,
MCE_CMD_ENABLE_LATIC = 16U,
MCE_CMD_UNCORE_PERFMON_REQ = 17U,
MCE_CMD_MISC_CCPLEX = 18U,
MCE_CMD_IS_CCX_ALLOWED = 0xFEU,
MCE_CMD_MAX = 0xFFU,
} mce_cmd_t;
#define MCE_CMD_MASK 0xFF
#define MCE_CMD_MASK 0xFFU
/*******************************************************************************
* Timeout value used to powerdown a core
******************************************************************************/
#define MCE_CORE_SLEEP_TIME_INFINITE 0xFFFFFFFF
#define MCE_CORE_SLEEP_TIME_INFINITE 0xFFFFFFFFU
/*******************************************************************************
* Struct to prepare UPDATE_CSTATE_INFO request
......
plat/nvidia/tegra/include/drivers/memctrl_v1.h
View file @ 50e91633
/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -35,29 +35,29 @@
#include <tegra_def.h>
/* SMMU registers */
#define MC_SMMU_CONFIG_0 0x10
#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0
#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1
#define MC_SMMU_TLB_CONFIG_0 0x14
#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010
#define MC_SMMU_PTC_CONFIG_0 0x18
#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003f
#define MC_SMMU_TLB_FLUSH_0 0x30
#define TLB_FLUSH_VA_MATCH_ALL 0
#define TLB_FLUSH_ASID_MATCH_DISABLE 0
#define TLB_FLUSH_ASID_MATCH_SHIFT 31
#define MC_SMMU_CONFIG_0 0x10U
#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0U
#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1U
#define MC_SMMU_TLB_CONFIG_0 0x14U
#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010U
#define MC_SMMU_PTC_CONFIG_0 0x18U
#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003fU
#define MC_SMMU_TLB_FLUSH_0 0x30U
#define TLB_FLUSH_VA_MATCH_ALL 0U
#define TLB_FLUSH_ASID_MATCH_DISABLE 0U
#define TLB_FLUSH_ASID_MATCH_SHIFT 31U
#define MC_SMMU_TLB_FLUSH_ALL \
(TLB_FLUSH_VA_MATCH_ALL | \
(TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT))
#define MC_SMMU_PTC_FLUSH_0 0x34
#define MC_SMMU_PTC_FLUSH_ALL 0
#define MC_SMMU_ASID_SECURITY_0 0x38
#define MC_SMMU_ASID_SECURITY 0
#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228
#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22c
#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230
#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234
#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98
#define MC_SMMU_PTC_FLUSH_0 0x34U
#define MC_SMMU_PTC_FLUSH_ALL 0U
#define MC_SMMU_ASID_SECURITY_0 0x38U
#define MC_SMMU_ASID_SECURITY 0U
#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228U
#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22cU
#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230U
#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234U
#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98U
#define MC_SMMU_TRANSLATION_ENABLE (~0)
/* MC IRAM aperture registers */
......
plat/nvidia/tegra/include/drivers/pmc.h
View file @ 50e91633
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -34,19 +34,19 @@
#include <mmio.h>
#include <tegra_def.h>
#define PMC_CONFIG 0x0
#define PMC_PWRGATE_STATUS 0x38
#define PMC_PWRGATE_TOGGLE 0x30
#define PMC_TOGGLE_START 0x100
#define PMC_SCRATCH39 0x138
#define PMC_SECURE_DISABLE2 0x2c4
#define PMC_SECURE_DISABLE2_WRITE22_ON (1 << 28)
#define PMC_SECURE_SCRATCH22 0x338
#define PMC_SECURE_DISABLE3 0x2d8
#define PMC_SECURE_DISABLE3_WRITE34_ON (1 << 20)
#define PMC_SECURE_DISABLE3_WRITE35_ON (1 << 22)
#define PMC_SECURE_SCRATCH34 0x368
#define PMC_SECURE_SCRATCH35 0x36c
#define PMC_CONFIG 0x0U
#define PMC_PWRGATE_STATUS 0x38U
#define PMC_PWRGATE_TOGGLE 0x30U
#define PMC_TOGGLE_START 0x100U
#define PMC_SCRATCH39 0x138U
#define PMC_SECURE_DISABLE2 0x2c4U
#define PMC_SECURE_DISABLE2_WRITE22_ON (1U << 28)
#define PMC_SECURE_SCRATCH22 0x338U
#define PMC_SECURE_DISABLE3 0x2d8U
#define PMC_SECURE_DISABLE3_WRITE34_ON (1U << 20)
#define PMC_SECURE_DISABLE3_WRITE35_ON (1U << 22)
#define PMC_SECURE_SCRATCH34 0x368U
#define PMC_SECURE_SCRATCH35 0x36cU
static inline uint32_t tegra_pmc_read_32(uint32_t off)
{
......
plat/nvidia/tegra/include/drivers/smmu.h
View file @ 50e91633
......@@ -38,591 +38,591 @@
/*******************************************************************************
* SMMU Register constants
******************************************************************************/
#define SMMU_CBn_SCTLR (0x0)
#define SMMU_CBn_SCTLR_STAGE2 (0x0)
#define SMMU_CBn_ACTLR (0x4)
#define SMMU_CBn_RESUME (0x8)
#define SMMU_CBn_TCR2 (0x10)
#define SMMU_CBn_TTBR0_LO (0x20)
#define SMMU_CBn_TTBR0_HI (0x24)
#define SMMU_CBn_TTBR1_LO (0x28)
#define SMMU_CBn_TTBR1_HI (0x2c)
#define SMMU_CBn_TCR_LPAE (0x30)
#define SMMU_CBn_TCR (0x30)
#define SMMU_CBn_TCR_EAE_1 (0x30)
#define SMMU_CBn_TCR (0x30)
#define SMMU_CBn_CONTEXTIDR (0x34)
#define SMMU_CBn_CONTEXTIDR_EAE_1 (0x34)
#define SMMU_CBn_PRRR_MAIR0 (0x38)
#define SMMU_CBn_NMRR_MAIR1 (0x3c)
#define SMMU_CBn_SMMU_CBn_PAR (0x50)
#define SMMU_CBn_SMMU_CBn_PAR0 (0x50)
#define SMMU_CBn_SMMU_CBn_PAR1 (0x54)
/* SMMU_CBn_SMMU_CBn_PAR0_Fault (0x50) */
/* SMMU_CBn_SMMU_CBn_PAR0_Fault (0x54) */
#define SMMU_CBn_FSR (0x58)
#define SMMU_CBn_FSRRESTORE (0x5c)
#define SMMU_CBn_FAR_LO (0x60)
#define SMMU_CBn_FAR_HI (0x64)
#define SMMU_CBn_FSYNR0 (0x68)
#define SMMU_CBn_IPAFAR_LO (0x70)
#define SMMU_CBn_IPAFAR_HI (0x74)
#define SMMU_CBn_TLBIVA_LO (0x600)
#define SMMU_CBn_TLBIVA_HI (0x604)
#define SMMU_CBn_TLBIVA_AARCH_32 (0x600)
#define SMMU_CBn_TLBIVAA_LO (0x608)
#define SMMU_CBn_TLBIVAA_HI (0x60c)
#define SMMU_CBn_TLBIVAA_AARCH_32 (0x608)
#define SMMU_CBn_TLBIASID (0x610)
#define SMMU_CBn_TLBIALL (0x618)
#define SMMU_CBn_TLBIVAL_LO (0x620)
#define SMMU_CBn_TLBIVAL_HI (0x624)
#define SMMU_CBn_TLBIVAL_AARCH_32 (0x618)
#define SMMU_CBn_TLBIVAAL_LO (0x628)
#define SMMU_CBn_TLBIVAAL_HI (0x62c)
#define SMMU_CBn_TLBIVAAL_AARCH_32 (0x628)
#define SMMU_CBn_TLBIIPAS2_LO (0x630)
#define SMMU_CBn_TLBIIPAS2_HI (0x634)
#define SMMU_CBn_TLBIIPAS2L_LO (0x638)
#define SMMU_CBn_TLBIIPAS2L_HI (0x63c)
#define SMMU_CBn_TLBSYNC (0x7f0)
#define SMMU_CBn_TLBSTATUS (0x7f4)
#define SMMU_CBn_ATSR (0x800)
#define SMMU_CBn_PMEVCNTR0 (0xe00)
#define SMMU_CBn_PMEVCNTR1 (0xe04)
#define SMMU_CBn_PMEVCNTR2 (0xe08)
#define SMMU_CBn_PMEVCNTR3 (0xe0c)
#define SMMU_CBn_PMEVTYPER0 (0xe80)
#define SMMU_CBn_PMEVTYPER1 (0xe84)
#define SMMU_CBn_PMEVTYPER2 (0xe88)
#define SMMU_CBn_PMEVTYPER3 (0xe8c)
#define SMMU_CBn_PMCFGR (0xf00)
#define SMMU_CBn_PMCR (0xf04)
#define SMMU_CBn_PMCEID (0xf20)
#define SMMU_CBn_PMCNTENSE (0xf40)
#define SMMU_CBn_PMCNTENCLR (0xf44)
#define SMMU_CBn_PMCNTENSET (0xf48)
#define SMMU_CBn_PMINTENCLR (0xf4c)
#define SMMU_CBn_PMOVSCLR (0xf50)
#define SMMU_CBn_PMOVSSET (0xf58)
#define SMMU_CBn_PMAUTHSTATUS (0xfb8)
#define SMMU_GNSR0_CR0 (0x0)
#define SMMU_GNSR0_CR2 (0x8)
#define SMMU_GNSR0_ACR (0x10)
#define SMMU_GNSR0_IDR0 (0x20)
#define SMMU_GNSR0_IDR1 (0x24)
#define SMMU_GNSR0_IDR2 (0x28)
#define SMMU_GNSR0_IDR7 (0x3c)
#define SMMU_GNSR0_GFAR_LO (0x40)
#define SMMU_GNSR0_GFAR_HI (0x44)
#define SMMU_GNSR0_GFSR (0x48)
#define SMMU_GNSR0_GFSRRESTORE (0x4c)
#define SMMU_GNSR0_GFSYNR0 (0x50)
#define SMMU_GNSR0_GFSYNR1 (0x54)
#define SMMU_GNSR0_GFSYNR1_v2 (0x54)
#define SMMU_GNSR0_TLBIVMID (0x64)
#define SMMU_GNSR0_TLBIALLNSNH (0x68)
#define SMMU_GNSR0_TLBIALLH (0x6c)
#define SMMU_GNSR0_TLBGSYNC (0x70)
#define SMMU_GNSR0_TLBGSTATUS (0x74)
#define SMMU_GNSR0_TLBIVAH_LO (0x78)
#define SMMU_GNSR0_TLBIVALH64_LO (0xb0)
#define SMMU_GNSR0_TLBIVALH64_HI (0xb4)
#define SMMU_GNSR0_TLBIVMIDS1 (0xb8)
#define SMMU_GNSR0_TLBIVAH64_LO (0xc0)
#define SMMU_GNSR0_TLBIVAH64_HI (0xc4)
#define SMMU_GNSR0_SMR0 (0x800)
#define SMMU_GNSR0_SMRn (0x800)
#define SMMU_GNSR0_SMR1 (0x804)
#define SMMU_GNSR0_SMR2 (0x808)
#define SMMU_GNSR0_SMR3 (0x80c)
#define SMMU_GNSR0_SMR4 (0x810)
#define SMMU_GNSR0_SMR5 (0x814)
#define SMMU_GNSR0_SMR6 (0x818)
#define SMMU_GNSR0_SMR7 (0x81c)
#define SMMU_GNSR0_SMR8 (0x820)
#define SMMU_GNSR0_SMR9 (0x824)
#define SMMU_GNSR0_SMR10 (0x828)
#define SMMU_GNSR0_SMR11 (0x82c)
#define SMMU_GNSR0_SMR12 (0x830)
#define SMMU_GNSR0_SMR13 (0x834)
#define SMMU_GNSR0_SMR14 (0x838)
#define SMMU_GNSR0_SMR15 (0x83c)
#define SMMU_GNSR0_SMR16 (0x840)
#define SMMU_GNSR0_SMR17 (0x844)
#define SMMU_GNSR0_SMR18 (0x848)
#define SMMU_GNSR0_SMR19 (0x84c)
#define SMMU_GNSR0_SMR20 (0x850)
#define SMMU_GNSR0_SMR21 (0x854)
#define SMMU_GNSR0_SMR22 (0x858)
#define SMMU_GNSR0_SMR23 (0x85c)
#define SMMU_GNSR0_SMR24 (0x860)
#define SMMU_GNSR0_SMR25 (0x864)
#define SMMU_GNSR0_SMR26 (0x868)
#define SMMU_GNSR0_SMR27 (0x86c)
#define SMMU_GNSR0_SMR28 (0x870)
#define SMMU_GNSR0_SMR29 (0x874)
#define SMMU_GNSR0_SMR30 (0x878)
#define SMMU_GNSR0_SMR31 (0x87c)
#define SMMU_GNSR0_SMR32 (0x880)
#define SMMU_GNSR0_SMR33 (0x884)
#define SMMU_GNSR0_SMR34 (0x888)
#define SMMU_GNSR0_SMR35 (0x88c)
#define SMMU_GNSR0_SMR36 (0x890)
#define SMMU_GNSR0_SMR37 (0x894)
#define SMMU_GNSR0_SMR38 (0x898)
#define SMMU_GNSR0_SMR39 (0x89c)
#define SMMU_GNSR0_SMR40 (0x8a0)
#define SMMU_GNSR0_SMR41 (0x8a4)
#define SMMU_GNSR0_SMR42 (0x8a8)
#define SMMU_GNSR0_SMR43 (0x8ac)
#define SMMU_GNSR0_SMR44 (0x8b0)
#define SMMU_GNSR0_SMR45 (0x8b4)
#define SMMU_GNSR0_SMR46 (0x8b8)
#define SMMU_GNSR0_SMR47 (0x8bc)
#define SMMU_GNSR0_SMR48 (0x8c0)
#define SMMU_GNSR0_SMR49 (0x8c4)
#define SMMU_GNSR0_SMR50 (0x8c8)
#define SMMU_GNSR0_SMR51 (0x8cc)
#define SMMU_GNSR0_SMR52 (0x8d0)
#define SMMU_GNSR0_SMR53 (0x8d4)
#define SMMU_GNSR0_SMR54 (0x8d8)
#define SMMU_GNSR0_SMR55 (0x8dc)
#define SMMU_GNSR0_SMR56 (0x8e0)
#define SMMU_GNSR0_SMR57 (0x8e4)
#define SMMU_GNSR0_SMR58 (0x8e8)
#define SMMU_GNSR0_SMR59 (0x8ec)
#define SMMU_GNSR0_SMR60 (0x8f0)
#define SMMU_GNSR0_SMR61 (0x8f4)
#define SMMU_GNSR0_SMR62 (0x8f8)
#define SMMU_GNSR0_SMR63 (0x8fc)
#define SMMU_GNSR0_SMR64 (0x900)
#define SMMU_GNSR0_SMR65 (0x904)
#define SMMU_GNSR0_SMR66 (0x908)
#define SMMU_GNSR0_SMR67 (0x90c)
#define SMMU_GNSR0_SMR68 (0x910)
#define SMMU_GNSR0_SMR69 (0x914)
#define SMMU_GNSR0_SMR70 (0x918)
#define SMMU_GNSR0_SMR71 (0x91c)
#define SMMU_GNSR0_SMR72 (0x920)
#define SMMU_GNSR0_SMR73 (0x924)
#define SMMU_GNSR0_SMR74 (0x928)
#define SMMU_GNSR0_SMR75 (0x92c)
#define SMMU_GNSR0_SMR76 (0x930)
#define SMMU_GNSR0_SMR77 (0x934)
#define SMMU_GNSR0_SMR78 (0x938)
#define SMMU_GNSR0_SMR79 (0x93c)
#define SMMU_GNSR0_SMR80 (0x940)
#define SMMU_GNSR0_SMR81 (0x944)
#define SMMU_GNSR0_SMR82 (0x948)
#define SMMU_GNSR0_SMR83 (0x94c)
#define SMMU_GNSR0_SMR84 (0x950)
#define SMMU_GNSR0_SMR85 (0x954)
#define SMMU_GNSR0_SMR86 (0x958)
#define SMMU_GNSR0_SMR87 (0x95c)
#define SMMU_GNSR0_SMR88 (0x960)
#define SMMU_GNSR0_SMR89 (0x964)
#define SMMU_GNSR0_SMR90 (0x968)
#define SMMU_GNSR0_SMR91 (0x96c)
#define SMMU_GNSR0_SMR92 (0x970)
#define SMMU_GNSR0_SMR93 (0x974)
#define SMMU_GNSR0_SMR94 (0x978)
#define SMMU_GNSR0_SMR95 (0x97c)
#define SMMU_GNSR0_SMR96 (0x980)
#define SMMU_GNSR0_SMR97 (0x984)
#define SMMU_GNSR0_SMR98 (0x988)
#define SMMU_GNSR0_SMR99 (0x98c)
#define SMMU_GNSR0_SMR100 (0x990)
#define SMMU_GNSR0_SMR101 (0x994)
#define SMMU_GNSR0_SMR102 (0x998)
#define SMMU_GNSR0_SMR103 (0x99c)
#define SMMU_GNSR0_SMR104 (0x9a0)
#define SMMU_GNSR0_SMR105 (0x9a4)
#define SMMU_GNSR0_SMR106 (0x9a8)
#define SMMU_GNSR0_SMR107 (0x9ac)
#define SMMU_GNSR0_SMR108 (0x9b0)
#define SMMU_GNSR0_SMR109 (0x9b4)
#define SMMU_GNSR0_SMR110 (0x9b8)
#define SMMU_GNSR0_SMR111 (0x9bc)
#define SMMU_GNSR0_SMR112 (0x9c0)
#define SMMU_GNSR0_SMR113 (0x9c4)
#define SMMU_GNSR0_SMR114 (0x9c8)
#define SMMU_GNSR0_SMR115 (0x9cc)
#define SMMU_GNSR0_SMR116 (0x9d0)
#define SMMU_GNSR0_SMR117 (0x9d4)
#define SMMU_GNSR0_SMR118 (0x9d8)
#define SMMU_GNSR0_SMR119 (0x9dc)
#define SMMU_GNSR0_SMR120 (0x9e0)
#define SMMU_GNSR0_SMR121 (0x9e4)
#define SMMU_GNSR0_SMR122 (0x9e8)
#define SMMU_GNSR0_SMR123 (0x9ec)
#define SMMU_GNSR0_SMR124 (0x9f0)
#define SMMU_GNSR0_SMR125 (0x9f4)
#define SMMU_GNSR0_SMR126 (0x9f8)
#define SMMU_GNSR0_SMR127 (0x9fc)
#define SMMU_GNSR0_S2CR0 (0xc00)
#define SMMU_GNSR0_S2CRn (0xc00)
#define SMMU_GNSR0_S2CRn (0xc00)
#define SMMU_GNSR0_S2CR1 (0xc04)
#define SMMU_GNSR0_S2CR2 (0xc08)
#define SMMU_GNSR0_S2CR3 (0xc0c)
#define SMMU_GNSR0_S2CR4 (0xc10)
#define SMMU_GNSR0_S2CR5 (0xc14)
#define SMMU_GNSR0_S2CR6 (0xc18)
#define SMMU_GNSR0_S2CR7 (0xc1c)
#define SMMU_GNSR0_S2CR8 (0xc20)
#define SMMU_GNSR0_S2CR9 (0xc24)
#define SMMU_GNSR0_S2CR10 (0xc28)
#define SMMU_GNSR0_S2CR11 (0xc2c)
#define SMMU_GNSR0_S2CR12 (0xc30)
#define SMMU_GNSR0_S2CR13 (0xc34)
#define SMMU_GNSR0_S2CR14 (0xc38)
#define SMMU_GNSR0_S2CR15 (0xc3c)
#define SMMU_GNSR0_S2CR16 (0xc40)
#define SMMU_GNSR0_S2CR17 (0xc44)
#define SMMU_GNSR0_S2CR18 (0xc48)
#define SMMU_GNSR0_S2CR19 (0xc4c)
#define SMMU_GNSR0_S2CR20 (0xc50)
#define SMMU_GNSR0_S2CR21 (0xc54)
#define SMMU_GNSR0_S2CR22 (0xc58)
#define SMMU_GNSR0_S2CR23 (0xc5c)
#define SMMU_GNSR0_S2CR24 (0xc60)
#define SMMU_GNSR0_S2CR25 (0xc64)
#define SMMU_GNSR0_S2CR26 (0xc68)
#define SMMU_GNSR0_S2CR27 (0xc6c)
#define SMMU_GNSR0_S2CR28 (0xc70)
#define SMMU_GNSR0_S2CR29 (0xc74)
#define SMMU_GNSR0_S2CR30 (0xc78)
#define SMMU_GNSR0_S2CR31 (0xc7c)
#define SMMU_GNSR0_S2CR32 (0xc80)
#define SMMU_GNSR0_S2CR33 (0xc84)
#define SMMU_GNSR0_S2CR34 (0xc88)
#define SMMU_GNSR0_S2CR35 (0xc8c)
#define SMMU_GNSR0_S2CR36 (0xc90)
#define SMMU_GNSR0_S2CR37 (0xc94)
#define SMMU_GNSR0_S2CR38 (0xc98)
#define SMMU_GNSR0_S2CR39 (0xc9c)
#define SMMU_GNSR0_S2CR40 (0xca0)
#define SMMU_GNSR0_S2CR41 (0xca4)
#define SMMU_GNSR0_S2CR42 (0xca8)
#define SMMU_GNSR0_S2CR43 (0xcac)
#define SMMU_GNSR0_S2CR44 (0xcb0)
#define SMMU_GNSR0_S2CR45 (0xcb4)
#define SMMU_GNSR0_S2CR46 (0xcb8)
#define SMMU_GNSR0_S2CR47 (0xcbc)
#define SMMU_GNSR0_S2CR48 (0xcc0)
#define SMMU_GNSR0_S2CR49 (0xcc4)
#define SMMU_GNSR0_S2CR50 (0xcc8)
#define SMMU_GNSR0_S2CR51 (0xccc)
#define SMMU_GNSR0_S2CR52 (0xcd0)
#define SMMU_GNSR0_S2CR53 (0xcd4)
#define SMMU_GNSR0_S2CR54 (0xcd8)
#define SMMU_GNSR0_S2CR55 (0xcdc)
#define SMMU_GNSR0_S2CR56 (0xce0)
#define SMMU_GNSR0_S2CR57 (0xce4)
#define SMMU_GNSR0_S2CR58 (0xce8)
#define SMMU_GNSR0_S2CR59 (0xcec)
#define SMMU_GNSR0_S2CR60 (0xcf0)
#define SMMU_GNSR0_S2CR61 (0xcf4)
#define SMMU_GNSR0_S2CR62 (0xcf8)
#define SMMU_GNSR0_S2CR63 (0xcfc)
#define SMMU_GNSR0_S2CR64 (0xd00)
#define SMMU_GNSR0_S2CR65 (0xd04)
#define SMMU_GNSR0_S2CR66 (0xd08)
#define SMMU_GNSR0_S2CR67 (0xd0c)
#define SMMU_GNSR0_S2CR68 (0xd10)
#define SMMU_GNSR0_S2CR69 (0xd14)
#define SMMU_GNSR0_S2CR70 (0xd18)
#define SMMU_GNSR0_S2CR71 (0xd1c)
#define SMMU_GNSR0_S2CR72 (0xd20)
#define SMMU_GNSR0_S2CR73 (0xd24)
#define SMMU_GNSR0_S2CR74 (0xd28)
#define SMMU_GNSR0_S2CR75 (0xd2c)
#define SMMU_GNSR0_S2CR76 (0xd30)
#define SMMU_GNSR0_S2CR77 (0xd34)
#define SMMU_GNSR0_S2CR78 (0xd38)
#define SMMU_GNSR0_S2CR79 (0xd3c)
#define SMMU_GNSR0_S2CR80 (0xd40)
#define SMMU_GNSR0_S2CR81 (0xd44)
#define SMMU_GNSR0_S2CR82 (0xd48)
#define SMMU_GNSR0_S2CR83 (0xd4c)
#define SMMU_GNSR0_S2CR84 (0xd50)
#define SMMU_GNSR0_S2CR85 (0xd54)
#define SMMU_GNSR0_S2CR86 (0xd58)
#define SMMU_GNSR0_S2CR87 (0xd5c)
#define SMMU_GNSR0_S2CR88 (0xd60)
#define SMMU_GNSR0_S2CR89 (0xd64)
#define SMMU_GNSR0_S2CR90 (0xd68)
#define SMMU_GNSR0_S2CR91 (0xd6c)
#define SMMU_GNSR0_S2CR92 (0xd70)
#define SMMU_GNSR0_S2CR93 (0xd74)
#define SMMU_GNSR0_S2CR94 (0xd78)
#define SMMU_GNSR0_S2CR95 (0xd7c)
#define SMMU_GNSR0_S2CR96 (0xd80)
#define SMMU_GNSR0_S2CR97 (0xd84)
#define SMMU_GNSR0_S2CR98 (0xd88)
#define SMMU_GNSR0_S2CR99 (0xd8c)
#define SMMU_GNSR0_S2CR100 (0xd90)
#define SMMU_GNSR0_S2CR101 (0xd94)
#define SMMU_GNSR0_S2CR102 (0xd98)
#define SMMU_GNSR0_S2CR103 (0xd9c)
#define SMMU_GNSR0_S2CR104 (0xda0)
#define SMMU_GNSR0_S2CR105 (0xda4)
#define SMMU_GNSR0_S2CR106 (0xda8)
#define SMMU_GNSR0_S2CR107 (0xdac)
#define SMMU_GNSR0_S2CR108 (0xdb0)
#define SMMU_GNSR0_S2CR109 (0xdb4)
#define SMMU_GNSR0_S2CR110 (0xdb8)
#define SMMU_GNSR0_S2CR111 (0xdbc)
#define SMMU_GNSR0_S2CR112 (0xdc0)
#define SMMU_GNSR0_S2CR113 (0xdc4)
#define SMMU_GNSR0_S2CR114 (0xdc8)
#define SMMU_GNSR0_S2CR115 (0xdcc)
#define SMMU_GNSR0_S2CR116 (0xdd0)
#define SMMU_GNSR0_S2CR117 (0xdd4)
#define SMMU_GNSR0_S2CR118 (0xdd8)
#define SMMU_GNSR0_S2CR119 (0xddc)
#define SMMU_GNSR0_S2CR120 (0xde0)
#define SMMU_GNSR0_S2CR121 (0xde4)
#define SMMU_GNSR0_S2CR122 (0xde8)
#define SMMU_GNSR0_S2CR123 (0xdec)
#define SMMU_GNSR0_S2CR124 (0xdf0)
#define SMMU_GNSR0_S2CR125 (0xdf4)
#define SMMU_GNSR0_S2CR126 (0xdf8)
#define SMMU_GNSR0_S2CR127 (0xdfc)
#define SMMU_GNSR0_PIDR0 (0xfe0)
#define SMMU_GNSR0_PIDR1 (0xfe4)
#define SMMU_GNSR0_PIDR2 (0xfe8)
#define SMMU_GNSR0_PIDR3 (0xfec)
#define SMMU_GNSR0_PIDR4 (0xfd0)
#define SMMU_GNSR0_PIDR5 (0xfd4)
#define SMMU_GNSR0_PIDR6 (0xfd8)
#define SMMU_GNSR0_PIDR7 (0xfdc)
#define SMMU_GNSR0_CIDR0 (0xff0)
#define SMMU_GNSR0_CIDR1 (0xff4)
#define SMMU_GNSR0_CIDR2 (0xff8)
#define SMMU_GNSR0_CIDR3 (0xffc)
#define SMMU_GNSR1_CBAR0 (0x0)
#define SMMU_GNSR1_CBARn (0x0)
#define SMMU_GNSR1_CBFRSYNRA0 (0x400)
#define SMMU_GNSR1_CBA2R0 (0x800)
#define SMMU_GNSR1_CBAR1 (0x4)
#define SMMU_GNSR1_CBFRSYNRA1 (0x404)
#define SMMU_GNSR1_CBA2R1 (0x804)
#define SMMU_GNSR1_CBAR2 (0x8)
#define SMMU_GNSR1_CBFRSYNRA2 (0x408)
#define SMMU_GNSR1_CBA2R2 (0x808)
#define SMMU_GNSR1_CBAR3 (0xc)
#define SMMU_GNSR1_CBFRSYNRA3 (0x40c)
#define SMMU_GNSR1_CBA2R3 (0x80c)
#define SMMU_GNSR1_CBAR4 (0x10)
#define SMMU_GNSR1_CBFRSYNRA4 (0x410)
#define SMMU_GNSR1_CBA2R4 (0x810)
#define SMMU_GNSR1_CBAR5 (0x14)
#define SMMU_GNSR1_CBFRSYNRA5 (0x414)
#define SMMU_GNSR1_CBA2R5 (0x814)
#define SMMU_GNSR1_CBAR6 (0x18)
#define SMMU_GNSR1_CBFRSYNRA6 (0x418)
#define SMMU_GNSR1_CBA2R6 (0x818)
#define SMMU_GNSR1_CBAR7 (0x1c)
#define SMMU_GNSR1_CBFRSYNRA7 (0x41c)
#define SMMU_GNSR1_CBA2R7 (0x81c)
#define SMMU_GNSR1_CBAR8 (0x20)
#define SMMU_GNSR1_CBFRSYNRA8 (0x420)
#define SMMU_GNSR1_CBA2R8 (0x820)
#define SMMU_GNSR1_CBAR9 (0x24)
#define SMMU_GNSR1_CBFRSYNRA9 (0x424)
#define SMMU_GNSR1_CBA2R9 (0x824)
#define SMMU_GNSR1_CBAR10 (0x28)
#define SMMU_GNSR1_CBFRSYNRA10 (0x428)
#define SMMU_GNSR1_CBA2R10 (0x828)
#define SMMU_GNSR1_CBAR11 (0x2c)
#define SMMU_GNSR1_CBFRSYNRA11 (0x42c)
#define SMMU_GNSR1_CBA2R11 (0x82c)
#define SMMU_GNSR1_CBAR12 (0x30)
#define SMMU_GNSR1_CBFRSYNRA12 (0x430)
#define SMMU_GNSR1_CBA2R12 (0x830)
#define SMMU_GNSR1_CBAR13 (0x34)
#define SMMU_GNSR1_CBFRSYNRA13 (0x434)
#define SMMU_GNSR1_CBA2R13 (0x834)
#define SMMU_GNSR1_CBAR14 (0x38)
#define SMMU_GNSR1_CBFRSYNRA14 (0x438)
#define SMMU_GNSR1_CBA2R14 (0x838)
#define SMMU_GNSR1_CBAR15 (0x3c)
#define SMMU_GNSR1_CBFRSYNRA15 (0x43c)
#define SMMU_GNSR1_CBA2R15 (0x83c)
#define SMMU_GNSR1_CBAR16 (0x40)
#define SMMU_GNSR1_CBFRSYNRA16 (0x440)
#define SMMU_GNSR1_CBA2R16 (0x840)
#define SMMU_GNSR1_CBAR17 (0x44)
#define SMMU_GNSR1_CBFRSYNRA17 (0x444)
#define SMMU_GNSR1_CBA2R17 (0x844)
#define SMMU_GNSR1_CBAR18 (0x48)
#define SMMU_GNSR1_CBFRSYNRA18 (0x448)
#define SMMU_GNSR1_CBA2R18 (0x848)
#define SMMU_GNSR1_CBAR19 (0x4c)
#define SMMU_GNSR1_CBFRSYNRA19 (0x44c)
#define SMMU_GNSR1_CBA2R19 (0x84c)
#define SMMU_GNSR1_CBAR20 (0x50)
#define SMMU_GNSR1_CBFRSYNRA20 (0x450)
#define SMMU_GNSR1_CBA2R20 (0x850)
#define SMMU_GNSR1_CBAR21 (0x54)
#define SMMU_GNSR1_CBFRSYNRA21 (0x454)
#define SMMU_GNSR1_CBA2R21 (0x854)
#define SMMU_GNSR1_CBAR22 (0x58)
#define SMMU_GNSR1_CBFRSYNRA22 (0x458)
#define SMMU_GNSR1_CBA2R22 (0x858)
#define SMMU_GNSR1_CBAR23 (0x5c)
#define SMMU_GNSR1_CBFRSYNRA23 (0x45c)
#define SMMU_GNSR1_CBA2R23 (0x85c)
#define SMMU_GNSR1_CBAR24 (0x60)
#define SMMU_GNSR1_CBFRSYNRA24 (0x460)
#define SMMU_GNSR1_CBA2R24 (0x860)
#define SMMU_GNSR1_CBAR25 (0x64)
#define SMMU_GNSR1_CBFRSYNRA25 (0x464)
#define SMMU_GNSR1_CBA2R25 (0x864)
#define SMMU_GNSR1_CBAR26 (0x68)
#define SMMU_GNSR1_CBFRSYNRA26 (0x468)
#define SMMU_GNSR1_CBA2R26 (0x868)
#define SMMU_GNSR1_CBAR27 (0x6c)
#define SMMU_GNSR1_CBFRSYNRA27 (0x46c)
#define SMMU_GNSR1_CBA2R27 (0x86c)
#define SMMU_GNSR1_CBAR28 (0x70)
#define SMMU_GNSR1_CBFRSYNRA28 (0x470)
#define SMMU_GNSR1_CBA2R28 (0x870)
#define SMMU_GNSR1_CBAR29 (0x74)
#define SMMU_GNSR1_CBFRSYNRA29 (0x474)
#define SMMU_GNSR1_CBA2R29 (0x874)
#define SMMU_GNSR1_CBAR30 (0x78)
#define SMMU_GNSR1_CBFRSYNRA30 (0x478)
#define SMMU_GNSR1_CBA2R30 (0x878)
#define SMMU_GNSR1_CBAR31 (0x7c)
#define SMMU_GNSR1_CBFRSYNRA31 (0x47c)
#define SMMU_GNSR1_CBA2R31 (0x87c)
#define SMMU_GNSR1_CBAR32 (0x80)
#define SMMU_GNSR1_CBFRSYNRA32 (0x480)
#define SMMU_GNSR1_CBA2R32 (0x880)
#define SMMU_GNSR1_CBAR33 (0x84)
#define SMMU_GNSR1_CBFRSYNRA33 (0x484)
#define SMMU_GNSR1_CBA2R33 (0x884)
#define SMMU_GNSR1_CBAR34 (0x88)
#define SMMU_GNSR1_CBFRSYNRA34 (0x488)
#define SMMU_GNSR1_CBA2R34 (0x888)
#define SMMU_GNSR1_CBAR35 (0x8c)
#define SMMU_GNSR1_CBFRSYNRA35 (0x48c)
#define SMMU_GNSR1_CBA2R35 (0x88c)
#define SMMU_GNSR1_CBAR36 (0x90)
#define SMMU_GNSR1_CBFRSYNRA36 (0x490)
#define SMMU_GNSR1_CBA2R36 (0x890)
#define SMMU_GNSR1_CBAR37 (0x94)
#define SMMU_GNSR1_CBFRSYNRA37 (0x494)
#define SMMU_GNSR1_CBA2R37 (0x894)
#define SMMU_GNSR1_CBAR38 (0x98)
#define SMMU_GNSR1_CBFRSYNRA38 (0x498)
#define SMMU_GNSR1_CBA2R38 (0x898)
#define SMMU_GNSR1_CBAR39 (0x9c)
#define SMMU_GNSR1_CBFRSYNRA39 (0x49c)
#define SMMU_GNSR1_CBA2R39 (0x89c)
#define SMMU_GNSR1_CBAR40 (0xa0)
#define SMMU_GNSR1_CBFRSYNRA40 (0x4a0)
#define SMMU_GNSR1_CBA2R40 (0x8a0)
#define SMMU_GNSR1_CBAR41 (0xa4)
#define SMMU_GNSR1_CBFRSYNRA41 (0x4a4)
#define SMMU_GNSR1_CBA2R41 (0x8a4)
#define SMMU_GNSR1_CBAR42 (0xa8)
#define SMMU_GNSR1_CBFRSYNRA42 (0x4a8)
#define SMMU_GNSR1_CBA2R42 (0x8a8)
#define SMMU_GNSR1_CBAR43 (0xac)
#define SMMU_GNSR1_CBFRSYNRA43 (0x4ac)
#define SMMU_GNSR1_CBA2R43 (0x8ac)
#define SMMU_GNSR1_CBAR44 (0xb0)
#define SMMU_GNSR1_CBFRSYNRA44 (0x4b0)
#define SMMU_GNSR1_CBA2R44 (0x8b0)
#define SMMU_GNSR1_CBAR45 (0xb4)
#define SMMU_GNSR1_CBFRSYNRA45 (0x4b4)
#define SMMU_GNSR1_CBA2R45 (0x8b4)
#define SMMU_GNSR1_CBAR46 (0xb8)
#define SMMU_GNSR1_CBFRSYNRA46 (0x4b8)
#define SMMU_GNSR1_CBA2R46 (0x8b8)
#define SMMU_GNSR1_CBAR47 (0xbc)
#define SMMU_GNSR1_CBFRSYNRA47 (0x4bc)
#define SMMU_GNSR1_CBA2R47 (0x8bc)
#define SMMU_GNSR1_CBAR48 (0xc0)
#define SMMU_GNSR1_CBFRSYNRA48 (0x4c0)
#define SMMU_GNSR1_CBA2R48 (0x8c0)
#define SMMU_GNSR1_CBAR49 (0xc4)
#define SMMU_GNSR1_CBFRSYNRA49 (0x4c4)
#define SMMU_GNSR1_CBA2R49 (0x8c4)
#define SMMU_GNSR1_CBAR50 (0xc8)
#define SMMU_GNSR1_CBFRSYNRA50 (0x4c8)
#define SMMU_GNSR1_CBA2R50 (0x8c8)
#define SMMU_GNSR1_CBAR51 (0xcc)
#define SMMU_GNSR1_CBFRSYNRA51 (0x4cc)
#define SMMU_GNSR1_CBA2R51 (0x8cc)
#define SMMU_GNSR1_CBAR52 (0xd0)
#define SMMU_GNSR1_CBFRSYNRA52 (0x4d0)
#define SMMU_GNSR1_CBA2R52 (0x8d0)
#define SMMU_GNSR1_CBAR53 (0xd4)
#define SMMU_GNSR1_CBFRSYNRA53 (0x4d4)
#define SMMU_GNSR1_CBA2R53 (0x8d4)
#define SMMU_GNSR1_CBAR54 (0xd8)
#define SMMU_GNSR1_CBFRSYNRA54 (0x4d8)
#define SMMU_GNSR1_CBA2R54 (0x8d8)
#define SMMU_GNSR1_CBAR55 (0xdc)
#define SMMU_GNSR1_CBFRSYNRA55 (0x4dc)
#define SMMU_GNSR1_CBA2R55 (0x8dc)
#define SMMU_GNSR1_CBAR56 (0xe0)
#define SMMU_GNSR1_CBFRSYNRA56 (0x4e0)
#define SMMU_GNSR1_CBA2R56 (0x8e0)
#define SMMU_GNSR1_CBAR57 (0xe4)
#define SMMU_GNSR1_CBFRSYNRA57 (0x4e4)
#define SMMU_GNSR1_CBA2R57 (0x8e4)
#define SMMU_GNSR1_CBAR58 (0xe8)
#define SMMU_GNSR1_CBFRSYNRA58 (0x4e8)
#define SMMU_GNSR1_CBA2R58 (0x8e8)
#define SMMU_GNSR1_CBAR59 (0xec)
#define SMMU_GNSR1_CBFRSYNRA59 (0x4ec)
#define SMMU_GNSR1_CBA2R59 (0x8ec)
#define SMMU_GNSR1_CBAR60 (0xf0)
#define SMMU_GNSR1_CBFRSYNRA60 (0x4f0)
#define SMMU_GNSR1_CBA2R60 (0x8f0)
#define SMMU_GNSR1_CBAR61 (0xf4)
#define SMMU_GNSR1_CBFRSYNRA61 (0x4f4)
#define SMMU_GNSR1_CBA2R61 (0x8f4)
#define SMMU_GNSR1_CBAR62 (0xf8)
#define SMMU_GNSR1_CBFRSYNRA62 (0x4f8)
#define SMMU_GNSR1_CBA2R62 (0x8f8)
#define SMMU_GNSR1_CBAR63 (0xfc)
#define SMMU_GNSR1_CBFRSYNRA63 (0x4fc)
#define SMMU_GNSR1_CBA2R63 (0x8fc)
#define SMMU_CBn_SCTLR (0x0U)
#define SMMU_CBn_SCTLR_STAGE2 (0x0U)
#define SMMU_CBn_ACTLR (0x4U)
#define SMMU_CBn_RESUME (0x8U)
#define SMMU_CBn_TCR2 (0x10U)
#define SMMU_CBn_TTBR0_LO (0x20U)
#define SMMU_CBn_TTBR0_HI (0x24U)
#define SMMU_CBn_TTBR1_LO (0x28U)
#define SMMU_CBn_TTBR1_HI (0x2cU)
#define SMMU_CBn_TCR_LPAE (0x30U)
#define SMMU_CBn_TCR (0x30U)
#define SMMU_CBn_TCR_EAE_1 (0x30U)
#define SMMU_CBn_TCR (0x30U)
#define SMMU_CBn_CONTEXTIDR (0x34U)
#define SMMU_CBn_CONTEXTIDR_EAE_1 (0x34U)
#define SMMU_CBn_PRRR_MAIR0 (0x38U)
#define SMMU_CBn_NMRR_MAIR1 (0x3cU)
#define SMMU_CBn_SMMU_CBn_PAR (0x50U)
#define SMMU_CBn_SMMU_CBn_PAR0 (0x50U)
#define SMMU_CBn_SMMU_CBn_PAR1 (0x54U)
/* SMMU_CBn_SMMU_CBn_PAR0_Fault (0x50U) */
/* SMMU_CBn_SMMU_CBn_PAR0_Fault (0x54U) */
#define SMMU_CBn_FSR (0x58U)
#define SMMU_CBn_FSRRESTORE (0x5cU)
#define SMMU_CBn_FAR_LO (0x60U)
#define SMMU_CBn_FAR_HI (0x64U)
#define SMMU_CBn_FSYNR0 (0x68U)
#define SMMU_CBn_IPAFAR_LO (0x70U)
#define SMMU_CBn_IPAFAR_HI (0x74U)
#define SMMU_CBn_TLBIVA_LO (0x600U)
#define SMMU_CBn_TLBIVA_HI (0x604U)
#define SMMU_CBn_TLBIVA_AARCH_32 (0x600U)
#define SMMU_CBn_TLBIVAA_LO (0x608U)
#define SMMU_CBn_TLBIVAA_HI (0x60cU)
#define SMMU_CBn_TLBIVAA_AARCH_32 (0x608U)
#define SMMU_CBn_TLBIASID (0x610U)
#define SMMU_CBn_TLBIALL (0x618U)
#define SMMU_CBn_TLBIVAL_LO (0x620U)
#define SMMU_CBn_TLBIVAL_HI (0x624U)
#define SMMU_CBn_TLBIVAL_AARCH_32 (0x618U)
#define SMMU_CBn_TLBIVAAL_LO (0x628U)
#define SMMU_CBn_TLBIVAAL_HI (0x62cU)
#define SMMU_CBn_TLBIVAAL_AARCH_32 (0x628U)
#define SMMU_CBn_TLBIIPAS2_LO (0x630U)
#define SMMU_CBn_TLBIIPAS2_HI (0x634U)
#define SMMU_CBn_TLBIIPAS2L_LO (0x638U)
#define SMMU_CBn_TLBIIPAS2L_HI (0x63cU)
#define SMMU_CBn_TLBSYNC (0x7f0U)
#define SMMU_CBn_TLBSTATUS (0x7f4U)
#define SMMU_CBn_ATSR (0x800U)
#define SMMU_CBn_PMEVCNTR0 (0xe00U)
#define SMMU_CBn_PMEVCNTR1 (0xe04U)
#define SMMU_CBn_PMEVCNTR2 (0xe08U)
#define SMMU_CBn_PMEVCNTR3 (0xe0cU)
#define SMMU_CBn_PMEVTYPER0 (0xe80U)
#define SMMU_CBn_PMEVTYPER1 (0xe84U)
#define SMMU_CBn_PMEVTYPER2 (0xe88U)
#define SMMU_CBn_PMEVTYPER3 (0xe8cU)
#define SMMU_CBn_PMCFGR (0xf00U)
#define SMMU_CBn_PMCR (0xf04U)
#define SMMU_CBn_PMCEID (0xf20U)
#define SMMU_CBn_PMCNTENSE (0xf40U)
#define SMMU_CBn_PMCNTENCLR (0xf44U)
#define SMMU_CBn_PMCNTENSET (0xf48U)
#define SMMU_CBn_PMINTENCLR (0xf4cU)
#define SMMU_CBn_PMOVSCLR (0xf50U)
#define SMMU_CBn_PMOVSSET (0xf58U)
#define SMMU_CBn_PMAUTHSTATUS (0xfb8U)
#define SMMU_GNSR0_CR0 (0x0U)
#define SMMU_GNSR0_CR2 (0x8U)
#define SMMU_GNSR0_ACR (0x10U)
#define SMMU_GNSR0_IDR0 (0x20U)
#define SMMU_GNSR0_IDR1 (0x24U)
#define SMMU_GNSR0_IDR2 (0x28U)
#define SMMU_GNSR0_IDR7 (0x3cU)
#define SMMU_GNSR0_GFAR_LO (0x40U)
#define SMMU_GNSR0_GFAR_HI (0x44U)
#define SMMU_GNSR0_GFSR (0x48U)
#define SMMU_GNSR0_GFSRRESTORE (0x4cU)
#define SMMU_GNSR0_GFSYNR0 (0x50U)
#define SMMU_GNSR0_GFSYNR1 (0x54U)
#define SMMU_GNSR0_GFSYNR1_v2 (0x54U)
#define SMMU_GNSR0_TLBIVMID (0x64U)
#define SMMU_GNSR0_TLBIALLNSNH (0x68U)
#define SMMU_GNSR0_TLBIALLH (0x6cU)
#define SMMU_GNSR0_TLBGSYNC (0x70U)
#define SMMU_GNSR0_TLBGSTATUS (0x74U)
#define SMMU_GNSR0_TLBIVAH_LO (0x78U)
#define SMMU_GNSR0_TLBIVALH64_LO (0xb0U)
#define SMMU_GNSR0_TLBIVALH64_HI (0xb4U)
#define SMMU_GNSR0_TLBIVMIDS1 (0xb8U)
#define SMMU_GNSR0_TLBIVAH64_LO (0xc0U)
#define SMMU_GNSR0_TLBIVAH64_HI (0xc4U)
#define SMMU_GNSR0_SMR0 (0x800U)
#define SMMU_GNSR0_SMRn (0x800U)
#define SMMU_GNSR0_SMR1 (0x804U)
#define SMMU_GNSR0_SMR2 (0x808U)
#define SMMU_GNSR0_SMR3 (0x80cU)
#define SMMU_GNSR0_SMR4 (0x810U)
#define SMMU_GNSR0_SMR5 (0x814U)
#define SMMU_GNSR0_SMR6 (0x818U)
#define SMMU_GNSR0_SMR7 (0x81cU)
#define SMMU_GNSR0_SMR8 (0x820U)
#define SMMU_GNSR0_SMR9 (0x824U)
#define SMMU_GNSR0_SMR10 (0x828U)
#define SMMU_GNSR0_SMR11 (0x82cU)
#define SMMU_GNSR0_SMR12 (0x830U)
#define SMMU_GNSR0_SMR13 (0x834U)
#define SMMU_GNSR0_SMR14 (0x838U)
#define SMMU_GNSR0_SMR15 (0x83cU)
#define SMMU_GNSR0_SMR16 (0x840U)
#define SMMU_GNSR0_SMR17 (0x844U)
#define SMMU_GNSR0_SMR18 (0x848U)
#define SMMU_GNSR0_SMR19 (0x84cU)
#define SMMU_GNSR0_SMR20 (0x850U)
#define SMMU_GNSR0_SMR21 (0x854U)
#define SMMU_GNSR0_SMR22 (0x858U)
#define SMMU_GNSR0_SMR23 (0x85cU)
#define SMMU_GNSR0_SMR24 (0x860U)
#define SMMU_GNSR0_SMR25 (0x864U)
#define SMMU_GNSR0_SMR26 (0x868U)
#define SMMU_GNSR0_SMR27 (0x86cU)
#define SMMU_GNSR0_SMR28 (0x870U)
#define SMMU_GNSR0_SMR29 (0x874U)
#define SMMU_GNSR0_SMR30 (0x878U)
#define SMMU_GNSR0_SMR31 (0x87cU)
#define SMMU_GNSR0_SMR32 (0x880U)
#define SMMU_GNSR0_SMR33 (0x884U)
#define SMMU_GNSR0_SMR34 (0x888U)
#define SMMU_GNSR0_SMR35 (0x88cU)
#define SMMU_GNSR0_SMR36 (0x890U)
#define SMMU_GNSR0_SMR37 (0x894U)
#define SMMU_GNSR0_SMR38 (0x898U)
#define SMMU_GNSR0_SMR39 (0x89cU)
#define SMMU_GNSR0_SMR40 (0x8a0U)
#define SMMU_GNSR0_SMR41 (0x8a4U)
#define SMMU_GNSR0_SMR42 (0x8a8U)
#define SMMU_GNSR0_SMR43 (0x8acU)
#define SMMU_GNSR0_SMR44 (0x8b0U)
#define SMMU_GNSR0_SMR45 (0x8b4U)
#define SMMU_GNSR0_SMR46 (0x8b8U)
#define SMMU_GNSR0_SMR47 (0x8bcU)
#define SMMU_GNSR0_SMR48 (0x8c0U)
#define SMMU_GNSR0_SMR49 (0x8c4U)
#define SMMU_GNSR0_SMR50 (0x8c8U)
#define SMMU_GNSR0_SMR51 (0x8ccU)
#define SMMU_GNSR0_SMR52 (0x8d0U)
#define SMMU_GNSR0_SMR53 (0x8d4U)
#define SMMU_GNSR0_SMR54 (0x8d8U)
#define SMMU_GNSR0_SMR55 (0x8dcU)
#define SMMU_GNSR0_SMR56 (0x8e0U)
#define SMMU_GNSR0_SMR57 (0x8e4U)
#define SMMU_GNSR0_SMR58 (0x8e8U)
#define SMMU_GNSR0_SMR59 (0x8ecU)
#define SMMU_GNSR0_SMR60 (0x8f0U)
#define SMMU_GNSR0_SMR61 (0x8f4U)
#define SMMU_GNSR0_SMR62 (0x8f8U)
#define SMMU_GNSR0_SMR63 (0x8fcU)
#define SMMU_GNSR0_SMR64 (0x900U)
#define SMMU_GNSR0_SMR65 (0x904U)
#define SMMU_GNSR0_SMR66 (0x908U)
#define SMMU_GNSR0_SMR67 (0x90cU)
#define SMMU_GNSR0_SMR68 (0x910U)
#define SMMU_GNSR0_SMR69 (0x914U)
#define SMMU_GNSR0_SMR70 (0x918U)
#define SMMU_GNSR0_SMR71 (0x91cU)
#define SMMU_GNSR0_SMR72 (0x920U)
#define SMMU_GNSR0_SMR73 (0x924U)
#define SMMU_GNSR0_SMR74 (0x928U)
#define SMMU_GNSR0_SMR75 (0x92cU)
#define SMMU_GNSR0_SMR76 (0x930U)
#define SMMU_GNSR0_SMR77 (0x934U)
#define SMMU_GNSR0_SMR78 (0x938U)
#define SMMU_GNSR0_SMR79 (0x93cU)
#define SMMU_GNSR0_SMR80 (0x940U)
#define SMMU_GNSR0_SMR81 (0x944U)
#define SMMU_GNSR0_SMR82 (0x948U)
#define SMMU_GNSR0_SMR83 (0x94cU)
#define SMMU_GNSR0_SMR84 (0x950U)
#define SMMU_GNSR0_SMR85 (0x954U)
#define SMMU_GNSR0_SMR86 (0x958U)
#define SMMU_GNSR0_SMR87 (0x95cU)
#define SMMU_GNSR0_SMR88 (0x960U)
#define SMMU_GNSR0_SMR89 (0x964U)
#define SMMU_GNSR0_SMR90 (0x968U)
#define SMMU_GNSR0_SMR91 (0x96cU)
#define SMMU_GNSR0_SMR92 (0x970U)
#define SMMU_GNSR0_SMR93 (0x974U)
#define SMMU_GNSR0_SMR94 (0x978U)
#define SMMU_GNSR0_SMR95 (0x97cU)
#define SMMU_GNSR0_SMR96 (0x980U)
#define SMMU_GNSR0_SMR97 (0x984U)
#define SMMU_GNSR0_SMR98 (0x988U)
#define SMMU_GNSR0_SMR99 (0x98cU)
#define SMMU_GNSR0_SMR100 (0x990U)
#define SMMU_GNSR0_SMR101 (0x994U)
#define SMMU_GNSR0_SMR102 (0x998U)
#define SMMU_GNSR0_SMR103 (0x99cU)
#define SMMU_GNSR0_SMR104 (0x9a0U)
#define SMMU_GNSR0_SMR105 (0x9a4U)
#define SMMU_GNSR0_SMR106 (0x9a8U)
#define SMMU_GNSR0_SMR107 (0x9acU)
#define SMMU_GNSR0_SMR108 (0x9b0U)
#define SMMU_GNSR0_SMR109 (0x9b4U)
#define SMMU_GNSR0_SMR110 (0x9b8U)
#define SMMU_GNSR0_SMR111 (0x9bcU)
#define SMMU_GNSR0_SMR112 (0x9c0U)
#define SMMU_GNSR0_SMR113 (0x9c4U)
#define SMMU_GNSR0_SMR114 (0x9c8U)
#define SMMU_GNSR0_SMR115 (0x9ccU)
#define SMMU_GNSR0_SMR116 (0x9d0U)
#define SMMU_GNSR0_SMR117 (0x9d4U)
#define SMMU_GNSR0_SMR118 (0x9d8U)
#define SMMU_GNSR0_SMR119 (0x9dcU)
#define SMMU_GNSR0_SMR120 (0x9e0U)
#define SMMU_GNSR0_SMR121 (0x9e4U)
#define SMMU_GNSR0_SMR122 (0x9e8U)
#define SMMU_GNSR0_SMR123 (0x9ecU)
#define SMMU_GNSR0_SMR124 (0x9f0U)
#define SMMU_GNSR0_SMR125 (0x9f4U)
#define SMMU_GNSR0_SMR126 (0x9f8U)
#define SMMU_GNSR0_SMR127 (0x9fcU)
#define SMMU_GNSR0_S2CR0 (0xc00U)
#define SMMU_GNSR0_S2CRn (0xc00U)
#define SMMU_GNSR0_S2CRn (0xc00U)
#define SMMU_GNSR0_S2CR1 (0xc04U)
#define SMMU_GNSR0_S2CR2 (0xc08U)
#define SMMU_GNSR0_S2CR3 (0xc0cU)
#define SMMU_GNSR0_S2CR4 (0xc10U)
#define SMMU_GNSR0_S2CR5 (0xc14U)
#define SMMU_GNSR0_S2CR6 (0xc18U)
#define SMMU_GNSR0_S2CR7 (0xc1cU)
#define SMMU_GNSR0_S2CR8 (0xc20U)
#define SMMU_GNSR0_S2CR9 (0xc24U)
#define SMMU_GNSR0_S2CR10 (0xc28U)
#define SMMU_GNSR0_S2CR11 (0xc2cU)
#define SMMU_GNSR0_S2CR12 (0xc30U)
#define SMMU_GNSR0_S2CR13 (0xc34U)
#define SMMU_GNSR0_S2CR14 (0xc38U)
#define SMMU_GNSR0_S2CR15 (0xc3cU)
#define SMMU_GNSR0_S2CR16 (0xc40U)
#define SMMU_GNSR0_S2CR17 (0xc44U)
#define SMMU_GNSR0_S2CR18 (0xc48U)
#define SMMU_GNSR0_S2CR19 (0xc4cU)
#define SMMU_GNSR0_S2CR20 (0xc50U)
#define SMMU_GNSR0_S2CR21 (0xc54U)
#define SMMU_GNSR0_S2CR22 (0xc58U)
#define SMMU_GNSR0_S2CR23 (0xc5cU)
#define SMMU_GNSR0_S2CR24 (0xc60U)
#define SMMU_GNSR0_S2CR25 (0xc64U)
#define SMMU_GNSR0_S2CR26 (0xc68U)
#define SMMU_GNSR0_S2CR27 (0xc6cU)
#define SMMU_GNSR0_S2CR28 (0xc70U)
#define SMMU_GNSR0_S2CR29 (0xc74U)
#define SMMU_GNSR0_S2CR30 (0xc78U)
#define SMMU_GNSR0_S2CR31 (0xc7cU)
#define SMMU_GNSR0_S2CR32 (0xc80U)
#define SMMU_GNSR0_S2CR33 (0xc84U)
#define SMMU_GNSR0_S2CR34 (0xc88U)
#define SMMU_GNSR0_S2CR35 (0xc8cU)
#define SMMU_GNSR0_S2CR36 (0xc90U)
#define SMMU_GNSR0_S2CR37 (0xc94U)
#define SMMU_GNSR0_S2CR38 (0xc98U)
#define SMMU_GNSR0_S2CR39 (0xc9cU)
#define SMMU_GNSR0_S2CR40 (0xca0U)
#define SMMU_GNSR0_S2CR41 (0xca4U)
#define SMMU_GNSR0_S2CR42 (0xca8U)
#define SMMU_GNSR0_S2CR43 (0xcacU)
#define SMMU_GNSR0_S2CR44 (0xcb0U)
#define SMMU_GNSR0_S2CR45 (0xcb4U)
#define SMMU_GNSR0_S2CR46 (0xcb8U)
#define SMMU_GNSR0_S2CR47 (0xcbcU)
#define SMMU_GNSR0_S2CR48 (0xcc0U)
#define SMMU_GNSR0_S2CR49 (0xcc4U)
#define SMMU_GNSR0_S2CR50 (0xcc8U)
#define SMMU_GNSR0_S2CR51 (0xcccU)
#define SMMU_GNSR0_S2CR52 (0xcd0U)
#define SMMU_GNSR0_S2CR53 (0xcd4U)
#define SMMU_GNSR0_S2CR54 (0xcd8U)
#define SMMU_GNSR0_S2CR55 (0xcdcU)
#define SMMU_GNSR0_S2CR56 (0xce0U)
#define SMMU_GNSR0_S2CR57 (0xce4U)
#define SMMU_GNSR0_S2CR58 (0xce8U)
#define SMMU_GNSR0_S2CR59 (0xcecU)
#define SMMU_GNSR0_S2CR60 (0xcf0U)
#define SMMU_GNSR0_S2CR61 (0xcf4U)
#define SMMU_GNSR0_S2CR62 (0xcf8U)
#define SMMU_GNSR0_S2CR63 (0xcfcU)
#define SMMU_GNSR0_S2CR64 (0xd00U)
#define SMMU_GNSR0_S2CR65 (0xd04U)
#define SMMU_GNSR0_S2CR66 (0xd08U)
#define SMMU_GNSR0_S2CR67 (0xd0cU)
#define SMMU_GNSR0_S2CR68 (0xd10U)
#define SMMU_GNSR0_S2CR69 (0xd14U)
#define SMMU_GNSR0_S2CR70 (0xd18U)
#define SMMU_GNSR0_S2CR71 (0xd1cU)
#define SMMU_GNSR0_S2CR72 (0xd20U)
#define SMMU_GNSR0_S2CR73 (0xd24U)
#define SMMU_GNSR0_S2CR74 (0xd28U)
#define SMMU_GNSR0_S2CR75 (0xd2cU)
#define SMMU_GNSR0_S2CR76 (0xd30U)
#define SMMU_GNSR0_S2CR77 (0xd34U)
#define SMMU_GNSR0_S2CR78 (0xd38U)
#define SMMU_GNSR0_S2CR79 (0xd3cU)
#define SMMU_GNSR0_S2CR80 (0xd40U)
#define SMMU_GNSR0_S2CR81 (0xd44U)
#define SMMU_GNSR0_S2CR82 (0xd48U)
#define SMMU_GNSR0_S2CR83 (0xd4cU)
#define SMMU_GNSR0_S2CR84 (0xd50U)
#define SMMU_GNSR0_S2CR85 (0xd54U)
#define SMMU_GNSR0_S2CR86 (0xd58U)
#define SMMU_GNSR0_S2CR87 (0xd5cU)
#define SMMU_GNSR0_S2CR88 (0xd60U)
#define SMMU_GNSR0_S2CR89 (0xd64U)
#define SMMU_GNSR0_S2CR90 (0xd68U)
#define SMMU_GNSR0_S2CR91 (0xd6cU)
#define SMMU_GNSR0_S2CR92 (0xd70U)
#define SMMU_GNSR0_S2CR93 (0xd74U)
#define SMMU_GNSR0_S2CR94 (0xd78U)
#define SMMU_GNSR0_S2CR95 (0xd7cU)
#define SMMU_GNSR0_S2CR96 (0xd80U)
#define SMMU_GNSR0_S2CR97 (0xd84U)
#define SMMU_GNSR0_S2CR98 (0xd88U)
#define SMMU_GNSR0_S2CR99 (0xd8cU)
#define SMMU_GNSR0_S2CR100 (0xd90U)
#define SMMU_GNSR0_S2CR101 (0xd94U)
#define SMMU_GNSR0_S2CR102 (0xd98U)
#define SMMU_GNSR0_S2CR103 (0xd9cU)
#define SMMU_GNSR0_S2CR104 (0xda0U)
#define SMMU_GNSR0_S2CR105 (0xda4U)
#define SMMU_GNSR0_S2CR106 (0xda8U)
#define SMMU_GNSR0_S2CR107 (0xdacU)
#define SMMU_GNSR0_S2CR108 (0xdb0U)
#define SMMU_GNSR0_S2CR109 (0xdb4U)
#define SMMU_GNSR0_S2CR110 (0xdb8U)
#define SMMU_GNSR0_S2CR111 (0xdbcU)
#define SMMU_GNSR0_S2CR112 (0xdc0U)
#define SMMU_GNSR0_S2CR113 (0xdc4U)
#define SMMU_GNSR0_S2CR114 (0xdc8U)
#define SMMU_GNSR0_S2CR115 (0xdccU)
#define SMMU_GNSR0_S2CR116 (0xdd0U)
#define SMMU_GNSR0_S2CR117 (0xdd4U)
#define SMMU_GNSR0_S2CR118 (0xdd8U)
#define SMMU_GNSR0_S2CR119 (0xddcU)
#define SMMU_GNSR0_S2CR120 (0xde0U)
#define SMMU_GNSR0_S2CR121 (0xde4U)
#define SMMU_GNSR0_S2CR122 (0xde8U)
#define SMMU_GNSR0_S2CR123 (0xdecU)
#define SMMU_GNSR0_S2CR124 (0xdf0U)
#define SMMU_GNSR0_S2CR125 (0xdf4U)
#define SMMU_GNSR0_S2CR126 (0xdf8U)
#define SMMU_GNSR0_S2CR127 (0xdfcU)
#define SMMU_GNSR0_PIDR0 (0xfe0U)
#define SMMU_GNSR0_PIDR1 (0xfe4U)
#define SMMU_GNSR0_PIDR2 (0xfe8U)
#define SMMU_GNSR0_PIDR3 (0xfecU)
#define SMMU_GNSR0_PIDR4 (0xfd0U)
#define SMMU_GNSR0_PIDR5 (0xfd4U)
#define SMMU_GNSR0_PIDR6 (0xfd8U)
#define SMMU_GNSR0_PIDR7 (0xfdcU)
#define SMMU_GNSR0_CIDR0 (0xff0U)
#define SMMU_GNSR0_CIDR1 (0xff4U)
#define SMMU_GNSR0_CIDR2 (0xff8U)
#define SMMU_GNSR0_CIDR3 (0xffcU)
#define SMMU_GNSR1_CBAR0 (0x0U)
#define SMMU_GNSR1_CBARn (0x0U)
#define SMMU_GNSR1_CBFRSYNRA0 (0x400U)
#define SMMU_GNSR1_CBA2R0 (0x800U)
#define SMMU_GNSR1_CBAR1 (0x4U)
#define SMMU_GNSR1_CBFRSYNRA1 (0x404U)
#define SMMU_GNSR1_CBA2R1 (0x804U)
#define SMMU_GNSR1_CBAR2 (0x8U)
#define SMMU_GNSR1_CBFRSYNRA2 (0x408U)
#define SMMU_GNSR1_CBA2R2 (0x808U)
#define SMMU_GNSR1_CBAR3 (0xcU)
#define SMMU_GNSR1_CBFRSYNRA3 (0x40cU)
#define SMMU_GNSR1_CBA2R3 (0x80cU)
#define SMMU_GNSR1_CBAR4 (0x10U)
#define SMMU_GNSR1_CBFRSYNRA4 (0x410U)
#define SMMU_GNSR1_CBA2R4 (0x810U)
#define SMMU_GNSR1_CBAR5 (0x14U)
#define SMMU_GNSR1_CBFRSYNRA5 (0x414U)
#define SMMU_GNSR1_CBA2R5 (0x814U)
#define SMMU_GNSR1_CBAR6 (0x18U)
#define SMMU_GNSR1_CBFRSYNRA6 (0x418U)
#define SMMU_GNSR1_CBA2R6 (0x818U)
#define SMMU_GNSR1_CBAR7 (0x1cU)
#define SMMU_GNSR1_CBFRSYNRA7 (0x41cU)
#define SMMU_GNSR1_CBA2R7 (0x81cU)
#define SMMU_GNSR1_CBAR8 (0x20U)
#define SMMU_GNSR1_CBFRSYNRA8 (0x420U)
#define SMMU_GNSR1_CBA2R8 (0x820U)
#define SMMU_GNSR1_CBAR9 (0x24U)
#define SMMU_GNSR1_CBFRSYNRA9 (0x424U)
#define SMMU_GNSR1_CBA2R9 (0x824U)
#define SMMU_GNSR1_CBAR10 (0x28U)
#define SMMU_GNSR1_CBFRSYNRA10 (0x428U)
#define SMMU_GNSR1_CBA2R10 (0x828U)
#define SMMU_GNSR1_CBAR11 (0x2cU)
#define SMMU_GNSR1_CBFRSYNRA11 (0x42cU)
#define SMMU_GNSR1_CBA2R11 (0x82cU)
#define SMMU_GNSR1_CBAR12 (0x30U)
#define SMMU_GNSR1_CBFRSYNRA12 (0x430U)
#define SMMU_GNSR1_CBA2R12 (0x830U)
#define SMMU_GNSR1_CBAR13 (0x34U)
#define SMMU_GNSR1_CBFRSYNRA13 (0x434U)
#define SMMU_GNSR1_CBA2R13 (0x834U)
#define SMMU_GNSR1_CBAR14 (0x38U)
#define SMMU_GNSR1_CBFRSYNRA14 (0x438U)
#define SMMU_GNSR1_CBA2R14 (0x838U)
#define SMMU_GNSR1_CBAR15 (0x3cU)
#define SMMU_GNSR1_CBFRSYNRA15 (0x43cU)
#define SMMU_GNSR1_CBA2R15 (0x83cU)
#define SMMU_GNSR1_CBAR16 (0x40U)
#define SMMU_GNSR1_CBFRSYNRA16 (0x440U)
#define SMMU_GNSR1_CBA2R16 (0x840U)
#define SMMU_GNSR1_CBAR17 (0x44U)
#define SMMU_GNSR1_CBFRSYNRA17 (0x444U)
#define SMMU_GNSR1_CBA2R17 (0x844U)
#define SMMU_GNSR1_CBAR18 (0x48U)
#define SMMU_GNSR1_CBFRSYNRA18 (0x448U)
#define SMMU_GNSR1_CBA2R18 (0x848U)
#define SMMU_GNSR1_CBAR19 (0x4cU)
#define SMMU_GNSR1_CBFRSYNRA19 (0x44cU)
#define SMMU_GNSR1_CBA2R19 (0x84cU)
#define SMMU_GNSR1_CBAR20 (0x50U)
#define SMMU_GNSR1_CBFRSYNRA20 (0x450U)
#define SMMU_GNSR1_CBA2R20 (0x850U)
#define SMMU_GNSR1_CBAR21 (0x54U)
#define SMMU_GNSR1_CBFRSYNRA21 (0x454U)
#define SMMU_GNSR1_CBA2R21 (0x854U)
#define SMMU_GNSR1_CBAR22 (0x58U)
#define SMMU_GNSR1_CBFRSYNRA22 (0x458U)
#define SMMU_GNSR1_CBA2R22 (0x858U)
#define SMMU_GNSR1_CBAR23 (0x5cU)
#define SMMU_GNSR1_CBFRSYNRA23 (0x45cU)
#define SMMU_GNSR1_CBA2R23 (0x85cU)
#define SMMU_GNSR1_CBAR24 (0x60U)
#define SMMU_GNSR1_CBFRSYNRA24 (0x460U)
#define SMMU_GNSR1_CBA2R24 (0x860U)
#define SMMU_GNSR1_CBAR25 (0x64U)
#define SMMU_GNSR1_CBFRSYNRA25 (0x464U)
#define SMMU_GNSR1_CBA2R25 (0x864U)
#define SMMU_GNSR1_CBAR26 (0x68U)
#define SMMU_GNSR1_CBFRSYNRA26 (0x468U)
#define SMMU_GNSR1_CBA2R26 (0x868U)
#define SMMU_GNSR1_CBAR27 (0x6cU)
#define SMMU_GNSR1_CBFRSYNRA27 (0x46cU)
#define SMMU_GNSR1_CBA2R27 (0x86cU)
#define SMMU_GNSR1_CBAR28 (0x70U)
#define SMMU_GNSR1_CBFRSYNRA28 (0x470U)
#define SMMU_GNSR1_CBA2R28 (0x870U)
#define SMMU_GNSR1_CBAR29 (0x74U)
#define SMMU_GNSR1_CBFRSYNRA29 (0x474U)
#define SMMU_GNSR1_CBA2R29 (0x874U)
#define SMMU_GNSR1_CBAR30 (0x78U)
#define SMMU_GNSR1_CBFRSYNRA30 (0x478U)
#define SMMU_GNSR1_CBA2R30 (0x878U)
#define SMMU_GNSR1_CBAR31 (0x7cU)
#define SMMU_GNSR1_CBFRSYNRA31 (0x47cU)
#define SMMU_GNSR1_CBA2R31 (0x87cU)
#define SMMU_GNSR1_CBAR32 (0x80U)
#define SMMU_GNSR1_CBFRSYNRA32 (0x480U)
#define SMMU_GNSR1_CBA2R32 (0x880U)
#define SMMU_GNSR1_CBAR33 (0x84U)
#define SMMU_GNSR1_CBFRSYNRA33 (0x484U)
#define SMMU_GNSR1_CBA2R33 (0x884U)
#define SMMU_GNSR1_CBAR34 (0x88U)
#define SMMU_GNSR1_CBFRSYNRA34 (0x488U)
#define SMMU_GNSR1_CBA2R34 (0x888U)
#define SMMU_GNSR1_CBAR35 (0x8cU)
#define SMMU_GNSR1_CBFRSYNRA35 (0x48cU)
#define SMMU_GNSR1_CBA2R35 (0x88cU)
#define SMMU_GNSR1_CBAR36 (0x90U)
#define SMMU_GNSR1_CBFRSYNRA36 (0x490U)
#define SMMU_GNSR1_CBA2R36 (0x890U)
#define SMMU_GNSR1_CBAR37 (0x94U)
#define SMMU_GNSR1_CBFRSYNRA37 (0x494U)
#define SMMU_GNSR1_CBA2R37 (0x894U)
#define SMMU_GNSR1_CBAR38 (0x98U)
#define SMMU_GNSR1_CBFRSYNRA38 (0x498U)
#define SMMU_GNSR1_CBA2R38 (0x898U)
#define SMMU_GNSR1_CBAR39 (0x9cU)
#define SMMU_GNSR1_CBFRSYNRA39 (0x49cU)
#define SMMU_GNSR1_CBA2R39 (0x89cU)
#define SMMU_GNSR1_CBAR40 (0xa0U)
#define SMMU_GNSR1_CBFRSYNRA40 (0x4a0U)
#define SMMU_GNSR1_CBA2R40 (0x8a0U)
#define SMMU_GNSR1_CBAR41 (0xa4U)
#define SMMU_GNSR1_CBFRSYNRA41 (0x4a4U)
#define SMMU_GNSR1_CBA2R41 (0x8a4U)
#define SMMU_GNSR1_CBAR42 (0xa8U)
#define SMMU_GNSR1_CBFRSYNRA42 (0x4a8U)
#define SMMU_GNSR1_CBA2R42 (0x8a8U)
#define SMMU_GNSR1_CBAR43 (0xacU)
#define SMMU_GNSR1_CBFRSYNRA43 (0x4acU)
#define SMMU_GNSR1_CBA2R43 (0x8acU)
#define SMMU_GNSR1_CBAR44 (0xb0U)
#define SMMU_GNSR1_CBFRSYNRA44 (0x4b0U)
#define SMMU_GNSR1_CBA2R44 (0x8b0U)
#define SMMU_GNSR1_CBAR45 (0xb4U)
#define SMMU_GNSR1_CBFRSYNRA45 (0x4b4U)
#define SMMU_GNSR1_CBA2R45 (0x8b4U)
#define SMMU_GNSR1_CBAR46 (0xb8U)
#define SMMU_GNSR1_CBFRSYNRA46 (0x4b8U)
#define SMMU_GNSR1_CBA2R46 (0x8b8U)
#define SMMU_GNSR1_CBAR47 (0xbcU)
#define SMMU_GNSR1_CBFRSYNRA47 (0x4bcU)
#define SMMU_GNSR1_CBA2R47 (0x8bcU)
#define SMMU_GNSR1_CBAR48 (0xc0U)
#define SMMU_GNSR1_CBFRSYNRA48 (0x4c0U)
#define SMMU_GNSR1_CBA2R48 (0x8c0U)
#define SMMU_GNSR1_CBAR49 (0xc4U)
#define SMMU_GNSR1_CBFRSYNRA49 (0x4c4U)
#define SMMU_GNSR1_CBA2R49 (0x8c4U)
#define SMMU_GNSR1_CBAR50 (0xc8U)
#define SMMU_GNSR1_CBFRSYNRA50 (0x4c8U)
#define SMMU_GNSR1_CBA2R50 (0x8c8U)
#define SMMU_GNSR1_CBAR51 (0xccU)
#define SMMU_GNSR1_CBFRSYNRA51 (0x4ccU)
#define SMMU_GNSR1_CBA2R51 (0x8ccU)
#define SMMU_GNSR1_CBAR52 (0xd0U)
#define SMMU_GNSR1_CBFRSYNRA52 (0x4d0U)
#define SMMU_GNSR1_CBA2R52 (0x8d0U)
#define SMMU_GNSR1_CBAR53 (0xd4U)
#define SMMU_GNSR1_CBFRSYNRA53 (0x4d4U)
#define SMMU_GNSR1_CBA2R53 (0x8d4U)
#define SMMU_GNSR1_CBAR54 (0xd8U)
#define SMMU_GNSR1_CBFRSYNRA54 (0x4d8U)
#define SMMU_GNSR1_CBA2R54 (0x8d8U)
#define SMMU_GNSR1_CBAR55 (0xdcU)
#define SMMU_GNSR1_CBFRSYNRA55 (0x4dcU)
#define SMMU_GNSR1_CBA2R55 (0x8dcU)
#define SMMU_GNSR1_CBAR56 (0xe0U)
#define SMMU_GNSR1_CBFRSYNRA56 (0x4e0U)
#define SMMU_GNSR1_CBA2R56 (0x8e0U)
#define SMMU_GNSR1_CBAR57 (0xe4U)
#define SMMU_GNSR1_CBFRSYNRA57 (0x4e4U)
#define SMMU_GNSR1_CBA2R57 (0x8e4U)
#define SMMU_GNSR1_CBAR58 (0xe8U)
#define SMMU_GNSR1_CBFRSYNRA58 (0x4e8U)
#define SMMU_GNSR1_CBA2R58 (0x8e8U)
#define SMMU_GNSR1_CBAR59 (0xecU)
#define SMMU_GNSR1_CBFRSYNRA59 (0x4ecU)
#define SMMU_GNSR1_CBA2R59 (0x8ecU)
#define SMMU_GNSR1_CBAR60 (0xf0U)
#define SMMU_GNSR1_CBFRSYNRA60 (0x4f0U)
#define SMMU_GNSR1_CBA2R60 (0x8f0U)
#define SMMU_GNSR1_CBAR61 (0xf4U)
#define SMMU_GNSR1_CBFRSYNRA61 (0x4f4U)
#define SMMU_GNSR1_CBA2R61 (0x8f4U)
#define SMMU_GNSR1_CBAR62 (0xf8U)
#define SMMU_GNSR1_CBFRSYNRA62 (0x4f8U)
#define SMMU_GNSR1_CBA2R62 (0x8f8U)
#define SMMU_GNSR1_CBAR63 (0xfcU)
#define SMMU_GNSR1_CBFRSYNRA63 (0x4fcU)
#define SMMU_GNSR1_CBA2R63 (0x8fcU)
/*******************************************************************************
* SMMU Global Secure Aux. Configuration Register
******************************************************************************/
#define SMMU_GSR0_SECURE_ACR 0x10
#define SMMU_GNSR_ACR (SMMU_GSR0_SECURE_ACR + 0x400)
#define SMMU_GSR0_PGSIZE_SHIFT 16
#define SMMU_GSR0_PGSIZE_4K (0 << SMMU_GSR0_PGSIZE_SHIFT)
#define SMMU_GSR0_PGSIZE_64K (1 << SMMU_GSR0_PGSIZE_SHIFT)
#define SMMU_ACR_CACHE_LOCK_ENABLE_BIT (1 << 26)
#define SMMU_GSR0_SECURE_ACR 0x10U
#define SMMU_GNSR_ACR (SMMU_GSR0_SECURE_ACR + 0x400U)
#define SMMU_GSR0_PGSIZE_SHIFT 16U
#define SMMU_GSR0_PGSIZE_4K (0U << SMMU_GSR0_PGSIZE_SHIFT)
#define SMMU_GSR0_PGSIZE_64K (1U << SMMU_GSR0_PGSIZE_SHIFT)
#define SMMU_ACR_CACHE_LOCK_ENABLE_BIT (1U << 26)
/*******************************************************************************
* SMMU Global Aux. Control Register
******************************************************************************/
#define SMMU_CBn_ACTLR_CPRE_BIT (1 << 1)
#define SMMU_CBn_ACTLR_CPRE_BIT (1U << 1)
/*******************************************************************************
* SMMU configuration constants
******************************************************************************/
#define ID1_PAGESIZE (1 << 31)
#define ID1_NUMPAGENDXB_SHIFT 28
#define ID1_NUMPAGENDXB_MASK 7
#define ID1_NUMS2CB_SHIFT 16
#define ID1_NUMS2CB_MASK 0xff
#define ID1_NUMCB_SHIFT 0
#define ID1_NUMCB_MASK 0xff
#define PGSHIFT 16
#define CB_SIZE 0x800000
#define ID1_PAGESIZE (1U << 31)
#define ID1_NUMPAGENDXB_SHIFT 28U
#define ID1_NUMPAGENDXB_MASK 7U
#define ID1_NUMS2CB_SHIFT 16U
#define ID1_NUMS2CB_MASK 0xffU
#define ID1_NUMCB_SHIFT 0U
#define ID1_NUMCB_MASK 0xffU
#define PGSHIFT 16U
#define CB_SIZE 0x800000U
typedef struct smmu_regs {
uint32_t reg;
......@@ -632,19 +632,19 @@ typedef struct smmu_regs {
#define mc_make_sid_override_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \
.val = 0x00000000, \
.val = 0x00000000U, \
}
#define mc_make_sid_security_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(MC_STREAMID_OVERRIDE_CFG_ ## name), \
.val = 0x00000000, \
.val = 0x00000000U, \
}
#define smmu_make_gnsr0_sec_cfg(name) \
{ \
.reg = TEGRA_SMMU0_BASE + SMMU_GNSR0_ ## name, \
.val = 0x00000000, \
.val = 0x00000000U, \
}
/*
......@@ -653,39 +653,39 @@ typedef struct smmu_regs {
*/
#define smmu_make_gnsr0_nsec_cfg(name) \
{ \
.reg = TEGRA_SMMU0_BASE + 0x400 + SMMU_GNSR0_ ## name, \
.val = 0x00000000, \
.reg = TEGRA_SMMU0_BASE + 0x400U + SMMU_GNSR0_ ## name, \
.val = 0x00000000U, \
}
#define smmu_make_gnsr0_smr_cfg(n) \
{ \
.reg = TEGRA_SMMU0_BASE + SMMU_GNSR0_SMR ## n, \
.val = 0x00000000, \
.val = 0x00000000U, \
}
#define smmu_make_gnsr0_s2cr_cfg(n) \
{ \
.reg = TEGRA_SMMU0_BASE + SMMU_GNSR0_S2CR ## n, \
.val = 0x00000000, \
.val = 0x00000000U, \
}
#define smmu_make_gnsr1_cbar_cfg(n) \
{ \
.reg = TEGRA_SMMU0_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBAR ## n, \
.val = 0x00000000, \
.reg = TEGRA_SMMU0_BASE + (1U << PGSHIFT) + SMMU_GNSR1_CBAR ## n, \
.val = 0x00000000U, \
}
#define smmu_make_gnsr1_cba2r_cfg(n) \
{ \
.reg = TEGRA_SMMU0_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBA2R ## n, \
.val = 0x00000000, \
.reg = TEGRA_SMMU0_BASE + (1U << PGSHIFT) + SMMU_GNSR1_CBA2R ## n, \
.val = 0x00000000U, \
}
#define make_smmu_cb_cfg(name, n) \
{ \
.reg = TEGRA_SMMU0_BASE + (CB_SIZE >> 1) + (n * (1 << PGSHIFT)) \
+ SMMU_CBn_ ## name, \
.val = 0x00000000, \
.val = 0x00000000U, \
}
#define smmu_make_smrg_group(n) \
......@@ -709,19 +709,19 @@ typedef struct smmu_regs {
#define smmu_bypass_cfg \
{ \
.reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \
.val = 0x00000000, \
.val = 0x00000000U, \
}
#define _START_OF_TABLE_ \
{ \
.reg = 0xCAFE05C7, \
.val = 0x00000000, \
.reg = 0xCAFE05C7U, \
.val = 0x00000000U, \
}
#define _END_OF_TABLE_ \
{ \
.reg = 0xFFFFFFFF, \
.val = 0xFFFFFFFF, \
.reg = 0xFFFFFFFFU, \
.val = 0xFFFFFFFFU, \
}
......
plat/nvidia/tegra/include/tegra_private.h
View file @ 50e91633
/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -39,8 +39,8 @@
/*******************************************************************************
* Tegra DRAM memory base address
******************************************************************************/
#define TEGRA_DRAM_BASE 0x80000000
#define TEGRA_DRAM_END 0x27FFFFFFF
#define TEGRA_DRAM_BASE 0x80000000ULL
#define TEGRA_DRAM_END 0x27FFFFFFFULL
/*******************************************************************************
* Struct for parameters received from BL2
......
plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h
View file @ 50e91633
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -38,46 +38,46 @@
* Macros to prepare CSTATE info request
******************************************************************************/
/* Description of the parameters for UPDATE_CSTATE_INFO request */
#define CLUSTER_CSTATE_MASK 0x7
#define CLUSTER_CSTATE_SHIFT 0
#define CLUSTER_CSTATE_UPDATE_BIT (1 << 7)
#define CCPLEX_CSTATE_MASK 0x3
#define CCPLEX_CSTATE_SHIFT 8
#define CCPLEX_CSTATE_UPDATE_BIT (1 << 15)
#define SYSTEM_CSTATE_MASK 0xF
#define SYSTEM_CSTATE_SHIFT 16
#define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT 22
#define SYSTEM_CSTATE_FORCE_UPDATE_BIT (1 << 22)
#define SYSTEM_CSTATE_UPDATE_BIT (1 << 23)
#define CSTATE_WAKE_MASK_UPDATE_BIT (1 << 31)
#define CSTATE_WAKE_MASK_SHIFT 32
#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFF
#define CLUSTER_CSTATE_MASK 0x7ULL
#define CLUSTER_CSTATE_SHIFT 0U
#define CLUSTER_CSTATE_UPDATE_BIT (1ULL << 7)
#define CCPLEX_CSTATE_MASK 0x3ULL
#define CCPLEX_CSTATE_SHIFT 8ULL
#define CCPLEX_CSTATE_UPDATE_BIT (1ULL << 15)
#define SYSTEM_CSTATE_MASK 0xFULL
#define SYSTEM_CSTATE_SHIFT 16ULL
#define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT 22ULL
#define SYSTEM_CSTATE_FORCE_UPDATE_BIT (1ULL << 22)
#define SYSTEM_CSTATE_UPDATE_BIT (1ULL << 23)
#define CSTATE_WAKE_MASK_UPDATE_BIT (1ULL << 31)
#define CSTATE_WAKE_MASK_SHIFT 32ULL
#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFU
/*******************************************************************************
* Auto-CC3 control macros
******************************************************************************/
#define MCE_AUTO_CC3_FREQ_MASK 0x1FF
#define MCE_AUTO_CC3_FREQ_SHIFT 0
#define MCE_AUTO_CC3_VTG_MASK 0x7F
#define MCE_AUTO_CC3_VTG_SHIFT 16
#define MCE_AUTO_CC3_ENABLE_BIT (1 << 31)
#define MCE_AUTO_CC3_FREQ_MASK 0x1FFU
#define MCE_AUTO_CC3_FREQ_SHIFT 0U
#define MCE_AUTO_CC3_VTG_MASK 0x7FU
#define MCE_AUTO_CC3_VTG_SHIFT 16U
#define MCE_AUTO_CC3_ENABLE_BIT (1U << 31)
/*******************************************************************************
* Macros for the 'IS_SC7_ALLOWED' command
******************************************************************************/
#define MCE_SC7_ALLOWED_MASK 0x7
#define MCE_SC7_WAKE_TIME_SHIFT 32
#define MCE_SC7_ALLOWED_MASK 0x7U
#define MCE_SC7_WAKE_TIME_SHIFT 32U
/*******************************************************************************
* Macros for 'read/write ctats' commands
******************************************************************************/
#define MCE_CSTATE_STATS_TYPE_SHIFT 32
#define MCE_CSTATE_WRITE_DATA_LO_MASK 0xF
#define MCE_CSTATE_STATS_TYPE_SHIFT 32ULL
#define MCE_CSTATE_WRITE_DATA_LO_MASK 0xFU
/*******************************************************************************
* Macros for 'update crossover threshold' command
******************************************************************************/
#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32
#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32U
/*******************************************************************************
* MCA command struct
......@@ -150,15 +150,15 @@ typedef union uncore_perfmon_req {
uint64_t data;
} uncore_perfmon_req_t;
#define UNCORE_PERFMON_CMD_READ 0
#define UNCORE_PERFMON_CMD_WRITE 1
#define UNCORE_PERFMON_CMD_READ 0U
#define UNCORE_PERFMON_CMD_WRITE 1U
#define UNCORE_PERFMON_CMD_MASK 0xFF
#define UNCORE_PERFMON_UNIT_GRP_MASK 0xF
#define UNCORE_PERFMON_SELECTOR_MASK 0xF
#define UNCORE_PERFMON_REG_MASK 0xFF
#define UNCORE_PERFMON_CTR_MASK 0xFF
#define UNCORE_PERFMON_RESP_STATUS_MASK 0xFF
#define UNCORE_PERFMON_CMD_MASK 0xFFU
#define UNCORE_PERFMON_UNIT_GRP_MASK 0xFU
#define UNCORE_PERFMON_SELECTOR_MASK 0xFU
#define UNCORE_PERFMON_REG_MASK 0xFFU
#define UNCORE_PERFMON_CTR_MASK 0xFFU
#define UNCORE_PERFMON_RESP_STATUS_MASK 0xFFU
/*******************************************************************************
* Structure populated by arch specific code to export routines which perform
......
plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h
View file @ 50e91633
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -40,103 +40,103 @@
*/
enum {
TEGRA_ARI_VERSION_MAJOR = 3,
TEGRA_ARI_VERSION_MINOR = 1,
TEGRA_ARI_VERSION_MAJOR = 3U,
TEGRA_ARI_VERSION_MINOR = 1U,
};
typedef enum {
/* indexes below get the core lock */
TEGRA_ARI_MISC = 0,
TEGRA_ARI_MISC = 0U,
/* index 1 is deprecated */
/* index 2 is deprecated */
/* index 3 is deprecated */
TEGRA_ARI_ONLINE_CORE = 4,
TEGRA_ARI_ONLINE_CORE = 4U,
/* indexes below need cluster lock */
TEGRA_ARI_MISC_CLUSTER = 41,
TEGRA_ARI_IS_CCX_ALLOWED = 42,
TEGRA_ARI_CC3_CTRL = 43,
TEGRA_ARI_MISC_CLUSTER = 41U,
TEGRA_ARI_IS_CCX_ALLOWED = 42U,
TEGRA_ARI_CC3_CTRL = 43U,
/* indexes below need ccplex lock */
TEGRA_ARI_ENTER_CSTATE = 80,
TEGRA_ARI_UPDATE_CSTATE_INFO = 81,
TEGRA_ARI_IS_SC7_ALLOWED = 82,
TEGRA_ARI_ENTER_CSTATE = 80U,
TEGRA_ARI_UPDATE_CSTATE_INFO = 81U,
TEGRA_ARI_IS_SC7_ALLOWED = 82U,
/* index 83 is deprecated */
TEGRA_ARI_PERFMON = 84,
TEGRA_ARI_UPDATE_CCPLEX_GSC = 85,
TEGRA_ARI_PERFMON = 84U,
TEGRA_ARI_UPDATE_CCPLEX_GSC = 85U,
/* index 86 is depracated */
/* index 87 is deprecated */
TEGRA_ARI_ROC_FLUSH_CACHE_ONLY = 88,
TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS = 89,
TEGRA_ARI_MISC_CCPLEX = 90,
TEGRA_ARI_MCA = 91,
TEGRA_ARI_UPDATE_CROSSOVER = 92,
TEGRA_ARI_CSTATE_STATS = 93,
TEGRA_ARI_WRITE_CSTATE_STATS = 94,
TEGRA_ARI_COPY_MISCREG_AA64_RST = 95,
TEGRA_ARI_ROC_CLEAN_CACHE_ONLY = 96,
TEGRA_ARI_ROC_FLUSH_CACHE_ONLY = 88U,
TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS = 89U,
TEGRA_ARI_MISC_CCPLEX = 90U,
TEGRA_ARI_MCA = 91U,
TEGRA_ARI_UPDATE_CROSSOVER = 92U,
TEGRA_ARI_CSTATE_STATS = 93U,
TEGRA_ARI_WRITE_CSTATE_STATS = 94U,
TEGRA_ARI_COPY_MISCREG_AA64_RST = 95U,
TEGRA_ARI_ROC_CLEAN_CACHE_ONLY = 96U,
} tegra_ari_req_id_t;
typedef enum {
TEGRA_ARI_MISC_ECHO = 0,
TEGRA_ARI_MISC_VERSION = 1,
TEGRA_ARI_MISC_FEATURE_LEAF_0 = 2,
TEGRA_ARI_MISC_ECHO = 0U,
TEGRA_ARI_MISC_VERSION = 1U,
TEGRA_ARI_MISC_FEATURE_LEAF_0 = 2U,
} tegra_ari_misc_index_t;
typedef enum {
TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF = 0,
TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT = 1,
TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL = 2,
TEGRA_ARI_MISC_CCPLEX_EDBGREQ = 3,
TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF = 0U,
TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT = 1U,
TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL = 2U,
TEGRA_ARI_MISC_CCPLEX_EDBGREQ = 3U,
} tegra_ari_misc_ccplex_index_t;
typedef enum {
TEGRA_ARI_CORE_C0 = 0,
TEGRA_ARI_CORE_C1 = 1,
TEGRA_ARI_CORE_C6 = 6,
TEGRA_ARI_CORE_C7 = 7,
TEGRA_ARI_CORE_WARMRSTREQ = 8,
TEGRA_ARI_CORE_C0 = 0U,
TEGRA_ARI_CORE_C1 = 1U,
TEGRA_ARI_CORE_C6 = 6U,
TEGRA_ARI_CORE_C7 = 7U,
TEGRA_ARI_CORE_WARMRSTREQ = 8U,
} tegra_ari_core_sleep_state_t;
typedef enum {
TEGRA_ARI_CLUSTER_CC0 = 0,
TEGRA_ARI_CLUSTER_CC1 = 1,
TEGRA_ARI_CLUSTER_CC6 = 6,
TEGRA_ARI_CLUSTER_CC7 = 7,
TEGRA_ARI_CLUSTER_CC0 = 0U,
TEGRA_ARI_CLUSTER_CC1 = 1U,
TEGRA_ARI_CLUSTER_CC6 = 6U,
TEGRA_ARI_CLUSTER_CC7 = 7U,
} tegra_ari_cluster_sleep_state_t;
typedef enum {
TEGRA_ARI_CCPLEX_CCP0 = 0,
TEGRA_ARI_CCPLEX_CCP1 = 1,
TEGRA_ARI_CCPLEX_CCP3 = 3, /* obsoleted */
TEGRA_ARI_CCPLEX_CCP0 = 0U,
TEGRA_ARI_CCPLEX_CCP1 = 1U,
TEGRA_ARI_CCPLEX_CCP3 = 3U, /* obsoleted */
} tegra_ari_ccplex_sleep_state_t;
typedef enum {
TEGRA_ARI_SYSTEM_SC0 = 0,
TEGRA_ARI_SYSTEM_SC1 = 1, /* obsoleted */
TEGRA_ARI_SYSTEM_SC2 = 2, /* obsoleted */
TEGRA_ARI_SYSTEM_SC3 = 3, /* obsoleted */
TEGRA_ARI_SYSTEM_SC4 = 4, /* obsoleted */
TEGRA_ARI_SYSTEM_SC7 = 7,
TEGRA_ARI_SYSTEM_SC8 = 8,
TEGRA_ARI_SYSTEM_SC0 = 0U,
TEGRA_ARI_SYSTEM_SC1 = 1U, /* obsoleted */
TEGRA_ARI_SYSTEM_SC2 = 2U, /* obsoleted */
TEGRA_ARI_SYSTEM_SC3 = 3U, /* obsoleted */
TEGRA_ARI_SYSTEM_SC4 = 4U, /* obsoleted */
TEGRA_ARI_SYSTEM_SC7 = 7U,
TEGRA_ARI_SYSTEM_SC8 = 8U,
} tegra_ari_system_sleep_state_t;
typedef enum {
TEGRA_ARI_CROSSOVER_C1_C6 = 0,
TEGRA_ARI_CROSSOVER_CC1_CC6 = 1,
TEGRA_ARI_CROSSOVER_CC1_CC7 = 2,
TEGRA_ARI_CROSSOVER_CCP1_CCP3 = 3, /* obsoleted */
TEGRA_ARI_CROSSOVER_CCP3_SC2 = 4, /* obsoleted */
TEGRA_ARI_CROSSOVER_CCP3_SC3 = 5, /* obsoleted */
TEGRA_ARI_CROSSOVER_CCP3_SC4 = 6, /* obsoleted */
TEGRA_ARI_CROSSOVER_CCP3_SC7 = 7, /* obsoleted */
TEGRA_ARI_CROSSOVER_SC0_SC7 = 7,
TEGRA_ARI_CROSSOVER_CCP3_SC1 = 8, /* obsoleted */
TEGRA_ARI_CROSSOVER_C1_C6 = 0U,
TEGRA_ARI_CROSSOVER_CC1_CC6 = 1U,
TEGRA_ARI_CROSSOVER_CC1_CC7 = 2U,
TEGRA_ARI_CROSSOVER_CCP1_CCP3 = 3U, /* obsoleted */
TEGRA_ARI_CROSSOVER_CCP3_SC2 = 4U, /* obsoleted */
TEGRA_ARI_CROSSOVER_CCP3_SC3 = 5U, /* obsoleted */
TEGRA_ARI_CROSSOVER_CCP3_SC4 = 6U, /* obsoleted */
TEGRA_ARI_CROSSOVER_CCP3_SC7 = 7U, /* obsoleted */
TEGRA_ARI_CROSSOVER_SC0_SC7 = 7U,
TEGRA_ARI_CROSSOVER_CCP3_SC1 = 8U, /* obsoleted */
} tegra_ari_crossover_index_t;
typedef enum {
TEGRA_ARI_CSTATE_STATS_CLEAR = 0,
TEGRA_ARI_CSTATE_STATS_SC7_ENTRIES,
TEGRA_ARI_CSTATE_STATS_CLEAR = 0U,
TEGRA_ARI_CSTATE_STATS_SC7_ENTRIES = 1U,
TEGRA_ARI_CSTATE_STATS_SC4_ENTRIES, /* obsoleted */
TEGRA_ARI_CSTATE_STATS_SC3_ENTRIES, /* obsoleted */
TEGRA_ARI_CSTATE_STATS_SC2_ENTRIES, /* obsoleted */
......@@ -147,316 +147,314 @@ typedef enum {
TEGRA_ARI_CSTATE_STATS_D15_CC7_ENTRIES,
TEGRA_ARI_CSTATE_STATS_D15_0_C6_ENTRIES,
TEGRA_ARI_CSTATE_STATS_D15_1_C6_ENTRIES,
TEGRA_ARI_CSTATE_STATS_D15_0_C7_ENTRIES = 14,
TEGRA_ARI_CSTATE_STATS_D15_0_C7_ENTRIES = 14U,
TEGRA_ARI_CSTATE_STATS_D15_1_C7_ENTRIES,
TEGRA_ARI_CSTATE_STATS_A57_0_C7_ENTRIES = 18,
TEGRA_ARI_CSTATE_STATS_A57_0_C7_ENTRIES = 18U,
TEGRA_ARI_CSTATE_STATS_A57_1_C7_ENTRIES,
TEGRA_ARI_CSTATE_STATS_A57_2_C7_ENTRIES,
TEGRA_ARI_CSTATE_STATS_A57_3_C7_ENTRIES,
TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_0,
TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_1,
TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 26,
TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 26U,
TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_1,
TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_2,
TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_3,
} tegra_ari_cstate_stats_index_t;
typedef enum {
TEGRA_ARI_GSC_ALL = 0,
TEGRA_ARI_GSC_BPMP = 6,
TEGRA_ARI_GSC_APE = 7,
TEGRA_ARI_GSC_SPE = 8,
TEGRA_ARI_GSC_SCE = 9,
TEGRA_ARI_GSC_APR = 10,
TEGRA_ARI_GSC_TZRAM = 11,
TEGRA_ARI_GSC_SE = 12,
TEGRA_ARI_GSC_BPMP_TO_SPE = 16,
TEGRA_ARI_GSC_SPE_TO_BPMP = 17,
TEGRA_ARI_GSC_CPU_TZ_TO_BPMP = 18,
TEGRA_ARI_GSC_BPMP_TO_CPU_TZ = 19,
TEGRA_ARI_GSC_CPU_NS_TO_BPMP = 20,
TEGRA_ARI_GSC_BPMP_TO_CPU_NS = 21,
TEGRA_ARI_GSC_IPC_SE_SPE_SCE_BPMP = 22,
TEGRA_ARI_GSC_SC7_RESUME_FW = 23,
TEGRA_ARI_GSC_TZ_DRAM_IDX = 34,
TEGRA_ARI_GSC_VPR_IDX = 35,
TEGRA_ARI_GSC_ALL = 0U,
TEGRA_ARI_GSC_BPMP = 6U,
TEGRA_ARI_GSC_APE = 7U,
TEGRA_ARI_GSC_SPE = 8U,
TEGRA_ARI_GSC_SCE = 9U,
TEGRA_ARI_GSC_APR = 10U,
TEGRA_ARI_GSC_TZRAM = 11U,
TEGRA_ARI_GSC_SE = 12U,
TEGRA_ARI_GSC_BPMP_TO_SPE = 16U,
TEGRA_ARI_GSC_SPE_TO_BPMP = 17U,
TEGRA_ARI_GSC_CPU_TZ_TO_BPMP = 18U,
TEGRA_ARI_GSC_BPMP_TO_CPU_TZ = 19U,
TEGRA_ARI_GSC_CPU_NS_TO_BPMP = 20U,
TEGRA_ARI_GSC_BPMP_TO_CPU_NS = 21U,
TEGRA_ARI_GSC_IPC_SE_SPE_SCE_BPMP = 22U,
TEGRA_ARI_GSC_SC7_RESUME_FW = 23U,
TEGRA_ARI_GSC_TZ_DRAM_IDX = 34U,
TEGRA_ARI_GSC_VPR_IDX = 35U,
} tegra_ari_gsc_index_t;
/* This macro will produce enums for __name##_LSB, __name##_MSB and __name##_MSK */
#define TEGRA_ARI_ENUM_MASK_LSB_MSB(__name, __lsb, __msb) __name##_LSB = __lsb, __name##_MSB = __msb
typedef enum {
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CLUSTER_CSTATE, 0, 2),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CLUSTER_CSTATE_PRESENT, 7, 7),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CCPLEX_CSTATE, 8, 9),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CCPLEX_CSTATE_PRESENT, 15, 15),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__SYSTEM_CSTATE, 16, 19),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__IGNORE_CROSSOVERS, 22, 22),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__SYSTEM_CSTATE_PRESENT, 23, 23),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__WAKE_MASK_PRESENT, 31, 31),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CLUSTER_CSTATE, 0U, 2U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CLUSTER_CSTATE_PRESENT, 7U, 7U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CCPLEX_CSTATE, 8U, 9U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CCPLEX_CSTATE_PRESENT, 15U, 15U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__SYSTEM_CSTATE, 16U, 19U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__IGNORE_CROSSOVERS, 22U, 22U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__SYSTEM_CSTATE_PRESENT, 23U, 23U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__WAKE_MASK_PRESENT, 31U, 31U),
} tegra_ari_update_cstate_info_bitmasks_t;
typedef enum {
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL__EN, 0, 0),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL__EN, 0U, 0U),
} tegra_ari_misc_ccplex_bitmasks_t;
typedef enum {
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__IDLE_FREQ, 0, 8),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__IDLE_VOLT, 16, 23),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__ENABLE, 31, 31),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__IDLE_FREQ, 0U, 8U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__IDLE_VOLT, 16U, 23U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__ENABLE, 31U, 31U),
} tegra_ari_cc3_ctrl_bitmasks_t;
typedef enum {
TEGRA_ARI_MCA_NOP = 0,
TEGRA_ARI_MCA_READ_SERR = 1,
TEGRA_ARI_MCA_WRITE_SERR = 2,
TEGRA_ARI_MCA_CLEAR_SERR = 4,
TEGRA_ARI_MCA_REPORT_SERR = 5,
TEGRA_ARI_MCA_READ_INTSTS = 6,
TEGRA_ARI_MCA_WRITE_INTSTS = 7,
TEGRA_ARI_MCA_READ_PREBOOT_SERR = 8,
TEGRA_ARI_MCA_NOP = 0U,
TEGRA_ARI_MCA_READ_SERR = 1U,
TEGRA_ARI_MCA_WRITE_SERR = 2U,
TEGRA_ARI_MCA_CLEAR_SERR = 4U,
TEGRA_ARI_MCA_REPORT_SERR = 5U,
TEGRA_ARI_MCA_READ_INTSTS = 6U,
TEGRA_ARI_MCA_WRITE_INTSTS = 7U,
TEGRA_ARI_MCA_READ_PREBOOT_SERR = 8U,
} tegra_ari_mca_commands_t;
typedef enum {
TEGRA_ARI_MCA_RD_WR_DPMU = 0,
TEGRA_ARI_MCA_RD_WR_IOB = 1,
TEGRA_ARI_MCA_RD_WR_MCB = 2,
TEGRA_ARI_MCA_RD_WR_CCE = 3,
TEGRA_ARI_MCA_RD_WR_CQX = 4,
TEGRA_ARI_MCA_RD_WR_CTU = 5,
TEGRA_ARI_MCA_RD_WR_JSR_MTS = 7,
TEGRA_ARI_MCA_RD_BANK_INFO = 0x0f,
TEGRA_ARI_MCA_RD_BANK_TEMPLATE = 0x10,
TEGRA_ARI_MCA_RD_WR_SECURE_ACCESS_REGISTER = 0x11,
TEGRA_ARI_MCA_RD_WR_GLOBAL_CONFIG_REGISTER = 0x12,
TEGRA_ARI_MCA_RD_WR_DPMU = 0U,
TEGRA_ARI_MCA_RD_WR_IOB = 1U,
TEGRA_ARI_MCA_RD_WR_MCB = 2U,
TEGRA_ARI_MCA_RD_WR_CCE = 3U,
TEGRA_ARI_MCA_RD_WR_CQX = 4U,
TEGRA_ARI_MCA_RD_WR_CTU = 5U,
TEGRA_ARI_MCA_RD_WR_JSR_MTS = 7U,
TEGRA_ARI_MCA_RD_BANK_INFO = 0x0fU,
TEGRA_ARI_MCA_RD_BANK_TEMPLATE = 0x10U,
TEGRA_ARI_MCA_RD_WR_SECURE_ACCESS_REGISTER = 0x11U,
TEGRA_ARI_MCA_RD_WR_GLOBAL_CONFIG_REGISTER = 0x12U,
} tegra_ari_mca_rd_wr_indexes_t;
typedef enum {
TEGRA_ARI_MCA_RD_WR_ASERRX_CTRL = 0,
TEGRA_ARI_MCA_RD_WR_ASERRX_STATUS = 1,
TEGRA_ARI_MCA_RD_WR_ASERRX_ADDR = 2,
TEGRA_ARI_MCA_RD_WR_ASERRX_MISC1 = 3,
TEGRA_ARI_MCA_RD_WR_ASERRX_MISC2 = 4,
TEGRA_ARI_MCA_RD_WR_ASERRX_CTRL = 0U,
TEGRA_ARI_MCA_RD_WR_ASERRX_STATUS = 1U,
TEGRA_ARI_MCA_RD_WR_ASERRX_ADDR = 2U,
TEGRA_ARI_MCA_RD_WR_ASERRX_MISC1 = 3U,
TEGRA_ARI_MCA_RD_WR_ASERRX_MISC2 = 4U,
} tegra_ari_mca_read_asserx_subindexes_t;
typedef enum {
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_SETTING_ENABLES_NS_PERMITTED, 0, 0),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_READING_STATUS_NS_PERMITTED, 1, 1),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_PENDING_MCA_ERRORS_NS_PERMITTED, 2, 2),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_CLEARING_MCA_INTERRUPTS_NS_PERMITTED, 3, 3),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_SETTING_ENABLES_NS_PERMITTED, 0U, 0U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_READING_STATUS_NS_PERMITTED, 1U, 1U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_PENDING_MCA_ERRORS_NS_PERMITTED, 2U, 2U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_CLEARING_MCA_INTERRUPTS_NS_PERMITTED, 3U, 3U),
} tegra_ari_mca_secure_register_bitmasks_t;
typedef enum {
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_SERR_ERR_CODE, 0, 15),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_PWM_ERR, 16, 16),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_CRAB_ERR, 17, 17),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_RD_WR_N, 18, 18),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_UCODE_ERR, 19, 19),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_PWM, 20, 23),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_AV, 58, 58),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_MV, 59, 59),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_EN, 60, 60),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_UC, 61, 61),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_OVF, 62, 62),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_VAL, 63, 63),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_ADDR_ADDR, 0, 41),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_ADDR_UCODE_ERRCD, 42, 52),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_PWM_ERR, 0, 0),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_CRAB_ERR, 1, 1),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_UCODE_ERR, 3, 3),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_SERR_ERR_CODE, 0U, 15U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_PWM_ERR, 16U, 16U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_CRAB_ERR, 17U, 17U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_RD_WR_N, 18U, 18U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_UCODE_ERR, 19U, 19U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_PWM, 20U, 23U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_AV, 58U, 58U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_MV, 59U, 59U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_EN, 60U, 60U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_UC, 61U, 61U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_OVF, 62U, 62U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_VAL, 63U, 63U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_ADDR_ADDR, 0U, 41U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_ADDR_UCODE_ERRCD, 42U, 52U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_PWM_ERR, 0U, 0U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_CRAB_ERR, 1U, 1U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_UCODE_ERR, 3U, 3U),
} tegra_ari_mca_aserr0_bitmasks_t;
typedef enum {
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_SERR_ERR_CODE, 0, 15),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MSI_ERR, 16, 16),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_IHI_ERR, 17, 17),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CRI_ERR, 18, 18),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MMCRAB_ERR, 19, 19),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CSI_ERR, 20, 20),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_RD_WR_N, 21, 21),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_REQ_ERRT, 22, 23),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_RESP_ERRT, 24, 25),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_AV, 58, 58),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MV, 59, 59),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_EN, 60, 60),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_UC, 61, 61),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_OVF, 62, 62),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_VAL, 63, 63),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_AXI_ID, 0, 7),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_ID, 8, 27),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_CID, 28, 31),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_CMD, 32, 35),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_MSI_ERR, 0, 0),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_IHI_ERR, 1, 1),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_CRI_ERR, 2, 2),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_MMCRAB_ERR, 3, 3),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_CSI_ERR, 4, 4),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_MISC_ADDR, 0, 41),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_SERR_ERR_CODE, 0U, 15U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MSI_ERR, 16U, 16U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_IHI_ERR, 17U, 17U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CRI_ERR, 18U, 18U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MMCRAB_ERR, 19U, 19U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CSI_ERR, 20U, 20U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_RD_WR_N, 21U, 21U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_REQ_ERRT, 22U, 23U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_RESP_ERRT, 24U, 25U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_AV, 58U, 58U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MV, 59U, 59U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_EN, 60U, 60U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_UC, 61U, 61U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_OVF, 62U, 62U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_VAL, 63U, 63U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_AXI_ID, 0U, 7U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_ID, 8U, 27U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_CID, 28U, 31U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_CMD, 32U, 35U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_MSI_ERR, 0U, 0U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_IHI_ERR, 1U, 1U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_CRI_ERR, 2U, 2U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_MMCRAB_ERR, 3U, 3U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_CSI_ERR, 4U, 4U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_MISC_ADDR, 0U, 41U),
} tegra_ari_mca_aserr1_bitmasks_t;
typedef enum {
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_SERR_ERR_CODE, 0, 15),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_MC_ERR, 16, 16),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_SYSRAM_ERR, 17, 17),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_CLIENT_ID, 18, 19),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_AV, 58, 58),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_MV, 59, 59),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_EN, 60, 60),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_UC, 61, 61),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_OVF, 62, 62),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_VAL, 63, 63),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_ID, 0, 17),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_CMD, 18, 21),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_ADDR, 22, 53),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_CTRL_EN_MC_ERR, 0, 0),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_SERR_ERR_CODE, 0U, 15U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_MC_ERR, 16U, 16U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_SYSRAM_ERR, 17U, 17U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_CLIENT_ID, 18U, 19U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_AV, 58U, 58U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_MV, 59U, 59U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_EN, 60U, 60U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_UC, 61U, 61U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_OVF, 62U, 62U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_VAL, 63U, 63U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_ID, 0U, 17U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_CMD, 18U, 21U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_ADDR, 22U, 53U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_CTRL_EN_MC_ERR, 0U, 0U),
} tegra_ari_mca_aserr2_bitmasks_t;
typedef enum {
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_SERR_ERR_CODE, 0, 15),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_TO_ERR, 16, 16),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_STAT_ERR, 17, 17),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_DST_ERR, 18, 18),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_UNC_ERR, 19, 19),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_MH_ERR, 20, 20),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_PERR, 21, 21),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_PSN_ERR, 22, 22),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_AV, 58, 58),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_MV, 59, 59),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_EN, 60, 60),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_UC, 61, 61),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_OVF, 62, 62),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_VAL, 63, 63),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_ADDR_CMD, 0, 5),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_ADDR_ADDR, 6, 47),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_TO, 0, 0),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_DIV4, 1, 1),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_TLIMIT, 2, 11),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_PSN_ERR_CORR_MSK, 12, 25),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_MORE_INFO, 0, 17),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_TO_INFO, 18, 43),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_SRC, 44, 45),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_TID, 46, 52),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_TO_ERR, 0, 0),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_STAT_ERR, 1, 1),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_DST_ERR, 2, 2),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_UNC_ERR, 3, 3),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_MH_ERR, 4, 4),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_PERR, 5, 5),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_PSN_ERR, 6, 19),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_SERR_ERR_CODE, 0U, 15U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_TO_ERR, 16U, 16U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_STAT_ERR, 17U, 17U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_DST_ERR, 18U, 18U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_UNC_ERR, 19U, 19U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_MH_ERR, 20U, 20U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_PERR, 21U, 21U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_PSN_ERR, 22U, 22U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_AV, 58U, 58U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_MV, 59U, 59U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_EN, 60U, 60U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_UC, 61U, 61U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_OVF, 62U, 62U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_VAL, 63U, 63U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_ADDR_CMD, 0U, 5U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_ADDR_ADDR, 6U, 47U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_TO, 0U, 0U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_DIV4, 1U, 1U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_TLIMIT, 2U, 11U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_PSN_ERR_CORR_MSK, 12U, 25U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_MORE_INFO, 0U, 17U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_TO_INFO, 18U, 43U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_SRC, 44U, 45U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_TID, 46U, 52U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_TO_ERR, 0U, 0U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_STAT_ERR, 1U, 1U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_DST_ERR, 2U, 2U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_UNC_ERR, 3U, 3U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_MH_ERR, 4U, 4U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_PERR, 5U, 5U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_PSN_ERR, 6U, 19U),
} tegra_ari_mca_aserr3_bitmasks_t;
typedef enum {
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_SERR_ERR_CODE, 0, 15),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_SRC_ERR, 16, 16),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_DST_ERR, 17, 17),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_REQ_ERR, 18, 18),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_RSP_ERR, 19, 19),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_AV, 58, 58),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_MV, 59, 59),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_EN, 60, 60),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_UC, 61, 61),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_OVF, 62, 62),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_VAL, 63, 63),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_CTRL_EN_CPE_ERR, 0, 0),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_SERR_ERR_CODE, 0U, 15U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_SRC_ERR, 16U, 16U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_DST_ERR, 17U, 17U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_REQ_ERR, 18U, 18U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_RSP_ERR, 19U, 19U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_AV, 58U, 58U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_MV, 59U, 59U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_EN, 60U, 60U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_UC, 61U, 61U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_OVF, 62U, 62U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_VAL, 63U, 63U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_CTRL_EN_CPE_ERR, 0U, 0U),
} tegra_ari_mca_aserr4_bitmasks_t;
typedef enum {
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_SERR_ERR_CODE, 0, 15),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_CTUPAR, 16, 16),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_MULTI, 17, 17),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_AV, 58, 58),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_MV, 59, 59),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_EN, 60, 60),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_UC, 61, 61),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_OVF, 62, 62),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_VAL, 63, 63),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_SRC, 0, 7),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_ID, 8, 15),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_DATA, 16, 26),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_CMD, 32, 35),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_ADDR, 36, 45),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_CTRL_EN_CTUPAR, 0, 0),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_SERR_ERR_CODE, 0U, 15U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_CTUPAR, 16U, 16U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_MULTI, 17U, 17U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_AV, 58U, 58U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_MV, 59U, 59U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_EN, 60U, 60U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_UC, 61U, 61U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_OVF, 62U, 62U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_VAL, 63U, 63U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_SRC, 0U, 7U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_ID, 8U, 15U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_DATA, 16U, 26U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_CMD, 32U, 35U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_ADDR, 36U, 45U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_CTRL_EN_CTUPAR, 0U, 0U),
} tegra_ari_mca_aserr5_bitmasks_t;
typedef enum {
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_SERR_ERR_CODE, 0, 15),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_AV, 58, 58),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_MV, 59, 59),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_EN, 60, 60),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_UC, 61, 61),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_OVF, 62, 62),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_VAL, 63, 63),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_ADDR_TBD_INFO, 0, 63),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_SERR_ERR_CODE, 0U, 15U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_AV, 58U, 58U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_MV, 59U, 59U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_EN, 60U, 60U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_UC, 61U, 61U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_OVF, 62U, 62U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_VAL, 63U, 63U),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_ADDR_TBD_INFO, 0U, 63U),
} tegra_ari_mca_serr1_bitmasks_t;
#undef TEGRA_ARI_ENUM_MASK_LSB_MSB
typedef enum {
TEGRA_NVG_CHANNEL_PMIC = 0,
TEGRA_NVG_CHANNEL_POWER_PERF = 1,
TEGRA_NVG_CHANNEL_POWER_MODES = 2,
TEGRA_NVG_CHANNEL_WAKE_TIME = 3,
TEGRA_NVG_CHANNEL_CSTATE_INFO = 4,
TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 = 5,
TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC6 = 6,
TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC7 = 7,
TEGRA_NVG_CHANNEL_CROSSOVER_CCP1_CCP3 = 8, /* obsoleted */
TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC2 = 9, /* obsoleted */
TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC3 = 10, /* obsoleted */
TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC4 = 11, /* obsoleted */
TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC7 = 12, /* obsoleted */
TEGRA_NVG_CHANNEL_CROSSOVER_SC0_SC7 = 12,
TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR = 13,
TEGRA_NVG_CHANNEL_CSTATE_STATS_SC7_ENTRIES = 14,
TEGRA_NVG_CHANNEL_CSTATE_STATS_SC4_ENTRIES = 15, /* obsoleted */
TEGRA_NVG_CHANNEL_CSTATE_STATS_SC3_ENTRIES = 16, /* obsoleted */
TEGRA_NVG_CHANNEL_CSTATE_STATS_SC2_ENTRIES = 17, /* obsoleted */
TEGRA_NVG_CHANNEL_CSTATE_STATS_CCP3_ENTRIES = 18, /* obsoleted */
TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC6_ENTRIES = 19,
TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC7_ENTRIES = 20,
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC6_ENTRIES = 21,
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC7_ENTRIES = 22,
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_0_C6_ENTRIES = 23,
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_1_C6_ENTRIES = 24,
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_2_C6_ENTRIES = 25, /* Reserved (for Denver15 core 2) */
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_3_C6_ENTRIES = 26, /* Reserved (for Denver15 core 3) */
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_0_C7_ENTRIES = 27,
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_1_C7_ENTRIES = 28,
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_2_C7_ENTRIES = 29, /* Reserved (for Denver15 core 2) */
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_3_C7_ENTRIES = 30, /* Reserved (for Denver15 core 3) */
TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_0_C7_ENTRIES = 31,
TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_1_C7_ENTRIES = 32,
TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_2_C7_ENTRIES = 33,
TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_3_C7_ENTRIES = 34,
TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_0 = 35,
TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_1 = 36,
TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_2 = 37, /* Reserved (for Denver15 core 2) */
TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_3 = 38, /* Reserved (for Denver15 core 3) */
TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 39,
TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_1 = 40,
TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_2 = 41,
TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_3 = 42,
TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43,
TEGRA_NVG_CHANNEL_ONLINE_CORE = 44,
TEGRA_NVG_CHANNEL_CC3_CTRL = 45,
TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC1 = 46, /* obsoleted */
TEGRA_NVG_CHANNEL_PMIC = 0U,
TEGRA_NVG_CHANNEL_POWER_PERF = 1U,
TEGRA_NVG_CHANNEL_POWER_MODES = 2U,
TEGRA_NVG_CHANNEL_WAKE_TIME = 3U,
TEGRA_NVG_CHANNEL_CSTATE_INFO = 4U,
TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 = 5U,
TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC6 = 6U,
TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC7 = 7U,
TEGRA_NVG_CHANNEL_CROSSOVER_CCP1_CCP3 = 8U, /* obsoleted */
TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC2 = 9U, /* obsoleted */
TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC3 = 10U, /* obsoleted */
TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC4 = 11U, /* obsoleted */
TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC7 = 12U, /* obsoleted */
TEGRA_NVG_CHANNEL_CROSSOVER_SC0_SC7 = 12U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR = 13U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_SC7_ENTRIES = 14U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_SC4_ENTRIES = 15U, /* obsoleted */
TEGRA_NVG_CHANNEL_CSTATE_STATS_SC3_ENTRIES = 16U, /* obsoleted */
TEGRA_NVG_CHANNEL_CSTATE_STATS_SC2_ENTRIES = 17U, /* obsoleted */
TEGRA_NVG_CHANNEL_CSTATE_STATS_CCP3_ENTRIES = 18U, /* obsoleted */
TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC6_ENTRIES = 19U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC7_ENTRIES = 20U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC6_ENTRIES = 21U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC7_ENTRIES = 22U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_0_C6_ENTRIES = 23U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_1_C6_ENTRIES = 24U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_2_C6_ENTRIES = 25U, /* Reserved (for Denver15 core 2) */
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_3_C6_ENTRIES = 26U, /* Reserved (for Denver15 core 3) */
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_0_C7_ENTRIES = 27U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_1_C7_ENTRIES = 28U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_2_C7_ENTRIES = 29U, /* Reserved (for Denver15 core 2) */
TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_3_C7_ENTRIES = 30U, /* Reserved (for Denver15 core 3) */
TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_0_C7_ENTRIES = 31U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_1_C7_ENTRIES = 32U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_2_C7_ENTRIES = 33U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_3_C7_ENTRIES = 34U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_0 = 35U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_1 = 36U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_2 = 37U, /* Reserved (for Denver15 core 2) */
TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_3 = 38U, /* Reserved (for Denver15 core 3) */
TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 39U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_1 = 40U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_2 = 41U,
TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_3 = 42U,
TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43U,
TEGRA_NVG_CHANNEL_ONLINE_CORE = 44U,
TEGRA_NVG_CHANNEL_CC3_CTRL = 45U,
TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC1 = 46U, /* obsoleted */
TEGRA_NVG_CHANNEL_LAST_INDEX,
} tegra_nvg_channel_id_t;
......
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