Tegra: fix trivial misra issues

Not having U or ULL as a suffix for these enums causes
a lot of unnecessary MISRA issues. This patch adds U or
ULL suffix to these common enums to reduce number of
MISRA issues.
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

plat/nvidia/tegra/include/drivers/flowctrl.h

 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -34,34 +34,34 @@
 #include <mmio.h>
 #include <tegra_def.h>
 
-#define FLOWCTRL_HALT_CPU0_EVENTS	0x0
-#define  FLOWCTRL_WAITEVENT		(2 << 29)
-#define  FLOWCTRL_WAIT_FOR_INTERRUPT	(4 << 29)
-#define  FLOWCTRL_JTAG_RESUME		(1 << 28)
-#define  FLOWCTRL_HALT_SCLK		(1 << 27)
-#define  FLOWCTRL_HALT_LIC_IRQ		(1 << 11)
-#define  FLOWCTRL_HALT_LIC_FIQ		(1 << 10)
-#define  FLOWCTRL_HALT_GIC_IRQ		(1 << 9)
-#define  FLOWCTRL_HALT_GIC_FIQ		(1 << 8)
-#define FLOWCTRL_HALT_BPMP_EVENTS	0x4
-#define FLOWCTRL_CPU0_CSR		0x8
-#define  FLOW_CTRL_CSR_PWR_OFF_STS	(1 << 16)
-#define  FLOWCTRL_CSR_INTR_FLAG		(1 << 15)
-#define  FLOWCTRL_CSR_EVENT_FLAG	(1 << 14)
-#define  FLOWCTRL_CSR_IMMEDIATE_WAKE	(1 << 3)
-#define  FLOWCTRL_CSR_ENABLE		(1 << 0)
-#define FLOWCTRL_HALT_CPU1_EVENTS	0x14
-#define FLOWCTRL_CPU1_CSR		0x18
-#define FLOWCTRL_CC4_CORE0_CTRL		0x6c
-#define FLOWCTRL_WAIT_WFI_BITMAP	0x100
-#define FLOWCTRL_L2_FLUSH_CONTROL	0x94
-#define FLOWCTRL_BPMP_CLUSTER_CONTROL	0x98
-#define  FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK	(1 << 2)
+#define FLOWCTRL_HALT_CPU0_EVENTS	0x0U
+#define  FLOWCTRL_WAITEVENT		(2U << 29)
+#define  FLOWCTRL_WAIT_FOR_INTERRUPT	(4U << 29)
+#define  FLOWCTRL_JTAG_RESUME		(1U << 28)
+#define  FLOWCTRL_HALT_SCLK		(1U << 27)
+#define  FLOWCTRL_HALT_LIC_IRQ		(1U << 11)
+#define  FLOWCTRL_HALT_LIC_FIQ		(1U << 10)
+#define  FLOWCTRL_HALT_GIC_IRQ		(1U << 9)
+#define  FLOWCTRL_HALT_GIC_FIQ		(1U << 8)
+#define FLOWCTRL_HALT_BPMP_EVENTS	0x4U
+#define FLOWCTRL_CPU0_CSR		0x8U
+#define  FLOW_CTRL_CSR_PWR_OFF_STS	(1U << 16)
+#define  FLOWCTRL_CSR_INTR_FLAG		(1U << 15)
+#define  FLOWCTRL_CSR_EVENT_FLAG	(1U << 14)
+#define  FLOWCTRL_CSR_IMMEDIATE_WAKE	(1U << 3)
+#define  FLOWCTRL_CSR_ENABLE		(1U << 0)
+#define FLOWCTRL_HALT_CPU1_EVENTS	0x14U
+#define FLOWCTRL_CPU1_CSR		0x18U
+#define FLOWCTRL_CC4_CORE0_CTRL		0x6cU
+#define FLOWCTRL_WAIT_WFI_BITMAP	0x100U
+#define FLOWCTRL_L2_FLUSH_CONTROL	0x94U
+#define FLOWCTRL_BPMP_CLUSTER_CONTROL	0x98U
+#define  FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK	(1U << 2)
 
-#define FLOWCTRL_ENABLE_EXT		12
-#define FLOWCTRL_ENABLE_EXT_MASK	3
-#define FLOWCTRL_PG_CPU_NONCPU		0x1
-#define FLOWCTRL_TURNOFF_CPURAIL	0x2
+#define FLOWCTRL_ENABLE_EXT		12U
+#define FLOWCTRL_ENABLE_EXT_MASK	3U
+#define FLOWCTRL_PG_CPU_NONCPU		0x1U
+#define FLOWCTRL_TURNOFF_CPURAIL	0x2U
 
 static inline uint32_t tegra_fc_read_32(uint32_t off)
 {

plat/nvidia/tegra/include/drivers/mce.h

 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -38,35 +38,35 @@
  * MCE commands
  ******************************************************************************/
 typedef enum mce_cmd {
-	MCE_CMD_ENTER_CSTATE = 0,
-	MCE_CMD_UPDATE_CSTATE_INFO = 1,
-	MCE_CMD_UPDATE_CROSSOVER_TIME = 2,
-	MCE_CMD_READ_CSTATE_STATS = 3,
-	MCE_CMD_WRITE_CSTATE_STATS = 4,
-	MCE_CMD_IS_SC7_ALLOWED = 5,
-	MCE_CMD_ONLINE_CORE = 6,
-	MCE_CMD_CC3_CTRL = 7,
-	MCE_CMD_ECHO_DATA = 8,
-	MCE_CMD_READ_VERSIONS = 9,
-	MCE_CMD_ENUM_FEATURES = 10,
-	MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11,
-	MCE_CMD_ENUM_READ_MCA = 12,
-	MCE_CMD_ENUM_WRITE_MCA = 13,
-	MCE_CMD_ROC_FLUSH_CACHE = 14,
-	MCE_CMD_ROC_CLEAN_CACHE = 15,
-	MCE_CMD_ENABLE_LATIC = 16,
-	MCE_CMD_UNCORE_PERFMON_REQ = 17,
-	MCE_CMD_MISC_CCPLEX = 18,
-	MCE_CMD_IS_CCX_ALLOWED = 0xFE,
-	MCE_CMD_MAX = 0xFF,
+	MCE_CMD_ENTER_CSTATE = 0U,
+	MCE_CMD_UPDATE_CSTATE_INFO = 1U,
+	MCE_CMD_UPDATE_CROSSOVER_TIME = 2U,
+	MCE_CMD_READ_CSTATE_STATS = 3U,
+	MCE_CMD_WRITE_CSTATE_STATS = 4U,
+	MCE_CMD_IS_SC7_ALLOWED = 5U,
+	MCE_CMD_ONLINE_CORE = 6U,
+	MCE_CMD_CC3_CTRL = 7U,
+	MCE_CMD_ECHO_DATA = 8U,
+	MCE_CMD_READ_VERSIONS = 9U,
+	MCE_CMD_ENUM_FEATURES = 10U,
+	MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11U,
+	MCE_CMD_ENUM_READ_MCA = 12U,
+	MCE_CMD_ENUM_WRITE_MCA = 13U,
+	MCE_CMD_ROC_FLUSH_CACHE = 14U,
+	MCE_CMD_ROC_CLEAN_CACHE = 15U,
+	MCE_CMD_ENABLE_LATIC = 16U,
+	MCE_CMD_UNCORE_PERFMON_REQ = 17U,
+	MCE_CMD_MISC_CCPLEX = 18U,
+	MCE_CMD_IS_CCX_ALLOWED = 0xFEU,
+	MCE_CMD_MAX = 0xFFU,
 } mce_cmd_t;
 
-#define MCE_CMD_MASK				0xFF
+#define MCE_CMD_MASK				0xFFU
 
 /*******************************************************************************
  * Timeout value used to powerdown a core
  ******************************************************************************/
-#define MCE_CORE_SLEEP_TIME_INFINITE		0xFFFFFFFF
+#define MCE_CORE_SLEEP_TIME_INFINITE		0xFFFFFFFFU
 
 /*******************************************************************************
  * Struct to prepare UPDATE_CSTATE_INFO request

plat/nvidia/tegra/include/drivers/memctrl_v1.h

 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -35,29 +35,29 @@
 #include <tegra_def.h>
 
 /* SMMU registers */
-#define MC_SMMU_CONFIG_0			0x10
-#define  MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE	0
-#define  MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE	1
-#define MC_SMMU_TLB_CONFIG_0			0x14
-#define  MC_SMMU_TLB_CONFIG_0_RESET_VAL		0x20000010
-#define MC_SMMU_PTC_CONFIG_0			0x18
-#define  MC_SMMU_PTC_CONFIG_0_RESET_VAL		0x2000003f
-#define MC_SMMU_TLB_FLUSH_0			0x30
-#define  TLB_FLUSH_VA_MATCH_ALL			0
-#define  TLB_FLUSH_ASID_MATCH_DISABLE		0
-#define  TLB_FLUSH_ASID_MATCH_SHIFT		31
+#define MC_SMMU_CONFIG_0			0x10U
+#define  MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE	0U
+#define  MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE	1U
+#define MC_SMMU_TLB_CONFIG_0			0x14U
+#define  MC_SMMU_TLB_CONFIG_0_RESET_VAL		0x20000010U
+#define MC_SMMU_PTC_CONFIG_0			0x18U
+#define  MC_SMMU_PTC_CONFIG_0_RESET_VAL		0x2000003fU
+#define MC_SMMU_TLB_FLUSH_0			0x30U
+#define  TLB_FLUSH_VA_MATCH_ALL			0U
+#define  TLB_FLUSH_ASID_MATCH_DISABLE		0U
+#define  TLB_FLUSH_ASID_MATCH_SHIFT		31U
 #define  MC_SMMU_TLB_FLUSH_ALL		\
 	 (TLB_FLUSH_VA_MATCH_ALL | 	\
 	 (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT))
-#define MC_SMMU_PTC_FLUSH_0			0x34
-#define  MC_SMMU_PTC_FLUSH_ALL			0
-#define MC_SMMU_ASID_SECURITY_0			0x38
-#define  MC_SMMU_ASID_SECURITY			0
-#define MC_SMMU_TRANSLATION_ENABLE_0_0		0x228
-#define MC_SMMU_TRANSLATION_ENABLE_1_0		0x22c
-#define MC_SMMU_TRANSLATION_ENABLE_2_0		0x230
-#define MC_SMMU_TRANSLATION_ENABLE_3_0		0x234
-#define MC_SMMU_TRANSLATION_ENABLE_4_0		0xb98
+#define MC_SMMU_PTC_FLUSH_0			0x34U
+#define  MC_SMMU_PTC_FLUSH_ALL			0U
+#define MC_SMMU_ASID_SECURITY_0			0x38U
+#define  MC_SMMU_ASID_SECURITY			0U
+#define MC_SMMU_TRANSLATION_ENABLE_0_0		0x228U
+#define MC_SMMU_TRANSLATION_ENABLE_1_0		0x22cU
+#define MC_SMMU_TRANSLATION_ENABLE_2_0		0x230U
+#define MC_SMMU_TRANSLATION_ENABLE_3_0		0x234U
+#define MC_SMMU_TRANSLATION_ENABLE_4_0		0xb98U
 #define  MC_SMMU_TRANSLATION_ENABLE		(~0)
 
 /* MC IRAM aperture registers */

plat/nvidia/tegra/include/drivers/pmc.h

 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -34,19 +34,19 @@
 #include <mmio.h>
 #include <tegra_def.h>
 
-#define PMC_CONFIG				0x0
-#define PMC_PWRGATE_STATUS			0x38
-#define PMC_PWRGATE_TOGGLE			0x30
-#define  PMC_TOGGLE_START			0x100
-#define PMC_SCRATCH39				0x138
-#define PMC_SECURE_DISABLE2			0x2c4
-#define  PMC_SECURE_DISABLE2_WRITE22_ON		(1 << 28)
-#define PMC_SECURE_SCRATCH22			0x338
-#define PMC_SECURE_DISABLE3			0x2d8
-#define  PMC_SECURE_DISABLE3_WRITE34_ON		(1 << 20)
-#define  PMC_SECURE_DISABLE3_WRITE35_ON		(1 << 22)
-#define PMC_SECURE_SCRATCH34			0x368
-#define PMC_SECURE_SCRATCH35			0x36c
+#define PMC_CONFIG				0x0U
+#define PMC_PWRGATE_STATUS			0x38U
+#define PMC_PWRGATE_TOGGLE			0x30U
+#define  PMC_TOGGLE_START			0x100U
+#define PMC_SCRATCH39				0x138U
+#define PMC_SECURE_DISABLE2			0x2c4U
+#define  PMC_SECURE_DISABLE2_WRITE22_ON		(1U << 28)
+#define PMC_SECURE_SCRATCH22			0x338U
+#define PMC_SECURE_DISABLE3			0x2d8U
+#define  PMC_SECURE_DISABLE3_WRITE34_ON		(1U << 20)
+#define  PMC_SECURE_DISABLE3_WRITE35_ON		(1U << 22)
+#define PMC_SECURE_SCRATCH34			0x368U
+#define PMC_SECURE_SCRATCH35			0x36cU
 
 static inline uint32_t tegra_pmc_read_32(uint32_t off)
 {

plat/nvidia/tegra/include/tegra_private.h

 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -39,8 +39,8 @@
 /*******************************************************************************
  * Tegra DRAM memory base address
  ******************************************************************************/
-#define TEGRA_DRAM_BASE		0x80000000
-#define TEGRA_DRAM_END		0x27FFFFFFF
+#define TEGRA_DRAM_BASE		0x80000000ULL
+#define TEGRA_DRAM_END		0x27FFFFFFFULL
 
 /*******************************************************************************
  * Struct for parameters received from BL2

plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h

 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -38,46 +38,46 @@
  * Macros to prepare CSTATE info request
  ******************************************************************************/
 /* Description of the parameters for UPDATE_CSTATE_INFO request */
-#define CLUSTER_CSTATE_MASK			0x7
-#define CLUSTER_CSTATE_SHIFT			0
-#define CLUSTER_CSTATE_UPDATE_BIT		(1 << 7)
-#define CCPLEX_CSTATE_MASK			0x3
-#define CCPLEX_CSTATE_SHIFT			8
-#define CCPLEX_CSTATE_UPDATE_BIT		(1 << 15)
-#define SYSTEM_CSTATE_MASK			0xF
-#define SYSTEM_CSTATE_SHIFT			16
-#define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT	22
-#define SYSTEM_CSTATE_FORCE_UPDATE_BIT		(1 << 22)
-#define SYSTEM_CSTATE_UPDATE_BIT		(1 << 23)
-#define CSTATE_WAKE_MASK_UPDATE_BIT		(1 << 31)
-#define CSTATE_WAKE_MASK_SHIFT			32
-#define CSTATE_WAKE_MASK_CLEAR			0xFFFFFFFF
+#define CLUSTER_CSTATE_MASK			0x7ULL
+#define CLUSTER_CSTATE_SHIFT			0U
+#define CLUSTER_CSTATE_UPDATE_BIT		(1ULL << 7)
+#define CCPLEX_CSTATE_MASK			0x3ULL
+#define CCPLEX_CSTATE_SHIFT			8ULL
+#define CCPLEX_CSTATE_UPDATE_BIT		(1ULL << 15)
+#define SYSTEM_CSTATE_MASK			0xFULL
+#define SYSTEM_CSTATE_SHIFT			16ULL
+#define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT	22ULL
+#define SYSTEM_CSTATE_FORCE_UPDATE_BIT		(1ULL << 22)
+#define SYSTEM_CSTATE_UPDATE_BIT		(1ULL << 23)
+#define CSTATE_WAKE_MASK_UPDATE_BIT		(1ULL << 31)
+#define CSTATE_WAKE_MASK_SHIFT			32ULL
+#define CSTATE_WAKE_MASK_CLEAR			0xFFFFFFFFU
 
 /*******************************************************************************
  * Auto-CC3 control macros
  ******************************************************************************/
-#define MCE_AUTO_CC3_FREQ_MASK			0x1FF
-#define MCE_AUTO_CC3_FREQ_SHIFT			0
-#define MCE_AUTO_CC3_VTG_MASK			0x7F
-#define MCE_AUTO_CC3_VTG_SHIFT			16
-#define MCE_AUTO_CC3_ENABLE_BIT			(1 << 31)
+#define MCE_AUTO_CC3_FREQ_MASK			0x1FFU
+#define MCE_AUTO_CC3_FREQ_SHIFT			0U
+#define MCE_AUTO_CC3_VTG_MASK			0x7FU
+#define MCE_AUTO_CC3_VTG_SHIFT			16U
+#define MCE_AUTO_CC3_ENABLE_BIT			(1U << 31)
 
 /*******************************************************************************
  * Macros for the 'IS_SC7_ALLOWED' command
  ******************************************************************************/
-#define MCE_SC7_ALLOWED_MASK			0x7
-#define MCE_SC7_WAKE_TIME_SHIFT			32
+#define MCE_SC7_ALLOWED_MASK			0x7U
+#define MCE_SC7_WAKE_TIME_SHIFT			32U
 
 /*******************************************************************************
  * Macros for 'read/write ctats' commands
  ******************************************************************************/
-#define MCE_CSTATE_STATS_TYPE_SHIFT		32
-#define MCE_CSTATE_WRITE_DATA_LO_MASK		0xF
+#define MCE_CSTATE_STATS_TYPE_SHIFT		32ULL
+#define MCE_CSTATE_WRITE_DATA_LO_MASK		0xFU
 
 /*******************************************************************************
  * Macros for 'update crossover threshold' command
  ******************************************************************************/
-#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT	32
+#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT	32U
 
 /*******************************************************************************
  * MCA command struct
@@ -150,15 +150,15 @@ typedef union uncore_perfmon_req {
 	uint64_t data;
 } uncore_perfmon_req_t;
 
-#define UNCORE_PERFMON_CMD_READ			0
-#define UNCORE_PERFMON_CMD_WRITE		1
+#define UNCORE_PERFMON_CMD_READ			0U
+#define UNCORE_PERFMON_CMD_WRITE		1U
 
-#define UNCORE_PERFMON_CMD_MASK			0xFF
-#define UNCORE_PERFMON_UNIT_GRP_MASK		0xF
-#define UNCORE_PERFMON_SELECTOR_MASK		0xF
-#define UNCORE_PERFMON_REG_MASK			0xFF
-#define UNCORE_PERFMON_CTR_MASK			0xFF
-#define UNCORE_PERFMON_RESP_STATUS_MASK		0xFF
+#define UNCORE_PERFMON_CMD_MASK			0xFFU
+#define UNCORE_PERFMON_UNIT_GRP_MASK		0xFU
+#define UNCORE_PERFMON_SELECTOR_MASK		0xFU
+#define UNCORE_PERFMON_REG_MASK			0xFFU
+#define UNCORE_PERFMON_CTR_MASK			0xFFU
+#define UNCORE_PERFMON_RESP_STATUS_MASK		0xFFU
 
 /*******************************************************************************
  * Structure populated by arch specific code to export routines which perform