diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index f89e77a341eb0877771837ca437fcad32cd78d34..a6652766fcb5a0c2a44d67b880d933f6b471bb93 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -129,10 +129,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
image_info_t bl32_img_info = { {0} };
- uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end, console_base;
- uint32_t console_clock;
+ uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
int32_t ret;
- static console_16550_t console;
/*
* For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
@@ -182,31 +180,9 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
}
/*
- * Reference clock used by the FPGAs is a lot slower.
+ * Enable console for the platform
*/
- if (tegra_platform_is_fpga()) {
- console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
- } else {
- console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
- }
-
- /*
- * Get the base address of the UART controller to be used for the
- * console
- */
- console_base = plat_get_console_from_id(plat_params->uart_id);
-
- if (console_base != 0U) {
- /*
- * Configure the UART port to be used as the console
- */
- (void)console_16550_register(console_base,
- console_clock,
- TEGRA_CONSOLE_BAUDRATE,
- &console);
- console_set_scope(&console.console, CONSOLE_FLAG_BOOT |
- CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
- }
+ plat_enable_console(plat_params->uart_id);
/*
* The previous bootloader passes the base address of the shared memory
diff --git a/plat/nvidia/tegra/include/drivers/spe.h b/plat/nvidia/tegra/include/drivers/spe.h
new file mode 100644
index 0000000000000000000000000000000000000000..0d6d69d1067025c763e7e81e823abd4731b89da4
--- /dev/null
+++ b/plat/nvidia/tegra/include/drivers/spe.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2019, NVIDIA Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SPE_H
+#define SPE_H
+
+#include <stdint.h>
+
+#include <drivers/console.h>
+
+typedef struct {
+ console_t console;
+ uintptr_t base;
+} console_spe_t;
+
+/*
+ * Initialize a new spe console instance and register it with the console
+ * framework. The |console| pointer must point to storage that will be valid
+ * for the lifetime of the console, such as a global or static local variable.
+ * Its contents will be reinitialized from scratch.
+ */
+int console_spe_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
+ console_spe_t *console);
+
+#endif /* SPE_H */
diff --git a/plat/nvidia/tegra/include/t194/tegra194_private.h b/plat/nvidia/tegra/include/t194/tegra194_private.h
new file mode 100644
index 0000000000000000000000000000000000000000..e519cdccc658cc694eb5fa1c0574ee9daeea4eb8
--- /dev/null
+++ b/plat/nvidia/tegra/include/t194/tegra194_private.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __TEGRA194_PRIVATE_H__
+#define __TEGRA194_PRIVATE_H__
+
+void tegra194_cpu_reset_handler(void);
+uint64_t tegra194_get_cpu_reset_handler_base(void);
+uint64_t tegra194_get_cpu_reset_handler_size(void);
+uint64_t tegra194_get_smmu_ctx_offset(void);
+void tegra194_set_system_suspend_entry(void);
+
+#endif /* __TEGRA194_PRIVATE_H__ */
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index 79d776f556dcd746449cbd91157215d1c4fe2c62..1a9ba0a8421c423c6b03e92c8353e017b771d828 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -14,9 +14,9 @@
* and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
* parameter.
******************************************************************************/
-#define PSTATE_ID_CORE_IDLE 6
-#define PSTATE_ID_CORE_POWERDN 7
-#define PSTATE_ID_SOC_POWERDN 2
+#define PSTATE_ID_CORE_IDLE U(6)
+#define PSTATE_ID_CORE_POWERDN U(7)
+#define PSTATE_ID_SOC_POWERDN U(2)
/*******************************************************************************
* Platform power states (used by PSCI framework)
@@ -24,215 +24,211 @@
* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
******************************************************************************/
-#define PLAT_MAX_RET_STATE 1
-#define PLAT_MAX_OFF_STATE 8
-
-/*******************************************************************************
- * Implementation defined ACTLR_EL3 bit definitions
- ******************************************************************************/
-#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
-#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
-#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
-#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
-#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
-#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
- ACTLR_EL3_L2ECTLR_BIT | \
- ACTLR_EL3_L2CTLR_BIT | \
- ACTLR_EL3_CPUECTLR_BIT | \
- ACTLR_EL3_CPUACTLR_BIT)
+#define PLAT_MAX_RET_STATE U(1)
+#define PLAT_MAX_OFF_STATE U(8)
/*******************************************************************************
* Secure IRQ definitions
******************************************************************************/
-#define TEGRA186_MAX_SEC_IRQS 5
-#define TEGRA186_BPMP_WDT_IRQ 46
-#define TEGRA186_SPE_WDT_IRQ 47
-#define TEGRA186_SCE_WDT_IRQ 48
-#define TEGRA186_TOP_WDT_IRQ 49
-#define TEGRA186_AON_WDT_IRQ 50
+#define TEGRA194_MAX_SEC_IRQS U(2)
+#define TEGRA194_TOP_WDT_IRQ U(49)
+#define TEGRA194_AON_WDT_IRQ U(50)
-#define TEGRA186_SEC_IRQ_TARGET_MASK 0xFF /* 8 Carmel */
+#define TEGRA194_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */
/*******************************************************************************
* Tegra Miscellanous register constants
******************************************************************************/
-#define TEGRA_MISC_BASE 0x00100000
-#define HARDWARE_REVISION_OFFSET 0x4
-
-#define MISCREG_PFCFG 0x200C
-
-/*******************************************************************************
- * Tegra TSA Controller constants
- ******************************************************************************/
-#define TEGRA_TSA_BASE 0x02000000
-
-#define TSA_CONFIG_STATIC0_CSW_SESWR 0x1010
-#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_ETRW 0xD034
-#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x3020
-#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_AXISW 0x8008
-#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_HDAW 0xD008
-#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xE018
-#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x9008
-#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9028
-#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xB008
-#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6008
-#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_AFIW 0xF008
-#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_SATAW 0x4008
-#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x3038
-#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x6018
-#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x6028
-#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100
-
-#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11)
-#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11)
+#define TEGRA_MISC_BASE U(0x00100000)
+
+#define HARDWARE_REVISION_OFFSET U(0x4)
+#define MISCREG_EMU_REVID U(0x3160)
+#define BOARD_MASK_BITS U(0xFF)
+#define BOARD_SHIFT_BITS U(24)
+#define MISCREG_PFCFG U(0x200C)
/*******************************************************************************
* Tegra Memory Controller constants
******************************************************************************/
-#define TEGRA_MC_STREAMID_BASE 0x02C00000
-#define TEGRA_MC_BASE 0x02C10000
+#define TEGRA_MC_STREAMID_BASE U(0x02C00000)
+#define TEGRA_MC_BASE U(0x02C10000)
/* General Security Carveout register macros */
-#define MC_GSC_CONFIG_REGS_SIZE 0x40
-#define MC_GSC_LOCK_CFG_SETTINGS_BIT (1 << 1)
-#define MC_GSC_ENABLE_TZ_LOCK_BIT (1 << 0)
-#define MC_GSC_SIZE_RANGE_4KB_SHIFT 27
-#define MC_GSC_BASE_LO_SHIFT 12
-#define MC_GSC_BASE_LO_MASK 0xFFFFF
-#define MC_GSC_BASE_HI_SHIFT 0
-#define MC_GSC_BASE_HI_MASK 3
+#define MC_GSC_CONFIG_REGS_SIZE U(0x40)
+#define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1)
+#define MC_GSC_ENABLE_TZ_LOCK_BIT (U(1) << 0)
+#define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27)
+#define MC_GSC_BASE_LO_SHIFT U(12)
+#define MC_GSC_BASE_LO_MASK U(0xFFFFF)
+#define MC_GSC_BASE_HI_SHIFT U(0)
+#define MC_GSC_BASE_HI_MASK U(3)
+#define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31)
/* TZDRAM carveout configuration registers */
-#define MC_SECURITY_CFG0_0 0x70
-#define MC_SECURITY_CFG1_0 0x74
-#define MC_SECURITY_CFG3_0 0x9BC
+#define MC_SECURITY_CFG0_0 U(0x70)
+#define MC_SECURITY_CFG1_0 U(0x74)
+#define MC_SECURITY_CFG3_0 U(0x9BC)
+
+#define MC_SECURITY_BOM_MASK (U(0xFFF) << 20)
+#define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0)
+#define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0)
+
+#define MC_SECURITY_CFG_REG_CTRL_0 U(0x154)
+#define SECURITY_CFG_WRITE_ACCESS_BIT (U(0x1) << 0)
+#define SECURITY_CFG_WRITE_ACCESS_ENABLE U(0x0)
+#define SECURITY_CFG_WRITE_ACCESS_DISABLE U(0x1)
/* Video Memory carveout configuration registers */
-#define MC_VIDEO_PROTECT_BASE_HI 0x978
-#define MC_VIDEO_PROTECT_BASE_LO 0x648
-#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
+#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
+#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
+#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
/*
* Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
* non-overlapping Video memory region
*/
-#define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0
-#define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4
-#define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8
-#define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC
-#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0
+#define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0)
+#define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4)
+#define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8)
+#define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC)
+#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0)
/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
-#define MC_TZRAM_CARVEOUT_CFG 0x2190
-#define MC_TZRAM_BASE_LO 0x2194
-#define MC_TZRAM_BASE_HI 0x2198
-#define MC_TZRAM_SIZE 0x219C
-#define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0
+#define MC_TZRAM_CARVEOUT_CFG U(0x2190)
+#define MC_TZRAM_BASE_LO U(0x2194)
+#define MC_TZRAM_BASE_HI U(0x2198)
+#define MC_TZRAM_SIZE U(0x219C)
+#define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0)
+#define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4)
+#define TZRAM_ALLOW_MPCORER (U(1) << 7)
+#define TZRAM_ALLOW_MPCOREW (U(1) << 25)
/* Memory Controller Reset Control registers */
-#define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1 << 27)
-#define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (1 << 28)
-#define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (1 << 29)
-#define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (1 << 30)
-#define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (1 << 31)
+#define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (U(1) << 28)
+#define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (U(1) << 29)
+#define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (U(1) << 30)
+#define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (U(1) << 31)
/*******************************************************************************
* Tegra UART Controller constants
******************************************************************************/
-#define TEGRA_UARTA_BASE 0x03100000
-#define TEGRA_UARTB_BASE 0x03110000
-#define TEGRA_UARTC_BASE 0x0C280000
-#define TEGRA_UARTD_BASE 0x03130000
-#define TEGRA_UARTE_BASE 0x03140000
-#define TEGRA_UARTF_BASE 0x03150000
-#define TEGRA_UARTG_BASE 0x0C290000
+#define TEGRA_UARTA_BASE U(0x03100000)
+#define TEGRA_UARTB_BASE U(0x03110000)
+#define TEGRA_UARTC_BASE U(0x0C280000)
+#define TEGRA_UARTD_BASE U(0x03130000)
+#define TEGRA_UARTE_BASE U(0x03140000)
+#define TEGRA_UARTF_BASE U(0x03150000)
+#define TEGRA_UARTG_BASE U(0x0C290000)
/*******************************************************************************
* Tegra Fuse Controller related constants
******************************************************************************/
-#define TEGRA_FUSE_BASE 0x03820000
-#define OPT_SUBREVISION 0x248
-#define SUBREVISION_MASK 0xF
+#define TEGRA_FUSE_BASE U(0x03820000)
+#define OPT_SUBREVISION U(0x248)
+#define SUBREVISION_MASK U(0xF)
/*******************************************************************************
* GICv2 & interrupt handling related constants
******************************************************************************/
-#define TEGRA_GICD_BASE 0x03881000
-#define TEGRA_GICC_BASE 0x03882000
+#define TEGRA_GICD_BASE U(0x03881000)
+#define TEGRA_GICC_BASE U(0x03882000)
/*******************************************************************************
* Security Engine related constants
******************************************************************************/
-#define TEGRA_SE0_BASE 0x03AC0000
-#define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C
-#define TEGRA_PKA1_BASE 0x03AD0000
-#define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144
-#define TEGRA_RNG1_BASE 0x03AE0000
-#define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0
+#define TEGRA_SE0_BASE U(0x03AC0000)
+#define SE0_MUTEX_WATCHDOG_NS_LIMIT U(0x6C)
+#define SE0_AES0_ENTROPY_SRC_AGE_CTRL U(0x2FC)
+#define TEGRA_PKA1_BASE U(0x03AD0000)
+#define SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL U(0x144)
+#define PKA1_MUTEX_WATCHDOG_NS_LIMIT SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL
+#define TEGRA_RNG1_BASE U(0x03AE0000)
+#define RNG1_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0)
+
+/*******************************************************************************
+ * Tegra hardware synchronization primitives for the SPE engine
+ ******************************************************************************/
+#define TEGRA_AON_HSP_SM_6_7_BASE U(0x0c190000)
+#define TEGRA_CONSOLE_SPE_BASE (TEGRA_AON_HSP_SM_6_7_BASE + U(0x8000))
/*******************************************************************************
* Tegra micro-seconds timer constants
******************************************************************************/
-#define TEGRA_TMRUS_BASE 0x0C2E0000
-#define TEGRA_TMRUS_SIZE 0x10000
+#define TEGRA_TMRUS_BASE U(0x0C2E0000)
+#define TEGRA_TMRUS_SIZE U(0x10000)
/*******************************************************************************
* Tegra Power Mgmt Controller constants
******************************************************************************/
-#define TEGRA_PMC_BASE 0x0C360000
+#define TEGRA_PMC_BASE U(0x0C360000)
/*******************************************************************************
* Tegra scratch registers constants
******************************************************************************/
-#define TEGRA_SCRATCH_BASE 0x0C390000
-#define SECURE_SCRATCH_RSV1_LO 0x06C
-#define SECURE_SCRATCH_RSV1_HI 0x070
-#define SECURE_SCRATCH_RSV6 0x094
-#define SECURE_SCRATCH_RSV11_LO 0x0BC
-#define SECURE_SCRATCH_RSV11_HI 0x0C0
-#define SECURE_SCRATCH_RSV53_LO 0x20C
-#define SECURE_SCRATCH_RSV53_HI 0x210
-#define SECURE_SCRATCH_RSV54_HI 0x218
-#define SECURE_SCRATCH_RSV55_LO 0x21C
-#define SECURE_SCRATCH_RSV55_HI 0x220
+#define TEGRA_SCRATCH_BASE U(0x0C390000)
+#define SECURE_SCRATCH_RSV44_LO U(0x1C4)
+#define SECURE_SCRATCH_RSV44_HI U(0x1C8)
+#define SECURE_SCRATCH_RSV97 U(0x36C)
+#define SECURE_SCRATCH_RSV99_LO U(0x37C)
+#define SECURE_SCRATCH_RSV99_HI U(0x380)
+#define SECURE_SCRATCH_RSV109_LO U(0x3CC)
+#define SECURE_SCRATCH_RSV109_HI U(0x3D0)
+
+#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV44_LO
+#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV44_HI
+#define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97
+#define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO
+#define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI
+#define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV109_LO
+#define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV109_HI
/*******************************************************************************
* Tegra Memory Mapped Control Register Access Bus constants
******************************************************************************/
-#define TEGRA_MMCRAB_BASE 0x0E000000
+#define TEGRA_MMCRAB_BASE U(0x0E000000)
/*******************************************************************************
* Tegra SMMU Controller constants
******************************************************************************/
-#define TEGRA_SMMU0_BASE 0x12000000
-#define TEGRA_SMMU1_BASE 0x11000000
-#define TEGRA_SMMU2_BASE 0x10000000
+#define TEGRA_SMMU0_BASE U(0x12000000)
+#define TEGRA_SMMU1_BASE U(0x11000000)
+#define TEGRA_SMMU2_BASE U(0x10000000)
/*******************************************************************************
* Tegra TZRAM constants
******************************************************************************/
-#define TEGRA_TZRAM_BASE 0x40000000
-#define TEGRA_TZRAM_SIZE 0x40000
+#define TEGRA_TZRAM_BASE U(0x40000000)
+#define TEGRA_TZRAM_SIZE U(0x40000)
/*******************************************************************************
* Tegra Clock and Reset Controller constants
******************************************************************************/
-#define TEGRA_CAR_RESET_BASE 0x200000000
-#define TEGRA_GPU_RESET_REG_OFFSET 0x18UL
-#define GPU_RESET_BIT (1UL << 0)
+#define TEGRA_CAR_RESET_BASE U(0x20000000)
+#define TEGRA_GPU_RESET_REG_OFFSET U(0x18)
+#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x1C)
+#define GPU_RESET_BIT (U(1) << 0)
+#define GPU_SET_BIT (U(1) << 0)
+
+/*******************************************************************************
+ * XUSB PADCTL
+ ******************************************************************************/
+#define TEGRA_XUSB_PADCTL_BASE U(0x3520000)
+#define TEGRA_XUSB_PADCTL_SIZE U(0x10000)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 U(0x136c)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 U(0x1370)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 U(0x1374)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 U(0x1378)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 U(0x137c)
+#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 U(0x139c)
+
+/*******************************************************************************
+ * XUSB STREAMIDs
+ ******************************************************************************/
+#define TEGRA_SID_XUSB_HOST U(0x1b)
+#define TEGRA_SID_XUSB_DEV U(0x1c)
+#define TEGRA_SID_XUSB_VF0 U(0x5d)
+#define TEGRA_SID_XUSB_VF1 U(0x5e)
+#define TEGRA_SID_XUSB_VF2 U(0x5f)
+#define TEGRA_SID_XUSB_VF3 U(0x60)
#endif /* __TEGRA_DEF_H__ */
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index fab0eafc311bcb641cea934053eb9ed5dae83170..cd2f77308c884e67af76f2bf55347ff13e43a7c3 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -76,7 +76,7 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state,
/* Declarations for plat_setup.c */
const mmap_region_t *plat_get_mmio_map(void);
-uint32_t plat_get_console_from_id(int32_t id);
+void plat_enable_console(int32_t id);
void plat_gic_setup(void);
struct tegra_bl31_params *plat_get_bl31_params(void);
plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
diff --git a/plat/nvidia/tegra/soc/t132/plat_setup.c b/plat/nvidia/tegra/soc/t132/plat_setup.c
index 570acd900daed345e104de32eddadc5cb2785552..df6267897086496f85478d1a19ad9eaf869f9d19 100644
--- a/plat/nvidia/tegra/soc/t132/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t132/plat_setup.c
@@ -6,9 +6,11 @@
#include <arch_helpers.h>
#include <common/bl_common.h>
+#include <drivers/console.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <tegra_def.h>
+#include <tegra_platform.h>
#include <tegra_private.h>
/* sets of MMIO ranges setup */
@@ -85,14 +87,30 @@ static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = {
};
/*******************************************************************************
- * Retrieve the UART controller base to be used as the console
+ * Enable console corresponding to the console ID
******************************************************************************/
-uint32_t plat_get_console_from_id(int id)
+void plat_enable_console(int32_t id)
{
- if (id > TEGRA132_MAX_UART_PORTS)
- return 0;
+ static console_16550_t uart_console;
+ uint32_t console_clock;
- return tegra132_uart_addresses[id];
+ if ((id > 0) && (id < TEGRA132_MAX_UART_PORTS)) {
+ /*
+ * Reference clock used by the FPGAs is a lot slower.
+ */
+ if (tegra_platform_is_fpga()) {
+ console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
+ } else {
+ console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
+ }
+
+ (void)console_16550_register(tegra132_uart_addresses[id],
+ console_clock,
+ TEGRA_CONSOLE_BAUDRATE,
+ &uart_console);
+ console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT |
+ CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
+ }
}
/*******************************************************************************
diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index ef0ba4eb1251dac5f1c5f934dd88fc45adeadbcf..1018caa94633e13e9a36ccc6d1f1922ea8d3eb30 100644
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -141,19 +141,30 @@ static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
};
/*******************************************************************************
- * Retrieve the UART controller base to be used as the console
+ * Enable console corresponding to the console ID
******************************************************************************/
-uint32_t plat_get_console_from_id(int32_t id)
+void plat_enable_console(int32_t id)
{
- uint32_t ret;
+ static console_16550_t uart_console;
+ uint32_t console_clock;
+
+ if ((id > 0) && (id < TEGRA186_MAX_UART_PORTS)) {
+ /*
+ * Reference clock used by the FPGAs is a lot slower.
+ */
+ if (tegra_platform_is_fpga()) {
+ console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
+ } else {
+ console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
+ }
- if (id > TEGRA186_MAX_UART_PORTS) {
- ret = 0;
- } else {
- ret = tegra186_uart_addresses[id];
+ (void)console_16550_register(tegra186_uart_addresses[id],
+ console_clock,
+ TEGRA_CONSOLE_BAUDRATE,
+ &uart_console);
+ console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT |
+ CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
}
-
- return ret;
}
/*******************************************************************************
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
index cc32ec41611ac02075aa0a624728821897aa69f0..3994b2d75514f2f2b421bda125cc22fc7e0ce468 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
@@ -7,44 +7,40 @@
#ifndef __MCE_PRIVATE_H__
#define __MCE_PRIVATE_H__
-#include <mmio.h>
#include <tegra_def.h>
/*******************************************************************************
* Macros to prepare CSTATE info request
******************************************************************************/
/* Description of the parameters for UPDATE_CSTATE_INFO request */
-#define CLUSTER_CSTATE_MASK 0x7UL
-#define CLUSTER_CSTATE_SHIFT 0X0UL
-#define CLUSTER_CSTATE_UPDATE_BIT (1UL << 7)
-#define CCPLEX_CSTATE_MASK 0x3UL
-#define CCPLEX_CSTATE_SHIFT 8UL
-#define CCPLEX_CSTATE_UPDATE_BIT (1UL << 15)
-#define SYSTEM_CSTATE_MASK 0xFUL
-#define SYSTEM_CSTATE_SHIFT 16UL
-#define SYSTEM_CSTATE_UPDATE_BIT (1UL << 23)
-#define CSTATE_WAKE_MASK_UPDATE_BIT (1UL << 31)
-#define CSTATE_WAKE_MASK_SHIFT 32UL
-#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFUL
+#define CLUSTER_CSTATE_MASK 0x7U
+#define CLUSTER_CSTATE_SHIFT 0X0U
+#define CLUSTER_CSTATE_UPDATE_BIT (1U << 7)
+#define CCPLEX_CSTATE_MASK 0x7U
+#define CCPLEX_CSTATE_SHIFT 8U
+#define CCPLEX_CSTATE_UPDATE_BIT (1U << 15)
+#define SYSTEM_CSTATE_MASK 0xFU
+#define SYSTEM_CSTATE_SHIFT 16U
+#define SYSTEM_CSTATE_UPDATE_BIT (1U << 23)
+#define CSTATE_WAKE_MASK_UPDATE_BIT (1U << 31)
+#define CSTATE_WAKE_MASK_SHIFT 32U
+#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFU
/*******************************************************************************
- * Auto-CC3 control macros
+ * Core ID mask (bits 3:0 in the online request)
******************************************************************************/
-#define MCE_AUTO_CC3_FREQ_MASK 0xFFUL
-#define MCE_AUTO_CC3_FREQ_SHIFT 0UL
-#define MCE_AUTO_CC3_ENABLE_BIT (1UL << 31)
+#define MCE_CORE_ID_MASK 0xFU
/*******************************************************************************
- * Core ID mask (bits 3:0 in the online request)
+ * C-state statistics macros
******************************************************************************/
-#define MCE_CORE_ID_MASK 0xFUL
+#define MCE_STAT_ID_SHIFT 16U
/*******************************************************************************
- * Cache control macros
+ * Security config macros
******************************************************************************/
-#define CACHE_CLEAN_SET (1UL << 0)
-#define CACHE_CLEAN_INVAL_SET (1UL << 1)
-#define CACHE_CLEAN_INVAL_TR_SET (1UL << 2)
+#define STRICT_CHECKING_ENABLED_SET (1UL << 0)
+#define STRICT_CHECKING_LOCKED_SET (1UL << 1)
/* declarations for NVG handler functions */
uint64_t nvg_get_version(void);
@@ -55,20 +51,25 @@ int32_t nvg_disable_power_saver_modes(void);
void nvg_set_wake_time(uint32_t wake_time);
void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex,
uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask);
-int32_t nvg_update_crossover_time(uint32_t type, uint32_t time);
int32_t nvg_set_cstate_stat_query_value(uint64_t data);
uint64_t nvg_get_cstate_stat_query_value(void);
int32_t nvg_is_sc7_allowed(void);
int32_t nvg_online_core(uint32_t core);
-int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable);
int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
-int32_t nvg_roc_flush_cache(void);
int32_t nvg_roc_clean_cache(void);
+int32_t nvg_roc_flush_cache(void);
int32_t nvg_roc_clean_cache_trbits(void);
int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
-
void nvg_set_request_data(uint64_t req, uint64_t data);
void nvg_set_request(uint64_t req);
uint64_t nvg_get_result(void);
+uint64_t nvg_cache_clean(void);
+uint64_t nvg_cache_clean_inval(void);
+uint64_t nvg_cache_inval_all(void);
+int32_t nvg_roc_clean_cache_trbits(void);
+void nvg_enable_strict_checking_mode(void);
+
+/* MCE helper functions */
+void mce_enable_strict_checking(void);
#endif /* __MCE_PRIVATE_H__ */
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h b/plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h
deleted file mode 100644
index 8eaae678a67edeefbb969ae269b995cd52ccd961..0000000000000000000000000000000000000000
--- a/plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h
+++ /dev/null
@@ -1,586 +0,0 @@
-/*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __MEMCTRL_PLAT_CONFIG_H
-#define __MEMCTRL_PLAT_CONFIG_H
-
-#include <memctrl_v2.h>
-
-/*******************************************************************************
- * StreamID to indicate no SMMU translations (requests to be steered on the
- * SMMU bypass path)
- ******************************************************************************/
-#define MC_STREAM_ID_MAX 0x7F
-
-/*******************************************************************************
- * Stream ID Override Config registers
- ******************************************************************************/
-#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x000
-#define MC_STREAMID_OVERRIDE_CFG_HDAR 0x0A8
-#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0x0B0
-#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0x0E0
-#define MC_STREAMID_OVERRIDE_CFG_SATAR 0x0F8
-#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138
-#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158
-#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8
-#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8
-#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8
-#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220
-#define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228
-#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230
-#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238
-#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250
-#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258
-#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260
-#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268
-#define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0
-#define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8
-#define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0 /*TODO: remove it after HW team confirmation */
-#define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8 /*TODO: remove it after HW team confirmation */
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338
-#define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360
-#define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368
-#define MC_STREAMID_OVERRIDE_CFG_VIW 0x390
-#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0
-#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8
-#define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0
-#define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8
-#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0
-#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8
-#define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400
-#define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408
-#define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410
-#define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418
-#define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420
-#define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428
-#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430
-#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438
-#define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440 /*TODO: remove it after HW team confirmation */
-#define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448 /*TODO: remove it after HW team confirmation */
-#define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460
-#define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468
-#define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470
-#define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478
-#define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480
-#define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488
-#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490
-#define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498
-#define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0
-#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8
-#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0
-#define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8
-#define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0
-#define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8
-#define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0
-#define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8
-#define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0
-#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8
-#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0
-#define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8
-#define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500
-#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508
-#define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510
-#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518
-#define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530
-#define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538
-#define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540
-#define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548
-#define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570
-#define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578
-#define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580
-#define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588
-#define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5E0
-#define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5E8
-#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5F0
-#define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5F8
-#define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600
-#define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608
-#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610
-#define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618
-#define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620
-#define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628
-#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630
-#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638
-#define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640
-#define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648
-#define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650
-#define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658
-#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660
-#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668
-#define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670
-#define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678
-#define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680
-#define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688
-#define MC_STREAMID_OVERRIDE_CFG_RCER 0x690
-#define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698
-#define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6A0
-#define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6A8
-#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6B0
-#define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6B8
-#define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6C0
-#define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6C8
-#define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6D0
-#define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6D8
-#define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6E0
-#define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6E8
-#define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6F0
-#define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6F8
-#define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700
-#define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708
-#define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710
-#define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718
-#define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720
-#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748
-#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750
-#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758
-#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760
-#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768
-#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770
-#define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778
-#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780
-#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788
-#define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790
-#define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798
-#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7C8
-#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7D0
-#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7D8
-
-/*******************************************************************************
- * Macro to calculate Security cfg register addr from StreamID Override register
- ******************************************************************************/
-#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) (addr + sizeof(uint32_t))
-
-/*******************************************************************************
- * Memory Controller transaction override config registers
- ******************************************************************************/
-#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8
-#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0
-#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000
-#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490
-#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478
-#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8
-#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220
-#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360
-#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8
-#define MC_TXN_OVERRIDE_CONFIG_GPUSRD 0x12c0
-#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460
-#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330
-#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470
-#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8
-#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318
-#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510
-#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8
-#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390
-#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468
-#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260
-#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480
-#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8
-#define MC_TXN_OVERRIDE_CONFIG_GPUSWR 0x12c8
-#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8
-#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258
-#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438
-#define MC_TXN_OVERRIDE_CONFIG_GPUSRD2 0x1440
-#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8
-#define MC_TXN_OVERRIDE_CONFIG_GPUSWR2 0x1448
-#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0
-#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500
-#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0
-#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0
-#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420
-#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408
-#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0
-#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0
-#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430
-#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0
-#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0
-#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518
-#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250
-#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230
-#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400
-#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8
-#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8
-#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320
-#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8
-#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8
-#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488
-#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8
-#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8
-#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428
-#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368
-#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300
-#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508
-#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238
-#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498
-#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310
-#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268
-#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0
-#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0
-#define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530
-#define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538
-#define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540
-#define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548
-#define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570
-#define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578
-#define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580
-#define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158C
-#define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15E4
-#define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15EC
-#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15F4
-#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15FC
-#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604
-#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160C
-#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614
-#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161C
-#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624
-#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162C
-#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634
-#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163C
-#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644
-#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164C
-#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654
-#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165C
-#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664
-#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166C
-#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674
-#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167C
-#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684
-#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168C
-#define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694
-#define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169C
-#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16A4
-#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16AC
-#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16B4
-#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16BC
-#define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16C4
-#define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16CC
-#define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16D4
-#define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16DC
-#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16E4
-#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16EC
-#define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16F4
-#define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16FC
-#define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704
-#define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170C
-#define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714
-#define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171C
-#define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724
-#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174C
-#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754
-#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175C
-#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764
-#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176C
-#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774
-#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177C
-#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784
-#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178C
-#define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794
-#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179C
-#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17CC
-#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17D4
-#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17DC
-
-/*******************************************************************************
- * Array to hold stream_id override config register offsets
- ******************************************************************************/
-const static uint32_t mc_streamid_override_regs[] = {
- MC_STREAMID_OVERRIDE_CFG_HDAR,
- MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
- MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
- MC_STREAMID_OVERRIDE_CFG_SATAR,
- MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
- MC_STREAMID_OVERRIDE_CFG_HDAW,
- MC_STREAMID_OVERRIDE_CFG_SATAW,
- MC_STREAMID_OVERRIDE_CFG_ISPRA,
- MC_STREAMID_OVERRIDE_CFG_ISPFALR,
- MC_STREAMID_OVERRIDE_CFG_ISPWA,
- MC_STREAMID_OVERRIDE_CFG_ISPWB,
- MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
- MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
- MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
- MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
- MC_STREAMID_OVERRIDE_CFG_TSECSRD,
- MC_STREAMID_OVERRIDE_CFG_TSECSWR,
- MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
- MC_STREAMID_OVERRIDE_CFG_SDMMCR,
- MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
- MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
- MC_STREAMID_OVERRIDE_CFG_SDMMCW,
- MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
- MC_STREAMID_OVERRIDE_CFG_VICSRD,
- MC_STREAMID_OVERRIDE_CFG_VICSWR,
- MC_STREAMID_OVERRIDE_CFG_VIW,
- MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
- MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
- MC_STREAMID_OVERRIDE_CFG_APER,
- MC_STREAMID_OVERRIDE_CFG_APEW,
- MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
- MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
- MC_STREAMID_OVERRIDE_CFG_SESRD,
- MC_STREAMID_OVERRIDE_CFG_SESWR,
- MC_STREAMID_OVERRIDE_CFG_AXIAPR,
- MC_STREAMID_OVERRIDE_CFG_AXIAPW,
- MC_STREAMID_OVERRIDE_CFG_ETRR,
- MC_STREAMID_OVERRIDE_CFG_ETRW,
- MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
- MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
- MC_STREAMID_OVERRIDE_CFG_AXISR,
- MC_STREAMID_OVERRIDE_CFG_AXISW,
- MC_STREAMID_OVERRIDE_CFG_EQOSR,
- MC_STREAMID_OVERRIDE_CFG_EQOSW,
- MC_STREAMID_OVERRIDE_CFG_UFSHCR,
- MC_STREAMID_OVERRIDE_CFG_UFSHCW,
- MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
- MC_STREAMID_OVERRIDE_CFG_BPMPR,
- MC_STREAMID_OVERRIDE_CFG_BPMPW,
- MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
- MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
- MC_STREAMID_OVERRIDE_CFG_AONR,
- MC_STREAMID_OVERRIDE_CFG_AONW,
- MC_STREAMID_OVERRIDE_CFG_AONDMAR,
- MC_STREAMID_OVERRIDE_CFG_AONDMAW,
- MC_STREAMID_OVERRIDE_CFG_SCER,
- MC_STREAMID_OVERRIDE_CFG_SCEW,
- MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
- MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
- MC_STREAMID_OVERRIDE_CFG_APEDMAR,
- MC_STREAMID_OVERRIDE_CFG_APEDMAW,
- MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
- MC_STREAMID_OVERRIDE_CFG_VICSRD1,
- MC_STREAMID_OVERRIDE_CFG_NVDECSRD1,
- MC_STREAMID_OVERRIDE_CFG_VIFALR,
- MC_STREAMID_OVERRIDE_CFG_VIFALW,
- MC_STREAMID_OVERRIDE_CFG_DLA0RDA,
- MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB,
- MC_STREAMID_OVERRIDE_CFG_DLA0WRA,
- MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB,
- MC_STREAMID_OVERRIDE_CFG_DLA1RDA,
- MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB,
- MC_STREAMID_OVERRIDE_CFG_DLA1WRA,
- MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB,
- MC_STREAMID_OVERRIDE_CFG_PVA0RDA,
- MC_STREAMID_OVERRIDE_CFG_PVA0RDB,
- MC_STREAMID_OVERRIDE_CFG_PVA0RDC,
- MC_STREAMID_OVERRIDE_CFG_PVA0WRA,
- MC_STREAMID_OVERRIDE_CFG_PVA0WRB,
- MC_STREAMID_OVERRIDE_CFG_PVA0WRC,
- MC_STREAMID_OVERRIDE_CFG_PVA1RDA,
- MC_STREAMID_OVERRIDE_CFG_PVA1RDB,
- MC_STREAMID_OVERRIDE_CFG_PVA1RDC,
- MC_STREAMID_OVERRIDE_CFG_PVA1WRA,
- MC_STREAMID_OVERRIDE_CFG_PVA1WRB,
- MC_STREAMID_OVERRIDE_CFG_PVA1WRC,
- MC_STREAMID_OVERRIDE_CFG_RCER,
- MC_STREAMID_OVERRIDE_CFG_RCEW,
- MC_STREAMID_OVERRIDE_CFG_RCEDMAR,
- MC_STREAMID_OVERRIDE_CFG_RCEDMAW,
- MC_STREAMID_OVERRIDE_CFG_NVENC1SRD,
- MC_STREAMID_OVERRIDE_CFG_NVENC1SWR,
- MC_STREAMID_OVERRIDE_CFG_PCIE0R,
- MC_STREAMID_OVERRIDE_CFG_PCIE0W,
- MC_STREAMID_OVERRIDE_CFG_PCIE1R,
- MC_STREAMID_OVERRIDE_CFG_PCIE1W,
- MC_STREAMID_OVERRIDE_CFG_PCIE2AR,
- MC_STREAMID_OVERRIDE_CFG_PCIE2AW,
- MC_STREAMID_OVERRIDE_CFG_PCIE3R,
- MC_STREAMID_OVERRIDE_CFG_PCIE3W,
- MC_STREAMID_OVERRIDE_CFG_PCIE4R,
- MC_STREAMID_OVERRIDE_CFG_PCIE4W,
- MC_STREAMID_OVERRIDE_CFG_PCIE5R,
- MC_STREAMID_OVERRIDE_CFG_PCIE5W,
- MC_STREAMID_OVERRIDE_CFG_ISPFALW,
- MC_STREAMID_OVERRIDE_CFG_DLA0RDA1,
- MC_STREAMID_OVERRIDE_CFG_DLA1RDA1,
- MC_STREAMID_OVERRIDE_CFG_PVA0RDA1,
- MC_STREAMID_OVERRIDE_CFG_PVA0RDB1,
- MC_STREAMID_OVERRIDE_CFG_PVA1RDA1,
- MC_STREAMID_OVERRIDE_CFG_PVA1RDB1,
- MC_STREAMID_OVERRIDE_CFG_PCIE5R1,
- MC_STREAMID_OVERRIDE_CFG_NVENCSRD1,
- MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1,
- MC_STREAMID_OVERRIDE_CFG_ISPRA1,
- MC_STREAMID_OVERRIDE_CFG_MIU0R,
- MC_STREAMID_OVERRIDE_CFG_MIU0W,
- MC_STREAMID_OVERRIDE_CFG_MIU1R,
- MC_STREAMID_OVERRIDE_CFG_MIU1W,
- MC_STREAMID_OVERRIDE_CFG_MIU2R,
- MC_STREAMID_OVERRIDE_CFG_MIU2W,
- MC_STREAMID_OVERRIDE_CFG_MIU3R,
- MC_STREAMID_OVERRIDE_CFG_MIU3W
-};
-
-/*******************************************************************************
- * Array to hold the security configs for stream IDs
- ******************************************************************************/
-const static mc_streamid_security_cfg_t mc_streamid_sec_cfgs[] = {
- mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
- mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
- mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, ENABLE),
-};
-
-/*******************************************************************************
- * Array to hold the transaction override configs
- ******************************************************************************/
-const static mc_txn_override_cfg_t mc_txn_override_cfgs[] = {
- mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR),
- mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR),
- mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR),
- mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR),
- mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR),
- mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR),
- mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR),
- mc_make_txn_override_cfg(APEW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR),
- mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR),
- mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR),
- mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(AONW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR),
-};
-
-#endif //__MEMCTRL_PLAT_CONFIG_H
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/se.h b/plat/nvidia/tegra/soc/t194/drivers/include/se.h
new file mode 100644
index 0000000000000000000000000000000000000000..6e656f677513264a30a129f9011dfe8b12e8e0a6
--- /dev/null
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/se.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SE_H__
+#define __SE_H__
+
+int32_t tegra_se_suspend(void);
+void tegra_se_resume(void);
+
+#endif /* __SE_H__ */
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
index 1fe462032d70b89fd5377e55fc01b707c0435d47..cc0da80bf62ee425bcd346a63726d0451b286d9e 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
@@ -19,257 +19,315 @@
* occur when there is only new functionality.
*/
enum {
- TEGRA_NVG_VERSION_MAJOR = 6,
- TEGRA_NVG_VERSION_MINOR = 0,
+ TEGRA_NVG_VERSION_MAJOR = 6,
+ TEGRA_NVG_VERSION_MINOR = 4
};
typedef enum {
- TEGRA_NVG_CHANNEL_VERSION = 0,
- TEGRA_NVG_CHANNEL_POWER_PERF = 1,
- TEGRA_NVG_CHANNEL_POWER_MODES = 2,
- TEGRA_NVG_CHANNEL_WAKE_TIME = 3,
- TEGRA_NVG_CHANNEL_CSTATE_INFO = 4,
- TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5,
- TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6,
- // Value 7 reserved
- TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8,
- // Value 9 reserved
- TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10,
- TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11,
- // Values 12-42 reserved
- TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43,
- TEGRA_NVG_CHANNEL_ONLINE_CORE = 44,
- TEGRA_NVG_CHANNEL_CC3_CTRL = 45,
- TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50,
- TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL = 51,
- // 52 FREQ FEEDBACK
- TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53,
- TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54,
- TEGRA_NVG_CHANNEL_LAST_INDEX,
+ TEGRA_NVG_CHANNEL_VERSION = 0,
+ TEGRA_NVG_CHANNEL_POWER_PERF = 1,
+ TEGRA_NVG_CHANNEL_POWER_MODES = 2,
+ TEGRA_NVG_CHANNEL_WAKE_TIME = 3,
+ TEGRA_NVG_CHANNEL_CSTATE_INFO = 4,
+ TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5,
+ TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6,
+ TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8,
+ TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10,
+ TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11,
+ TEGRA_NVG_CHANNEL_SHUTDOWN = 42,
+ TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43,
+ TEGRA_NVG_CHANNEL_ONLINE_CORE = 44,
+ TEGRA_NVG_CHANNEL_CC3_CTRL = 45,
+ TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49,
+ TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50,
+ TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53,
+ TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54,
+ TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55,
+ TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56,
+ TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57,
+ TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58,
+ TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59,
+ TEGRA_NVG_CHANNEL_DDA_MCF_ISO = 60,
+ TEGRA_NVG_CHANNEL_DDA_MCF_SISO = 61,
+ TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 62,
+ TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 63,
+ TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 64,
+ TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 65,
+ TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 66,
+ TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 67,
+ TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 68,
+ TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 69,
+ TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 70,
+ TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 71,
+ TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL = 72,
+ TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL = 73,
+ TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D = 74,
+ TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD = 75,
+ TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR = 76,
+ TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = 77,
+ TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = 78,
+ TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = 79,
+
+ TEGRA_NVG_CHANNEL_LAST_INDEX
} tegra_nvg_channel_id_t;
-
typedef enum {
- // Value 0 reserved
- NVG_STAT_QUERY_SC7_ENTRIES = 1,
- // Values 2-5 reserved
- NVG_STAT_QUERY_CC6_ENTRIES = 6,
- NVG_STAT_QUERY_CG7_ENTRIES = 7,
- // Values 8-9 reserved
- NVG_STAT_QUERY_C6_ENTRIES = 10,
- // Values 11-13 reserved
- NVG_STAT_QUERY_C7_ENTRIES = 14,
- // Values 15-31 reserved
- NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32,
- NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41,
- NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46,
- NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51,
- NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56,
+ NVG_STAT_QUERY_SC7_ENTRIES = 1,
+ NVG_STAT_QUERY_CC6_ENTRIES = 6,
+ NVG_STAT_QUERY_CG7_ENTRIES = 7,
+ NVG_STAT_QUERY_C6_ENTRIES = 10,
+ NVG_STAT_QUERY_C7_ENTRIES = 14,
+ NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32,
+ NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41,
+ NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46,
+ NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51,
+ NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56,
+ NVG_STAT_QUERY_SC7_ENTRY_TIME_SUM = 60,
+ NVG_STAT_QUERY_CC6_ENTRY_TIME_SUM = 61,
+ NVG_STAT_QUERY_CG7_ENTRY_TIME_SUM = 62,
+ NVG_STAT_QUERY_C6_ENTRY_TIME_SUM = 63,
+ NVG_STAT_QUERY_C7_ENTRY_TIME_SUM = 64,
+ NVG_STAT_QUERY_SC7_EXIT_TIME_SUM = 70,
+ NVG_STAT_QUERY_CC6_EXIT_TIME_SUM = 71,
+ NVG_STAT_QUERY_CG7_EXIT_TIME_SUM = 72,
+ NVG_STAT_QUERY_C6_EXIT_TIME_SUM = 73,
+ NVG_STAT_QUERY_C7_EXIT_TIME_SUM = 74,
+ NVG_STAT_QUERY_SC7_ENTRY_LAST = 80,
+ NVG_STAT_QUERY_CC6_ENTRY_LAST = 81,
+ NVG_STAT_QUERY_CG7_ENTRY_LAST = 82,
+ NVG_STAT_QUERY_C6_ENTRY_LAST = 83,
+ NVG_STAT_QUERY_C7_ENTRY_LAST = 84,
+ NVG_STAT_QUERY_SC7_EXIT_LAST = 90,
+ NVG_STAT_QUERY_CC6_EXIT_LAST = 91,
+ NVG_STAT_QUERY_CG7_EXIT_LAST = 92,
+ NVG_STAT_QUERY_C6_EXIT_LAST = 93,
+ NVG_STAT_QUERY_C7_EXIT_LAST = 94
} tegra_nvg_stat_query_t;
-
typedef enum {
- TEGRA_NVG_CORE_C0 = 0,
- TEGRA_NVG_CORE_C1 = 1,
- TEGRA_NVG_CORE_C6 = 6,
- TEGRA_NVG_CORE_C7 = 7,
- TEGRA_NVG_CORE_WARMRSTREQ = 8,
+ TEGRA_NVG_CORE_C0 = 0,
+ TEGRA_NVG_CORE_C1 = 1,
+ TEGRA_NVG_CORE_C6 = 6,
+ TEGRA_NVG_CORE_C7 = 7,
+ TEGRA_NVG_CORE_WARMRSTREQ = 8
} tegra_nvg_core_sleep_state_t;
typedef enum {
- TEGRA_NVG_CLUSTER_CC0 = 0,
- TEGRA_NVG_CLUSTER_CC6 = 6,
+ TEGRA_NVG_CLUSTER_CC0 = 0,
+ TEGRA_NVG_CLUSTER_CC6 = 6
} tegra_nvg_cluster_sleep_state_t;
typedef enum {
- TEGRA_NVG_CCPLEX_CG0 = 0,
- TEGRA_NVG_CCPLEX_CG7 = 1,
-
+ TEGRA_NVG_CG_CG0 = 0,
+ TEGRA_NVG_CG_CG7 = 7
} tegra_nvg_cluster_group_sleep_state_t;
typedef enum {
- TEGRA_NVG_SYSTEM_SC0 = 0,
- TEGRA_NVG_SYSTEM_SC7 = 7,
- TEGRA_NVG_SYSTEM_SC8 = 8,
+ TEGRA_NVG_SYSTEM_SC0 = 0,
+ TEGRA_NVG_SYSTEM_SC7 = 7,
+ TEGRA_NVG_SYSTEM_SC8 = 8
} tegra_nvg_system_sleep_state_t;
// ---------------------------------------------------------------------------
// NVG Data subformats
// ---------------------------------------------------------------------------
-typedef union
-{
- uint64_t flat;
- struct nvg_version_channel_t {
- uint64_t minor_version : 32;
- uint64_t major_version : 32;
- } bits;
+typedef union {
+ uint64_t flat;
+ struct nvg_version_channel_t {
+ uint32_t minor_version : 32;
+ uint32_t major_version : 32;
+ } bits;
} nvg_version_data_t;
-typedef union nvg_channel_1_data_u
-{
- uint64_t flat;
- struct nvg_channel_1_data_s
- {
- uint64_t perf_per_watt_mode : 1;
- uint64_t reserved_63_1 : 63;
- } bits;
+typedef union {
+ uint64_t flat;
+ struct nvg_power_perf_channel_t {
+ uint32_t perf_per_watt : 1;
+ uint32_t reserved_31_1 : 31;
+ uint32_t reserved_63_32 : 32;
+ } bits;
+} nvg_power_perf_channel_t;
+
+typedef union {
+ uint64_t flat;
+ struct nvg_power_modes_channel_t {
+ uint32_t low_battery : 1;
+ uint32_t reserved_1_1 : 1;
+ uint32_t battery_save : 1;
+ uint32_t reserved_31_3 : 29;
+ uint32_t reserved_63_32 : 32;
+ } bits;
+} nvg_power_modes_channel_t;
+
+typedef union nvg_channel_1_data_u {
+ uint64_t flat;
+ struct nvg_channel_1_data_s {
+ uint32_t perf_per_watt_mode : 1;
+ uint32_t reserved_31_1 : 31;
+ uint32_t reserved_63_32 : 32;
+ } bits;
} nvg_channel_1_data_t;
-typedef union nvg_channel_2_data_u
-{
- uint64_t flat;
- struct nvg_channel_2_data_s
- {
- uint64_t reserved_1_0 : 2;
- uint64_t battery_saver_mode : 1;
- uint64_t reserved_63_3 : 61;
- } bits;
+typedef union {
+ uint64_t flat;
+ struct nvg_ccplex_cache_control_channel_t {
+ uint32_t gpu_ways : 5;
+ uint32_t reserved_7_5 : 3;
+ uint32_t gpu_only_ways : 5;
+ uint32_t reserved_31_13 : 19;
+ uint32_t reserved_63_32 : 32;
+ } bits;
+} nvg_ccplex_cache_control_channel_t;
+
+typedef union nvg_channel_2_data_u {
+ uint64_t flat;
+ struct nvg_channel_2_data_s {
+ uint32_t reserved_1_0 : 2;
+ uint32_t battery_saver_mode : 1;
+ uint32_t reserved_31_3 : 29;
+ uint32_t reserved_63_32 : 32;
+ } bits;
} nvg_channel_2_data_t;
-typedef union
-{
- uint64_t flat;
- struct nvg_wake_time_channel_t {
- uint64_t wake_time : 32;
- uint64_t reserved_63_32 : 32;
- } bits;
+typedef union {
+ uint64_t flat;
+ struct nvg_wake_time_channel_t {
+ uint32_t wake_time : 32;
+ uint32_t reserved_63_32 : 32;
+ } bits;
} nvg_wake_time_channel_t;
-typedef union
-{
- uint64_t flat;
- struct nvg_cstate_info_channel_t {
- uint64_t cluster_state : 3;
- uint64_t reserved_6_3 : 4;
- uint64_t update_cluster : 1;
- uint64_t cg_cstate : 3;
- uint64_t reserved_14_11 : 4;
- uint64_t update_cg : 1;
- uint64_t system_cstate : 4;
- uint64_t reserved_22_20 : 3;
- uint64_t update_system : 1;
- uint64_t reserved_30_24 : 7;
- uint64_t update_wake_mask : 1;
- uint64_t wake_mask : 32;
- } bits;
+typedef union {
+ uint64_t flat;
+ struct nvg_cstate_info_channel_t {
+ uint32_t cluster_state : 3;
+ uint32_t reserved_6_3 : 4;
+ uint32_t update_cluster : 1;
+ uint32_t cg_cstate : 3;
+ uint32_t reserved_14_11 : 4;
+ uint32_t update_cg : 1;
+ uint32_t system_cstate : 4;
+ uint32_t reserved_22_20 : 3;
+ uint32_t update_system : 1;
+ uint32_t reserved_30_24 : 7;
+ uint32_t update_wake_mask : 1;
+ uint32_t wake_mask : 32;
+ } bits;
} nvg_cstate_info_channel_t;
-typedef union
-{
- uint64_t flat;
- struct nvg_lower_bound_channel_t {
- uint64_t crossover_value : 32;
- uint64_t reserved_63_32 : 32;
- } bits;
+typedef union {
+ uint64_t flat;
+ struct nvg_lower_bound_channel_t {
+ uint32_t crossover_value : 32;
+ uint32_t reserved_63_32 : 32;
+ } bits;
} nvg_lower_bound_channel_t;
-
-typedef union
-{
- uint64_t flat;
- struct nvg_cstate_stat_query_channel_t {
- uint64_t unit_id : 4;
- uint64_t reserved_15_4 : 12;
- uint64_t stat_id : 16;
- uint64_t reserved_63_32 : 32;
- } bits;
+typedef union {
+ uint64_t flat;
+ struct nvg_cstate_stat_query_channel_t {
+ uint32_t unit_id : 4;
+ uint32_t reserved_15_4 : 12;
+ uint32_t stat_id : 16;
+ uint32_t reserved_63_32 : 32;
+ } bits;
} nvg_cstate_stat_query_channel_t;
-typedef union
-{
- uint64_t flat;
- struct nvg_is_sc7_allowed_channel_t {
- uint64_t is_sc7_allowed : 1;
- uint64_t reserved_63_32 : 63;
- } bits;
+typedef union {
+ uint64_t flat;
+ struct nvg_is_sc7_allowed_channel_t {
+ uint32_t is_sc7_allowed : 1;
+ uint32_t reserved_31_1 : 31;
+ uint32_t reserved_63_32 : 32;
+ } bits;
} nvg_is_sc7_allowed_channel_t;
-
-typedef union
-{
- uint64_t flat;
- struct nvg_core_online_channel_t {
- uint64_t core_id : 4;
- uint64_t reserved_63_4 : 60;
- } bits;
+typedef union {
+ uint64_t flat;
+ struct nvg_core_online_channel_t {
+ uint32_t core_id : 4;
+ uint32_t reserved_31_4 : 28;
+ uint32_t reserved_63_32 : 32;
+ } bits;
} nvg_core_online_channel_t;
-
-typedef union
-{
- uint64_t flat;
- struct nvg_cc3_control_channel_t {
- uint64_t freq_req : 8;
- uint64_t reserved_30_8 : 23;
- uint64_t enable : 1;
- uint64_t reserved_63_32 : 32;
- } bits;
+typedef union {
+ uint64_t flat;
+ struct nvg_cc3_control_channel_t {
+ uint32_t freq_req : 8;
+ uint32_t reserved_30_8 : 23;
+ uint32_t enable : 1;
+ uint32_t reserved_63_32 : 32;
+ } bits;
} nvg_cc3_control_channel_t;
-
-typedef union
-{
- uint64_t flat;
- struct nvg_update_gsc_channel_t {
- uint64_t gsc_enum : 16;
- uint64_t reserved_63_16 : 48;
- } bits;
-} nvg_update_gsc_channel_t;
-
-
-typedef union
-{
- uint64_t flat;
- struct nvg_cache_inval_channel_t {
- uint64_t cache_clean : 1;
- uint64_t cache_clean_inval : 1;
- uint64_t cache_clean_inval_tr : 1;
- uint64_t reserved_63_3 : 61;
- } bits;
-} nvg_cache_inval_channel_t;
-
-
-/* GSC type define */
typedef enum {
- TEGRA_NVG_GSC_ALL=0,
- TEGRA_NVG_GSC_NVDEC=1,
- TEGRA_NVG_GSC_WPR1=2,
- TEGRA_NVG_GSC_WPR2=3,
- TEGRA_NVG_GSC_TSECA=4,
- TEGRA_NVG_GSC_TSECB=5,
-
- TEGRA_NVG_GSC_BPMP=6,
- TEGRA_NVG_GSC_APE=7,
- TEGRA_NVG_GSC_SPE=8,
- TEGRA_NVG_GSC_SCE=9,
- TEGRA_NVG_GSC_APR=10,
- TEGRA_NVG_GSC_TZRAM=11,
- TEGRA_NVG_GSC_SE=12,
-
- TEGRA_NVG_GSC_DMCE=13,
- TEGRA_NVG_GSC_BPMP_TO_DMCE=14,
- TEGRA_NVG_GSC_BPMP_TO_SPE=16,
- TEGRA_NVG_GSC_CPU_TZ_TO_BPMP=18,
- TEGRA_NVG_GSC_CPU_NS_TO_BPMP=20,
- TEGRA_NVG_GSC_IPC_SE_SPE_SCE_BPMP=22,
- TEGRA_NVG_GSC_SC7_RESUME_FW=23,
-
- TEGRA_NVG_GSC_VPR_RESIZE=24,
- TEGRA_NVG_GSC_RCE=25,
- TEGRA_NVG_GSC_CV=26,
-
- TEGRA_NVG_GSC_BO_MTS_PACKAGE=28,
- TEGRA_NVG_GSC_BO_MCE_PREBOOT=29,
-
- TEGRA_NVG_GSC_TZ_DRAM_IDX=34,
- TEGRA_NVG_GSC_VPR_IDX=35,
-} tegra_nvg_gsc_index_t;
-
-typedef enum {
- TEGRA_NVG_CROSSOVER_C6 = 0,
- TEGRA_NVG_CROSSOVER_CC6 = 1,
- TEGRA_NVG_CROSSOVER_CG7 = 2,
-} tegra_nvg_crossover_index_t;
-
-#endif // T194_NVG_H
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35,
+ TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX
+} tegra_nvg_channel_update_gsc_gsc_enum_t;
+
+typedef union {
+ uint64_t flat;
+ struct nvg_update_ccplex_gsc_channel_t {
+ uint32_t gsc_enum : 16;
+ uint32_t reserved_31_16 : 16;
+ uint32_t reserved_63_32 : 32;
+ } bits;
+} nvg_update_ccplex_gsc_channel_t;
+
+typedef union {
+ uint64_t flat;
+ struct nvg_security_config_channel_t {
+ uint32_t strict_checking_enabled : 1;
+ uint32_t strict_checking_locked : 1;
+ uint32_t reserved_31_2 : 30;
+ uint32_t reserved_63_32 : 32;
+ } bits;
+} nvg_security_config_t;
+
+typedef union {
+ uint64_t flat;
+ struct nvg_shutdown_channel_t {
+ uint32_t reboot : 1;
+ uint32_t reserved_31_1 : 31;
+ uint32_t reserved_63_32 : 32;
+ } bits;
+} nvg_shutdown_t;
+
+#endif
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S b/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S
index e6a6a998020cb5f55d9d19832273b59d6c4e165c..3c47208a10229104e74a7e5992a0fd13036fff95 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S
@@ -10,6 +10,9 @@
.globl nvg_set_request_data
.globl nvg_set_request
.globl nvg_get_result
+ .globl nvg_cache_clean
+ .globl nvg_cache_clean_inval
+ .globl nvg_cache_inval_all
/* void nvg_set_request_data(uint64_t req, uint64_t data) */
func nvg_set_request_data
@@ -29,3 +32,21 @@ func nvg_get_result
mrs x0, s3_0_c15_c1_3
ret
endfunc nvg_get_result
+
+/* uint64_t nvg_cache_clean(void) */
+func nvg_cache_clean
+ mrs x0, s3_0_c15_c3_5
+ ret
+endfunc nvg_cache_clean
+
+/* uint64_t nvg_cache_clean_inval(void) */
+func nvg_cache_clean_inval
+ mrs x0, s3_0_c15_c3_6
+ ret
+endfunc nvg_cache_clean_inval
+
+/* uint64_t nvg_cache_inval_all(void) */
+func nvg_cache_inval_all
+ mrs x0, s3_0_c15_c3_7
+ ret
+endfunc nvg_cache_inval_all
\ No newline at end of file
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
index 0a6515e1ce1a4f48bb15b053cca8258e9682bcb0..ba8436be42eb1f94c852226c0ea75edaf832aaa7 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
@@ -14,13 +14,26 @@
#include <denver.h>
#include <mce.h>
#include <mce_private.h>
-#include <mmio.h>
#include <platform_def.h>
+#include <stdbool.h>
#include <string.h>
#include <errno.h>
#include <t194_nvg.h>
#include <tegra_def.h>
#include <tegra_platform.h>
+#include <tegra_private.h>
+
+/* Handler to check if MCE firmware is supported */
+static bool mce_firmware_not_supported(void)
+{
+ bool status;
+
+ /* these platforms do not load MCE firmware */
+ status = tegra_platform_is_linsim() || tegra_platform_is_qt() ||
+ tegra_platform_is_virt_dev_kit();
+
+ return status;
+}
/*******************************************************************************
* Common handler for all MCE commands
@@ -28,16 +41,10 @@
int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
uint64_t arg2)
{
- uint64_t ret64 = 0, arg3, arg4, arg5;
int32_t ret = 0;
- cpu_context_t *ctx = cm_get_context(NON_SECURE);
- gp_regs_t *gp_regs = get_gpregs_ctx(ctx);
-
- assert(ctx);
- assert(gp_regs);
switch (cmd) {
- case MCE_CMD_ENTER_CSTATE:
+ case (uint64_t)MCE_CMD_ENTER_CSTATE:
ret = nvg_enter_cstate((uint32_t)arg0, (uint32_t)arg1);
if (ret < 0) {
ERROR("%s: enter_cstate failed(%d)\n", __func__, ret);
@@ -45,68 +52,15 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
break;
- case MCE_CMD_UPDATE_CSTATE_INFO:
- /*
- * get the parameters required for the update cstate info
- * command
- */
- arg3 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X4));
- arg4 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X5));
- arg5 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X6));
-
- /* arg0 cluster
- * arg1 ccplex
- * arg2 system
- * arg3 sys_state_force => T19x not support
- * arg4 wake_mask
- * arg5 update_wake_mask
- */
- nvg_update_cstate_info((uint32_t)arg0, (uint32_t)arg1,
- (uint32_t)arg2, (uint32_t)arg4, (uint8_t)arg5);
-
- write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X4), (arg3));
- write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X5), (arg4));
- write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X6), (arg5));
-
- break;
-
- case MCE_CMD_UPDATE_CROSSOVER_TIME:
- ret = nvg_update_crossover_time((uint32_t)arg0, (uint32_t)arg1);
- if (ret < 0) {
- ERROR("%s: update_crossover_time failed(%d)\n",
- __func__, ret);
- }
-
- break;
-
- case MCE_CMD_READ_CSTATE_STATS:
- ret64 = nvg_get_cstate_stat_query_value();
-
- /* update context to return cstate stats value */
- write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), (ret64));
- write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X2), (ret64));
-
- break;
-
- case MCE_CMD_WRITE_CSTATE_STATS:
- ret = nvg_set_cstate_stat_query_value(arg0);
-
- break;
-
- case MCE_CMD_IS_SC7_ALLOWED:
+ case (uint64_t)MCE_CMD_IS_SC7_ALLOWED:
ret = nvg_is_sc7_allowed();
if (ret < 0) {
ERROR("%s: is_sc7_allowed failed(%d)\n", __func__, ret);
- break;
}
- /* update context to return SC7 status value */
- write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), ((uint64_t)ret));
- write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X3), ((uint64_t)ret));
-
break;
- case MCE_CMD_ONLINE_CORE:
+ case (uint64_t)MCE_CMD_ONLINE_CORE:
ret = nvg_online_core((uint32_t)arg0);
if (ret < 0) {
ERROR("%s: online_core failed(%d)\n", __func__, ret);
@@ -114,55 +68,9 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
break;
- case MCE_CMD_CC3_CTRL:
- ret = nvg_cc3_ctrl((uint32_t)arg0, (uint8_t)arg2);
- if (ret < 0) {
- ERROR("%s: cc3_ctrl failed(%d)\n", __func__, ret);
- }
-
- break;
-
- case MCE_CMD_READ_VERSIONS:
- /* get the MCE firmware version */
- ret64 = nvg_get_version();
-
- /*
- * version = minor(63:32) | major(31:0). Update context
- * to return major and minor version number.
- */
- write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), (ret64 & (uint64_t)0xFFFF));
- write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X2), (ret64 >> 32));
-
- break;
-
- case MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
- ret = nvg_roc_clean_cache_trbits();
- if (ret < 0) {
- ERROR("%s: flush cache_trbits failed(%d)\n", __func__,
- ret);
- }
-
- break;
-
- case MCE_CMD_ROC_FLUSH_CACHE:
- ret = nvg_roc_flush_cache();
- if (ret < 0) {
- ERROR("%s: flush cache failed(%d)\n", __func__, ret);
- }
-
- break;
-
- case MCE_CMD_ROC_CLEAN_CACHE:
- ret = nvg_roc_clean_cache();
- if (ret < 0) {
- ERROR("%s: clean cache failed(%d)\n", __func__, ret);
- }
-
- break;
-
default:
ERROR("unknown MCE command (%llu)\n", cmd);
- ret = EINVAL;
+ ret = -EINVAL;
break;
}
@@ -174,7 +82,18 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
******************************************************************************/
int32_t mce_update_gsc_videomem(void)
{
- return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_VPR_IDX);
+ int32_t ret;
+
+ /*
+ * MCE firmware is not running on simulation platforms.
+ */
+ if (mce_firmware_not_supported()) {
+ ret = -EINVAL;
+ } else {
+ ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR);
+ }
+
+ return ret;
}
/*******************************************************************************
@@ -182,7 +101,18 @@ int32_t mce_update_gsc_videomem(void)
******************************************************************************/
int32_t mce_update_gsc_tzdram(void)
{
- return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_TZ_DRAM_IDX);
+ int32_t ret;
+
+ /*
+ * MCE firmware is not running on simulation platforms.
+ */
+ if (mce_firmware_not_supported()) {
+ ret = -EINVAL;
+ } else {
+ ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM);
+ }
+
+ return ret;
}
/*******************************************************************************
@@ -190,7 +120,18 @@ int32_t mce_update_gsc_tzdram(void)
******************************************************************************/
int32_t mce_update_gsc_tzram(void)
{
- return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_TZRAM);
+ int32_t ret;
+
+ /*
+ * MCE firmware is not running on simulation platforms.
+ */
+ if (mce_firmware_not_supported()) {
+ ret = -EINVAL;
+ } else {
+ ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM);
+ }
+
+ return ret;
}
/*******************************************************************************
@@ -215,9 +156,7 @@ void mce_verify_firmware_version(void)
/*
* MCE firmware is not running on simulation platforms.
*/
- if ((tegra_platform_is_linsim() == 1U) ||
- (tegra_platform_is_virt_dev_kit() == 1U) ||
- (tegra_platform_is_qt() == 1U)) {
+ if (mce_firmware_not_supported()) {
return;
}
@@ -229,8 +168,8 @@ void mce_verify_firmware_version(void)
minor = (uint32_t)version;
major = (uint32_t)(version >> 32);
- INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor,
- 0, 0);
+ INFO("MCE Version - HW=%u:%u, SW=%u:%u\n", major, minor,
+ TEGRA_NVG_VERSION_MAJOR, TEGRA_NVG_VERSION_MINOR);
/*
* Verify that the MCE firmware version and the interface header
@@ -246,3 +185,53 @@ void mce_verify_firmware_version(void)
panic();
}
}
+
+/*******************************************************************************
+ * Handler to enable the strict checking mode
+ ******************************************************************************/
+void mce_enable_strict_checking(void)
+{
+ uint64_t sctlr = read_sctlr_el3();
+ int32_t ret = 0;
+
+ if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
+ /*
+ * Step1: TZ-DRAM and TZRAM should be setup before the MMU is
+ * enabled.
+ *
+ * The common code makes sure that TZDRAM/TZRAM are already
+ * enabled before calling into this handler. If this is not the
+ * case, the following sequence must be executed before moving
+ * on to step 2.
+ *
+ * tlbialle1is();
+ * tlbialle3is();
+ * dsbsy();
+ * isb();
+ *
+ */
+ if ((sctlr & (uint64_t)SCTLR_M_BIT) == (uint64_t)SCTLR_M_BIT) {
+ tlbialle1is();
+ tlbialle3is();
+ dsbsy();
+ isb();
+ }
+
+ /*
+ * Step2: SCF flush - Clean and invalidate caches and clear the
+ * TR-bits
+ */
+ ret = nvg_roc_clean_cache_trbits();
+ if (ret < 0) {
+ ERROR("%s: flush cache_trbits failed(%d)\n", __func__,
+ ret);
+ return;
+ }
+
+ /*
+ * Step3: Issue the SECURITY_CONFIG request to MCE to enable
+ * strict checking mode.
+ */
+ nvg_enable_strict_checking_mode();
+ }
+}
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
index 12dd6cb09fe31cf2a70c846c025768b3f467a01b..1dd1f51b906fc6d9869cb7a8d540fd09dbbe588b 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
@@ -13,11 +13,10 @@
#include <mce_private.h>
#include <platform_def.h>
#include <t194_nvg.h>
+#include <tegra_private.h>
-extern void nvg_set_request_data(uint64_t req, uint64_t data);
-extern void nvg_set_request(uint64_t req);
-extern uint64_t nvg_get_result(void);
-
+#define ID_AFR0_EL1_CACHE_OPS_SHIFT 12
+#define ID_AFR0_EL1_CACHE_OPS_MASK 0xFU
/*
* Reports the major and minor version of this interface.
*
@@ -26,7 +25,7 @@ extern uint64_t nvg_get_result(void);
*/
uint64_t nvg_get_version(void)
{
- nvg_set_request(TEGRA_NVG_CHANNEL_VERSION);
+ nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_VERSION);
return (uint64_t)nvg_get_result();
}
@@ -38,7 +37,7 @@ uint64_t nvg_get_version(void)
*/
int32_t nvg_enable_power_perf_mode(void)
{
- nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_PERF, 1U);
+ nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 1U);
return 0;
}
@@ -50,7 +49,7 @@ int32_t nvg_enable_power_perf_mode(void)
*/
int32_t nvg_disable_power_perf_mode(void)
{
- nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_PERF, 0U);
+ nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 0U);
return 0;
}
@@ -62,7 +61,7 @@ int32_t nvg_disable_power_perf_mode(void)
*/
int32_t nvg_enable_power_saver_modes(void)
{
- nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_MODES, 1U);
+ nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 1U);
return 0;
}
@@ -74,7 +73,7 @@ int32_t nvg_enable_power_saver_modes(void)
*/
int32_t nvg_disable_power_saver_modes(void)
{
- nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_MODES, 0U);
+ nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 0U);
return 0;
}
@@ -88,7 +87,7 @@ int32_t nvg_disable_power_saver_modes(void)
void nvg_set_wake_time(uint32_t wake_time)
{
/* time (TSC ticks) until the core is expected to get a wake event */
- nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time);
+ nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time);
}
/*
@@ -97,7 +96,7 @@ void nvg_set_wake_time(uint32_t wake_time)
*
* NVGDATA[0:2]: SW(RW), CLUSTER_CSTATE
* NVGDATA[7]: SW(W), update cluster flag
- * NVGDATA[8:9]: SW(RW), CG_CSTATE
+ * NVGDATA[8:10]: SW(RW), CG_CSTATE
* NVGDATA[15]: SW(W), update ccplex flag
* NVGDATA[16:19]: SW(RW), SYSTEM_CSTATE
* NVGDATA[23]: SW(W), update system flag
@@ -136,77 +135,7 @@ void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex,
val |= ((uint64_t)wake_mask & CSTATE_WAKE_MASK_CLEAR) << CSTATE_WAKE_MASK_SHIFT;
/* set the updated cstate info */
- nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_INFO, val);
-}
-
-/*
- * Indices gives MTS the crossover point in TSC ticks for when it becomes
- * no longer viable to enter the named state
- *
- * Type 0 : NVGDATA[0:31]: C6 Lower bound
- * Type 1 : NVGDATA[0:31]: CC6 Lower bound
- * Type 2 : NVGDATA[0:31]: CG7 Lower bound
- */
-int32_t nvg_update_crossover_time(uint32_t type, uint32_t time)
-{
- int32_t ret = 0;
-
- switch (type) {
- case TEGRA_NVG_CROSSOVER_C6:
- nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND,
- (uint64_t)time);
- break;
-
- case TEGRA_NVG_CROSSOVER_CC6:
- nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND,
- (uint64_t)time);
- break;
-
- case TEGRA_NVG_CROSSOVER_CG7:
- nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND,
- (uint64_t)time);
- break;
-
- default:
- ERROR("%s: unknown crossover type (%d)\n", __func__, type);
- ret = EINVAL;
- break;
- }
-
- return ret;
-}
-
-/*
- * These NVG calls allow ARM SW to access CSTATE statistical information
- *
- * NVGDATA[0:3]: SW(RW) Core/cluster/cg id
- * NVGDATA[16:31]: SW(RW) Stat id
- */
-int32_t nvg_set_cstate_stat_query_value(uint64_t data)
-{
- int32_t ret = 0;
-
- /* sanity check stat id */
- if (data > (uint64_t)NVG_STAT_QUERY_C7_RESIDENCY_SUM) {
- ERROR("%s: unknown stat id (%d)\n", __func__, (uint32_t)data);
- ret = EINVAL;
- } else {
- nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST, data);
- }
-
- return ret;
-}
-
-/*
- * The read-only value associated with the CSTATE_STAT_QUERY_REQUEST
- *
- * NVGDATA[0:63]: SW(R) Stat count
- */
-uint64_t nvg_get_cstate_stat_query_value(void)
-{
- nvg_set_request(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE);
-
- return (uint64_t)nvg_get_result();
+ nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val);
}
/*
@@ -217,7 +146,7 @@ uint64_t nvg_get_cstate_stat_query_value(void)
int32_t nvg_is_sc7_allowed(void)
{
/* issue command to check if SC7 is allowed */
- nvg_set_request(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED);
+ nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED);
/* 1 = SC7 allowed, 0 = SC7 not allowed */
return (int32_t)nvg_get_result();
@@ -239,42 +168,13 @@ int32_t nvg_online_core(uint32_t core)
ret = EINVAL;
} else {
/* get a core online */
- nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE,
- (uint64_t)core & MCE_CORE_ID_MASK);
+ nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE,
+ (uint64_t)core & MCE_CORE_ID_MASK);
}
return ret;
}
-/*
- * Enables and controls the voltage/frequency hint for CC3. CC3 is disabled
- * by default.
- *
- * NVGDATA[7:0] SW(RW) frequency request
- * NVGDATA[31:31] SW(RW) enable bit
- */
-int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable)
-{
- uint64_t val = 0;
-
- /*
- * If the enable bit is cleared, Auto-CC3 will be disabled by setting
- * the SW visible frequency request registers for all non
- * floorswept cores valid independent of StandbyWFI and disabling
- * the IDLE frequency request register. If set, Auto-CC3
- * will be enabled by setting the ARM SW visible frequency
- * request registers for all non floorswept cores to be enabled by
- * StandbyWFI or the equivalent signal, and always keeping the IDLE
- * frequency request register enabled.
- */
- if (enable != 0U) {
- val = ((uint64_t)freq & MCE_AUTO_CC3_FREQ_MASK) | MCE_AUTO_CC3_ENABLE_BIT;
- }
- nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, val);
-
- return 0;
-}
-
/*
* MC GSC (General Security Carveout) register values are expected to be
* changed by TrustZone ARM code after boot.
@@ -283,14 +183,14 @@ int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable)
*/
int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx)
{
- int32_t ret = 0;
+ int32_t ret;
/* sanity check GSC ID */
- if (gsc_idx > (uint32_t)TEGRA_NVG_GSC_VPR_IDX) {
- ERROR("%s: unknown gsc_idx (%d)\n", __func__, gsc_idx);
+ if (gsc_idx > (uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR) {
+ ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx);
ret = EINVAL;
} else {
- nvg_set_request_data(TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC,
+ nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC,
(uint64_t)gsc_idx);
}
@@ -299,41 +199,62 @@ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx)
/*
* Cache clean operation for all CCPLEX caches.
- *
- * NVGDATA[0] cache_clean
*/
int32_t nvg_roc_clean_cache(void)
{
- nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
- (uint64_t)CACHE_CLEAN_SET);
+ int32_t ret = 0;
- return 0;
+ /* check if cache flush through mts is supported */
+ if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
+ ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
+ if (nvg_cache_clean() == 0U) {
+ ERROR("%s: failed\n", __func__);
+ ret = EINVAL;
+ }
+ } else {
+ ret = EINVAL;
+ }
+ return ret;
}
/*
* Cache clean and invalidate operation for all CCPLEX caches.
- *
- * NVGDATA[1] cache_clean_inval
*/
int32_t nvg_roc_flush_cache(void)
{
- nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
- (uint64_t)CACHE_CLEAN_INVAL_SET);
+ int32_t ret = 0;
- return 0;
+ /* check if cache flush through mts is supported */
+ if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
+ ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
+ if (nvg_cache_clean_inval() == 0U) {
+ ERROR("%s: failed\n", __func__);
+ ret = EINVAL;
+ }
+ } else {
+ ret = EINVAL;
+ }
+ return ret;
}
/*
* Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches.
- *
- * NVGDATA[2] cache_clean_inval_tr
*/
int32_t nvg_roc_clean_cache_trbits(void)
{
- nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
- (uint64_t)CACHE_CLEAN_INVAL_TR_SET);
+ int32_t ret = 0;
- return 0;
+ /* check if cache flush through mts is supported */
+ if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
+ ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
+ if (nvg_cache_inval_all() == 0U) {
+ ERROR("%s: failed\n", __func__);
+ ret = EINVAL;
+ }
+ } else {
+ ret = EINVAL;
+ }
+ return ret;
}
/*
@@ -342,6 +263,7 @@ int32_t nvg_roc_clean_cache_trbits(void)
int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time)
{
int32_t ret = 0;
+ uint64_t val = 0ULL;
/* check for allowed power state */
if ((state != (uint32_t)TEGRA_NVG_CORE_C0) &&
@@ -356,8 +278,22 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time)
nvg_set_wake_time(wake_time);
/* set the core cstate */
- write_actlr_el1(state);
+ val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
+ write_actlr_el1(val | (uint64_t)state);
}
return ret;
}
+
+/*
+ * Enable strict checking mode
+ *
+ * NVGDATA[3] strict_check ON + lock
+ */
+void nvg_enable_strict_checking_mode(void)
+{
+ uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET |
+ STRICT_CHECKING_LOCKED_SET);
+
+ nvg_set_request_data(TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params);
+}
diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se.c b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
new file mode 100644
index 0000000000000000000000000000000000000000..3df670c922a260c06841fb361c3c6b0e62ae10a4
--- /dev/null
+++ b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stdbool.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+#include <tegra_platform.h>
+
+#include "se_private.h"
+
+/*******************************************************************************
+ * Constants and Macros
+ ******************************************************************************/
+#define ERR_STATUS_SW_CLEAR U(0xFFFFFFFF)
+#define INT_STATUS_SW_CLEAR U(0xFFFFFFFF)
+#define MAX_TIMEOUT_MS U(100) /* Timeout in 100ms */
+#define NUM_SE_REGS_TO_SAVE U(4)
+
+/*******************************************************************************
+ * Data structure and global variables
+ ******************************************************************************/
+static uint32_t se_regs[NUM_SE_REGS_TO_SAVE];
+
+/*
+ * Check that SE operation has completed after kickoff.
+ *
+ * This function is invoked after an SE operation has been started,
+ * and it checks the following conditions:
+ *
+ * 1. SE_STATUS = IDLE
+ * 2. AHB bus data transfer is complete.
+ * 3. SE_ERR_STATUS is clean.
+ */
+static bool tegra_se_is_operation_complete(void)
+{
+ uint32_t val = 0, timeout = 0, sha_status, aes_status;
+ int32_t ret = 0;
+ bool se_is_busy, txn_has_errors, txn_successful;
+
+ /*
+ * Poll the status register to check if the operation
+ * completed.
+ */
+ do {
+ val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS);
+ se_is_busy = !!(val & CTX_SAVE_AUTO_SE_BUSY);
+
+ /* sleep until SE finishes */
+ if (se_is_busy) {
+ mdelay(1);
+ timeout++;
+ }
+
+ } while (se_is_busy && (timeout < MAX_TIMEOUT_MS));
+
+ /* any transaction errors? */
+ txn_has_errors = (tegra_se_read_32(SHA_ERR_STATUS) != 0U) ||
+ (tegra_se_read_32(AES0_ERR_STATUS) != 0U);
+
+ /* transaction successful? */
+ sha_status = tegra_se_read_32(SHA_INT_STATUS) & SHA_SE_OP_DONE;
+ aes_status = tegra_se_read_32(AES0_INT_STATUS) & AES0_SE_OP_DONE;
+ txn_successful = (sha_status == SHA_SE_OP_DONE) &&
+ (aes_status == AES0_SE_OP_DONE);
+
+ if ((timeout == MAX_TIMEOUT_MS) || txn_has_errors || !txn_successful) {
+ ERROR("%s: Atomic context save operation failed!\n",
+ __func__);
+ ret = -ECANCELED;
+ }
+
+ return (ret == 0);
+}
+
+/*
+ * Wait for SE engine to be idle and clear any pending interrupts, before
+ * starting the next SE operation.
+ */
+static bool tegra_se_is_ready(void)
+{
+ int32_t ret = 0;
+ uint32_t val = 0, timeout = 0;
+ bool se_is_ready;
+
+ /* Wait for previous operation to finish */
+ do {
+ val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS);
+ se_is_ready = (val == CTX_SAVE_AUTO_SE_READY);
+
+ /* sleep until SE is ready */
+ if (!se_is_ready) {
+ mdelay(1);
+ timeout++;
+ }
+
+ } while (!se_is_ready && (timeout < MAX_TIMEOUT_MS));
+
+ if (timeout == MAX_TIMEOUT_MS) {
+ ERROR("%s: SE is not ready!\n", __func__);
+ ret = -ETIMEDOUT;
+ }
+
+ /* Clear any pending interrupts from previous operation */
+ tegra_se_write_32(AES0_INT_STATUS, INT_STATUS_SW_CLEAR);
+ tegra_se_write_32(AES1_INT_STATUS, INT_STATUS_SW_CLEAR);
+ tegra_se_write_32(RSA_INT_STATUS, INT_STATUS_SW_CLEAR);
+ tegra_se_write_32(SHA_INT_STATUS, INT_STATUS_SW_CLEAR);
+
+ /* Clear error status for each engine seen from current port */
+ tegra_se_write_32(AES0_ERR_STATUS, ERR_STATUS_SW_CLEAR);
+ tegra_se_write_32(AES1_ERR_STATUS, ERR_STATUS_SW_CLEAR);
+ tegra_se_write_32(RSA_ERR_STATUS, ERR_STATUS_SW_CLEAR);
+ tegra_se_write_32(SHA_ERR_STATUS, ERR_STATUS_SW_CLEAR);
+
+ return (ret == 0);
+}
+
+/*
+ * During System Suspend, this handler triggers the hardware context
+ * save operation.
+ */
+static int32_t tegra_se_save_context(void)
+{
+ int32_t ret = -ECANCELED;
+
+ /*
+ * 1. Ensure all SE Driver including RNG1/PKA1 are shut down.
+ * TSEC/R5s are powergated/idle. All tasks on SE1~SE4, RNG1,
+ * PKA1 are wrapped up. SE0 is ready for use.
+ * 2. Clear interrupt/error in SE0 status register.
+ * 3. Scrub SE0 register to avoid false failure for illegal
+ * configuration. Probably not needed, dependent on HW
+ * implementation.
+ * 4. Check SE is ready for HW CTX_SAVE by polling
+ * SE_CTX_SAVE_AUTO_STATUS.SE_READY.
+ *
+ * Steps 1-4 are executed by tegra_se_is_ready().
+ *
+ * 5. Issue context save command.
+ * 6. Check SE is busy with CTX_SAVE, the command in step5 was not
+ * dropped for ongoing traffic in any of SE port/engine.
+ * 7. Poll SE register or wait for SE APB interrupt for task completion
+ * a. Polling: Read SE_CTX_SAVE_AUTO_STATUS.BUSY till it reports IDLE
+ * b. Interrupt: After receiving interrupt from SE APB, read
+ * SE_CTX_SAVE_AUTO_STATUS.BUSY till it reports IDLE.
+ * 8. Check AES0 and SHA ERR_STATUS to ensure no error case.
+ * 9. Check AES0 and SHA INT_STATUS to ensure operation has successfully
+ * completed.
+ *
+ * Steps 6-9 are executed by tegra_se_is_operation_complete().
+ */
+ if (tegra_se_is_ready()) {
+
+ /* Issue context save command */
+ tegra_se_write_32(AES0_OPERATION, SE_OP_CTX_SAVE);
+
+ /* Wait for operation to finish */
+ if (tegra_se_is_operation_complete()) {
+ ret = 0;
+ }
+ }
+
+ return ret;
+}
+
+/*
+ * Handler to power down the SE hardware blocks - SE, RNG1 and PKA1. This
+ * needs to be called only during System Suspend.
+ */
+int32_t tegra_se_suspend(void)
+{
+ int32_t ret = 0;
+
+ /* save SE registers */
+ se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT);
+ se_regs[1] = mmio_read_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL);
+ se_regs[2] = mmio_read_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT);
+ se_regs[3] = mmio_read_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT);
+
+ /* Save SE context. The BootROM restores it during System Resume */
+ ret = tegra_se_save_context();
+ if (ret != 0) {
+ ERROR("%s: context save failed (%d)\n", __func__, ret);
+ }
+
+ return ret;
+}
+
+/*
+ * Handler to power up the SE hardware block(s) during System Resume.
+ */
+void tegra_se_resume(void)
+{
+ /*
+ * When TZ takes over after System Resume, TZ should first reconfigure
+ * SE_MUTEX_WATCHDOG_NS_LIMIT, PKA1_MUTEX_WATCHDOG_NS_LIMIT,
+ * RNG1_MUTEX_WATCHDOG_NS_LIMIT and SE_ENTROPY_SRC_AGE_CTRL before
+ * other operations.
+ */
+ mmio_write_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT, se_regs[0]);
+ mmio_write_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL, se_regs[1]);
+ mmio_write_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[2]);
+ mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]);
+}
diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h
new file mode 100644
index 0000000000000000000000000000000000000000..7d531bb9de9606dd6f35b8b6252e5761fd958a30
--- /dev/null
+++ b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SE_PRIVATE_H__
+#define __SE_PRIVATE_H__
+
+#include <lib/utils_def.h>
+
+/* SE0_INT_ENABLE_0 */
+#define SE0_INT_ENABLE U(0x88)
+#define SE0_DISABLE_ALL_INT U(0x0)
+
+/* SE0_INT_STATUS_0 */
+#define SE0_INT_STATUS U(0x8C)
+#define SE0_CLEAR_ALL_INT_STATUS U(0x3F)
+
+/* SE0_SHA_INT_STATUS_0 */
+#define SHA_INT_STATUS U(0x184)
+#define SHA_SE_OP_DONE (U(1) << 4)
+
+/* SE0_SHA_ERR_STATUS_0 */
+#define SHA_ERR_STATUS U(0x18C)
+
+/* SE0_AES0_INT_STATUS_0 */
+#define AES0_INT_STATUS U(0x2F0)
+#define AES0_SE_OP_DONE (U(1) << 4)
+
+/* SE0_AES0_ERR_STATUS_0 */
+#define AES0_ERR_STATUS U(0x2F8)
+
+/* SE0_AES1_INT_STATUS_0 */
+#define AES1_INT_STATUS U(0x4F0)
+
+/* SE0_AES1_ERR_STATUS_0 */
+#define AES1_ERR_STATUS U(0x4F8)
+
+/* SE0_RSA_INT_STATUS_0 */
+#define RSA_INT_STATUS U(0x758)
+
+/* SE0_RSA_ERR_STATUS_0 */
+#define RSA_ERR_STATUS U(0x760)
+
+/* SE0_AES0_OPERATION_0 */
+#define AES0_OPERATION U(0x238)
+#define OP_MASK_BITS U(0x7)
+#define SE_OP_CTX_SAVE U(0x3)
+
+/* SE0_AES0_CTX_SAVE_CONFIG_0 */
+#define CTX_SAVE_CONFIG U(0x2D4)
+
+/* SE0_AES0_CTX_SAVE_AUTO_STATUS_0 */
+#define CTX_SAVE_AUTO_STATUS U(0x300)
+#define CTX_SAVE_AUTO_SE_READY U(0xFF)
+#define CTX_SAVE_AUTO_SE_BUSY (U(0x1) << 31)
+
+/* SE0_AES0_CTX_SAVE_AUTO_CTRL_0 */
+#define CTX_SAVE_AUTO_CTRL U(0x304)
+#define SE_CTX_SAVE_AUTO_EN (U(0x1) << 0)
+#define SE_CTX_SAVE_AUTO_LOCK_EN (U(0x1) << 1)
+
+/* SE0_AES0_CTX_SAVE_AUTO_START_ADDR_0 */
+#define CTX_SAVE_AUTO_START_ADDR U(0x308)
+
+/* SE0_AES0_CTX_SAVE_AUTO_START_ADDR_HI_0 */
+#define CTX_SAVE_AUTO_START_ADDR_HI U(0x30C)
+
+/*******************************************************************************
+ * Inline functions definition
+ ******************************************************************************/
+
+static inline uint32_t tegra_se_read_32(uint32_t offset)
+{
+ return mmio_read_32(TEGRA_SE0_BASE + offset);
+}
+
+static inline void tegra_se_write_32(uint32_t offset, uint32_t val)
+{
+ mmio_write_32(TEGRA_SE0_BASE + offset, val);
+}
+
+#endif /* __SE_PRIVATE_H__ */
diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
new file mode 100644
index 0000000000000000000000000000000000000000..54dbe7cdb470a8e4ec801be302915b5710d7b9c1
--- /dev/null
+++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
@@ -0,0 +1,674 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <common/bl_common.h>
+#include <mce.h>
+#include <memctrl_v2.h>
+#include <tegra_mc_def.h>
+#include <tegra_platform.h>
+
+/*******************************************************************************
+ * Array to hold stream_id override config register offsets
+ ******************************************************************************/
+const static uint32_t tegra194_streamid_override_regs[] = {
+ MC_STREAMID_OVERRIDE_CFG_HDAR,
+ MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
+ MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
+ MC_STREAMID_OVERRIDE_CFG_SATAR,
+ MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
+ MC_STREAMID_OVERRIDE_CFG_HDAW,
+ MC_STREAMID_OVERRIDE_CFG_SATAW,
+ MC_STREAMID_OVERRIDE_CFG_ISPRA,
+ MC_STREAMID_OVERRIDE_CFG_ISPFALR,
+ MC_STREAMID_OVERRIDE_CFG_ISPWA,
+ MC_STREAMID_OVERRIDE_CFG_ISPWB,
+ MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
+ MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
+ MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
+ MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
+ MC_STREAMID_OVERRIDE_CFG_TSECSRD,
+ MC_STREAMID_OVERRIDE_CFG_TSECSWR,
+ MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
+ MC_STREAMID_OVERRIDE_CFG_SDMMCR,
+ MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
+ MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
+ MC_STREAMID_OVERRIDE_CFG_SDMMCW,
+ MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
+ MC_STREAMID_OVERRIDE_CFG_VICSRD,
+ MC_STREAMID_OVERRIDE_CFG_VICSWR,
+ MC_STREAMID_OVERRIDE_CFG_VIW,
+ MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
+ MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
+ MC_STREAMID_OVERRIDE_CFG_APER,
+ MC_STREAMID_OVERRIDE_CFG_APEW,
+ MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
+ MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
+ MC_STREAMID_OVERRIDE_CFG_SESRD,
+ MC_STREAMID_OVERRIDE_CFG_SESWR,
+ MC_STREAMID_OVERRIDE_CFG_AXIAPR,
+ MC_STREAMID_OVERRIDE_CFG_AXIAPW,
+ MC_STREAMID_OVERRIDE_CFG_ETRR,
+ MC_STREAMID_OVERRIDE_CFG_ETRW,
+ MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
+ MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
+ MC_STREAMID_OVERRIDE_CFG_AXISR,
+ MC_STREAMID_OVERRIDE_CFG_AXISW,
+ MC_STREAMID_OVERRIDE_CFG_EQOSR,
+ MC_STREAMID_OVERRIDE_CFG_EQOSW,
+ MC_STREAMID_OVERRIDE_CFG_UFSHCR,
+ MC_STREAMID_OVERRIDE_CFG_UFSHCW,
+ MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
+ MC_STREAMID_OVERRIDE_CFG_BPMPR,
+ MC_STREAMID_OVERRIDE_CFG_BPMPW,
+ MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
+ MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
+ MC_STREAMID_OVERRIDE_CFG_AONR,
+ MC_STREAMID_OVERRIDE_CFG_AONW,
+ MC_STREAMID_OVERRIDE_CFG_AONDMAR,
+ MC_STREAMID_OVERRIDE_CFG_AONDMAW,
+ MC_STREAMID_OVERRIDE_CFG_SCER,
+ MC_STREAMID_OVERRIDE_CFG_SCEW,
+ MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
+ MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
+ MC_STREAMID_OVERRIDE_CFG_APEDMAR,
+ MC_STREAMID_OVERRIDE_CFG_APEDMAW,
+ MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
+ MC_STREAMID_OVERRIDE_CFG_VICSRD1,
+ MC_STREAMID_OVERRIDE_CFG_NVDECSRD1,
+ MC_STREAMID_OVERRIDE_CFG_VIFALR,
+ MC_STREAMID_OVERRIDE_CFG_VIFALW,
+ MC_STREAMID_OVERRIDE_CFG_DLA0RDA,
+ MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB,
+ MC_STREAMID_OVERRIDE_CFG_DLA0WRA,
+ MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB,
+ MC_STREAMID_OVERRIDE_CFG_DLA1RDA,
+ MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB,
+ MC_STREAMID_OVERRIDE_CFG_DLA1WRA,
+ MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB,
+ MC_STREAMID_OVERRIDE_CFG_PVA0RDA,
+ MC_STREAMID_OVERRIDE_CFG_PVA0RDB,
+ MC_STREAMID_OVERRIDE_CFG_PVA0RDC,
+ MC_STREAMID_OVERRIDE_CFG_PVA0WRA,
+ MC_STREAMID_OVERRIDE_CFG_PVA0WRB,
+ MC_STREAMID_OVERRIDE_CFG_PVA0WRC,
+ MC_STREAMID_OVERRIDE_CFG_PVA1RDA,
+ MC_STREAMID_OVERRIDE_CFG_PVA1RDB,
+ MC_STREAMID_OVERRIDE_CFG_PVA1RDC,
+ MC_STREAMID_OVERRIDE_CFG_PVA1WRA,
+ MC_STREAMID_OVERRIDE_CFG_PVA1WRB,
+ MC_STREAMID_OVERRIDE_CFG_PVA1WRC,
+ MC_STREAMID_OVERRIDE_CFG_RCER,
+ MC_STREAMID_OVERRIDE_CFG_RCEW,
+ MC_STREAMID_OVERRIDE_CFG_RCEDMAR,
+ MC_STREAMID_OVERRIDE_CFG_RCEDMAW,
+ MC_STREAMID_OVERRIDE_CFG_NVENC1SRD,
+ MC_STREAMID_OVERRIDE_CFG_NVENC1SWR,
+ MC_STREAMID_OVERRIDE_CFG_PCIE0R,
+ MC_STREAMID_OVERRIDE_CFG_PCIE0W,
+ MC_STREAMID_OVERRIDE_CFG_PCIE1R,
+ MC_STREAMID_OVERRIDE_CFG_PCIE1W,
+ MC_STREAMID_OVERRIDE_CFG_PCIE2AR,
+ MC_STREAMID_OVERRIDE_CFG_PCIE2AW,
+ MC_STREAMID_OVERRIDE_CFG_PCIE3R,
+ MC_STREAMID_OVERRIDE_CFG_PCIE3W,
+ MC_STREAMID_OVERRIDE_CFG_PCIE4R,
+ MC_STREAMID_OVERRIDE_CFG_PCIE4W,
+ MC_STREAMID_OVERRIDE_CFG_PCIE5R,
+ MC_STREAMID_OVERRIDE_CFG_PCIE5W,
+ MC_STREAMID_OVERRIDE_CFG_ISPFALW,
+ MC_STREAMID_OVERRIDE_CFG_DLA0RDA1,
+ MC_STREAMID_OVERRIDE_CFG_DLA1RDA1,
+ MC_STREAMID_OVERRIDE_CFG_PVA0RDA1,
+ MC_STREAMID_OVERRIDE_CFG_PVA0RDB1,
+ MC_STREAMID_OVERRIDE_CFG_PVA1RDA1,
+ MC_STREAMID_OVERRIDE_CFG_PVA1RDB1,
+ MC_STREAMID_OVERRIDE_CFG_PCIE5R1,
+ MC_STREAMID_OVERRIDE_CFG_NVENCSRD1,
+ MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1,
+ MC_STREAMID_OVERRIDE_CFG_ISPRA1,
+ MC_STREAMID_OVERRIDE_CFG_MIU0R,
+ MC_STREAMID_OVERRIDE_CFG_MIU0W,
+ MC_STREAMID_OVERRIDE_CFG_MIU1R,
+ MC_STREAMID_OVERRIDE_CFG_MIU1W,
+ MC_STREAMID_OVERRIDE_CFG_MIU2R,
+ MC_STREAMID_OVERRIDE_CFG_MIU2W,
+ MC_STREAMID_OVERRIDE_CFG_MIU3R,
+ MC_STREAMID_OVERRIDE_CFG_MIU3W
+};
+
+/*******************************************************************************
+ * Array to hold the security configs for stream IDs
+ ******************************************************************************/
+const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = {
+ mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, ENABLE),
+};
+
+/*******************************************************************************
+ * Array to hold the transaction override configs
+ ******************************************************************************/
+const static mc_txn_override_cfg_t tegra194_txn_override_cfgs[] = {
+ mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(APEW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(AONW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR),
+};
+
+/* To be called by common memctrl_v2.c */
+static void tegra194_memctrl_reconfig_mss_clients(void)
+{
+ uint32_t reg_val, wdata_0, wdata_1, wdata_2;
+
+ wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB;
+ if (tegra_platform_is_silicon()) {
+ wdata_0 |= MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB;
+ }
+
+ tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
+
+ /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
+ do {
+ reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
+ } while ((reg_val & wdata_0) != wdata_0);
+
+ wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB|
+ MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB;
+ if (tegra_platform_is_silicon()) {
+ wdata_1 |= MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_RCE_FLUSH_ENB;
+ }
+ tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
+ /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
+ do {
+ reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
+ } while ((reg_val & wdata_1) != wdata_1);
+
+ wdata_2 = MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_AONDMA_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_BPMPDMA_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_SCEDMA_FLUSH_ENB;
+ if (tegra_platform_is_silicon()) {
+ wdata_2 |= MC_CLIENT_HOTRESET_CTRL2_RCEDMA_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_PCIE5A_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_PCIE3A_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_PCIE3_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_PCIE0A_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_PCIE0A2_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB;
+ }
+ tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2);
+ /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
+ do {
+ reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS2);
+ } while ((reg_val & wdata_2) != wdata_2);
+
+ /*
+ * Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and
+ * strongly ordered MSS clients.
+ *
+ * MC clients with default SO_DEV override still enabled at TSA:
+ * EQOSW, SATAW, XUSB_DEVW, XUSB_HOSTW, PCIe0w, PCIe1w, PCIe2w,
+ * PCIe3w, PCIe4w and PCIe5w.
+ */
+ mc_set_tsa_w_passthrough(AONDMAW);
+ mc_set_tsa_w_passthrough(AONW);
+ mc_set_tsa_w_passthrough(APEDMAW);
+ mc_set_tsa_w_passthrough(APEW);
+ mc_set_tsa_w_passthrough(AXISW);
+ mc_set_tsa_w_passthrough(BPMPDMAW);
+ mc_set_tsa_w_passthrough(BPMPW);
+ mc_set_tsa_w_passthrough(ETRW);
+ mc_set_tsa_w_passthrough(SCEDMAW);
+ mc_set_tsa_w_passthrough(RCEDMAW);
+ mc_set_tsa_w_passthrough(RCEW);
+ mc_set_tsa_w_passthrough(SDMMCW);
+ mc_set_tsa_w_passthrough(SDMMCWA);
+ mc_set_tsa_w_passthrough(SDMMCWAB);
+ mc_set_tsa_w_passthrough(TSECSWR);
+ mc_set_tsa_w_passthrough(TSECSWRB);
+ mc_set_tsa_w_passthrough(UFSHCW);
+ mc_set_tsa_w_passthrough(VICSWR);
+ mc_set_tsa_w_passthrough(VIFALW);
+
+ /* Ordered MC Clients on Xavier are EQOS, SATA, XUSB, PCIe1 and PCIe3
+ * ISO clients(DISP, VI, EQOS) should never snoop caches and
+ * don't need ROC/PCFIFO ordering.
+ * ISO clients(EQOS) that need ordering should use PCFIFO ordering
+ * and bypass ROC ordering by using FORCE_NON_COHERENT path.
+ * FORCE_NON_COHERENT/FORCE_COHERENT config take precedence
+ * over SMMU attributes.
+ * Force all Normal memory transactions from ISO and non-ISO to be
+ * non-coherent(bypass ROC, avoid cache snoop to avoid perf hit).
+ * Force the SO_DEV transactions from ordered ISO clients(EQOS) to
+ * non-coherent path and enable MC PCFIFO interlock for ordering.
+ * Force the SO_DEV transactions from ordered non-ISO clients (PCIe,
+ * XUSB, SATA) to coherent so that the transactions are
+ * ordered by ROC.
+ * PCFIFO ensure write ordering.
+ * Read after Write ordering is maintained/enforced by MC clients.
+ * Clients that need PCIe type write ordering must
+ * go through ROC ordering.
+ * Ordering enable for Read clients is not necessary.
+ * R5's and A9 would get necessary ordering from AXI and
+ * don't need ROC ordering enable:
+ * - MMIO ordering is through dev mapping and MMIO
+ * accesses bypass SMMU.
+ * - Normal memory is accessed through SMMU and ordering is
+ * ensured by client and AXI.
+ * - Ack point for Normal memory is WCAM in MC.
+ * - MMIO's can be early acked and AXI ensures dev memory ordering,
+ * Client ensures read/write direction change ordering.
+ * - See Bug 200312466 for more details.
+ *
+ * CGID_TAG_ADR is only present from T186 A02. As this code is common
+ * between A01 and A02, tegra_memctrl_set_overrides() programs
+ * CGID_TAG_ADR for the necessary clients on A02.
+ */
+ mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
+ mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
+ mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
+ mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
+ mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(RCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(RCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(RCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(RCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, NO_OVERRIDE);
+ mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, NO_OVERRIDE);
+ mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(VIFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(VIFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
+ FORCE_COHERENT_SNOOP);
+ mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
+ FORCE_COHERENT_SNOOP);
+ mc_set_txn_override(PCIE0R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(PCIE0R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(PCIE0W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
+ FORCE_COHERENT_SNOOP);
+ mc_set_txn_override(PCIE1R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(PCIE1W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
+ FORCE_COHERENT_SNOOP);
+ if (tegra_platform_is_silicon()) {
+ mc_set_txn_override(PCIE2AR, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(PCIE2AW, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
+ mc_set_txn_override(PCIE3R, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(PCIE3W, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
+ mc_set_txn_override(PCIE4R, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(PCIE4W, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
+ mc_set_txn_override(PCIE5R, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(PCIE5W, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
+ mc_set_txn_override(PCIE5R1, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ NO_OVERRIDE, NO_OVERRIDE);
+ }
+ /*
+ * At this point, ordering can occur at ROC. So, remove PCFIFO's
+ * control over ordering requests.
+ *
+ * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for
+ * boot and strongly ordered MSS clients
+ */
+ /* SATAW is ordered client */
+ reg_val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL |
+ mc_set_pcfifo_ordered_boot_so_mss(1, SATAW);
+ tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, reg_val);
+
+ reg_val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL &
+ mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) &
+ mc_set_pcfifo_unordered_boot_so_mss(2, TSECSWR);
+ /* XUSB_DEVW has PCFIFO enabled. */
+ reg_val |= mc_set_pcfifo_ordered_boot_so_mss(2, XUSB_DEVW);
+ tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, reg_val);
+
+ reg_val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL &
+ mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWA) &
+ mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCW) &
+ mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB) &
+ mc_set_pcfifo_unordered_boot_so_mss(3, VICSWR) &
+ mc_set_pcfifo_unordered_boot_so_mss(3, APEW);
+ tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, reg_val);
+
+ reg_val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL &
+ mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, TSECSWRB) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, BPMPW) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, AONW) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, SCEW) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW);
+ /* EQOSW has PCFIFO order enabled. */
+ reg_val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW);
+ tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, reg_val);
+
+ reg_val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL &
+ mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW) &
+ mc_set_pcfifo_unordered_boot_so_mss(5, VIFALW);
+ tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, reg_val);
+
+ reg_val = MC_PCFIFO_CLIENT_CONFIG6_RESET_VAL &
+ mc_set_pcfifo_unordered_boot_so_mss(6, RCEW) &
+ mc_set_pcfifo_unordered_boot_so_mss(6, RCEDMAW) &
+ mc_set_pcfifo_unordered_boot_so_mss(6, PCIE0W);
+ /* PCIE1, PCIE2 and PCI3 has PCFIFO enabled. */
+ reg_val |= mc_set_pcfifo_ordered_boot_so_mss(6, PCIE1W) |
+ mc_set_pcfifo_ordered_boot_so_mss(6, PCIE2W) |
+ mc_set_pcfifo_ordered_boot_so_mss(6, PCIE3W);
+ tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG6, reg_val);
+
+ reg_val = MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL &
+ mc_set_pcfifo_unordered_boot_so_mss(7, PCIE4W) &
+ mc_set_pcfifo_unordered_boot_so_mss(7, PCIE5W);
+ tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG7, reg_val);
+
+ /* Set Order Id only for the clients having non zero order id */
+ reg_val = MC_CLIENT_ORDER_ID_9_RESET_VAL &
+ mc_client_order_id(9, XUSB_HOSTW);
+ tegra_mc_write_32(MC_CLIENT_ORDER_ID_9, reg_val);
+
+ reg_val = MC_CLIENT_ORDER_ID_27_RESET_VAL &
+ mc_client_order_id(27, PCIE0W);
+ tegra_mc_write_32(MC_CLIENT_ORDER_ID_27, reg_val);
+
+ reg_val = MC_CLIENT_ORDER_ID_28_RESET_VAL &
+ mc_client_order_id(28, PCIE4W) &
+ mc_client_order_id(28, PCIE5W);
+ tegra_mc_write_32(MC_CLIENT_ORDER_ID_28, reg_val);
+
+ /* Set VC Id only for the clients having different reset values */
+ reg_val = MC_HUB_PC_VC_ID_0_RESET_VAL &
+ /*
+ * SDMMCRAB, SDMMCWAB, SESRD, SESWR, TSECSRD,TSECSRDB,
+ * TSECSWR and TSECSWRB clients
+ */
+ mc_hub_vc_id(0, APB);
+ tegra_mc_write_32(MC_HUB_PC_VC_ID_0, reg_val);
+
+ reg_val = MC_HUB_PC_VC_ID_2_RESET_VAL &
+ /* SDMMCRAB and SDMMCWAB clients */
+ mc_hub_vc_id(2, SD);
+ tegra_mc_write_32(MC_HUB_PC_VC_ID_2, reg_val);
+
+ reg_val = MC_HUB_PC_VC_ID_4_RESET_VAL &
+ /* AXIR and AXIW clients */
+ mc_hub_vc_id(4, NIC);
+ tegra_mc_write_32(MC_HUB_PC_VC_ID_4, reg_val);
+
+ wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL;
+ tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
+
+ wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL;
+ tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
+
+ wdata_2 = MC_CLIENT_HOTRESET_CTRL2_RESET_VAL;
+ tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2);
+}
+
+/*******************************************************************************
+ * Struct to hold the memory controller settings
+ ******************************************************************************/
+static tegra_mc_settings_t tegra194_mc_settings = {
+ .streamid_override_cfg = tegra194_streamid_override_regs,
+ .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs),
+ .streamid_security_cfg = tegra194_streamid_sec_cfgs,
+ .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs),
+ .txn_override_cfg = tegra194_txn_override_cfgs,
+ .num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_txn_override_cfgs),
+ .reconfig_mss_clients = tegra194_memctrl_reconfig_mss_clients
+};
+
+/*******************************************************************************
+ * Handler to return the pointer to the memory controller's settings struct
+ ******************************************************************************/
+tegra_mc_settings_t *tegra_get_mc_settings(void)
+{
+ return &tegra194_mc_settings;
+}
+
+/*******************************************************************************
+ * Handler to program the scratch registers with TZDRAM settings for the
+ * resume firmware
+ ******************************************************************************/
+void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
+{
+ uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0);
+
+ /*
+ * Check TZDRAM carveout register access status. Setup TZDRAM fence
+ * only if access is enabled.
+ */
+ if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) ==
+ SECURITY_CFG_WRITE_ACCESS_ENABLE) {
+
+ /*
+ * Setup the Memory controller to allow only secure accesses to
+ * the TZDRAM carveout
+ */
+ INFO("Configuring TrustZone DRAM Memory Carveout\n");
+
+ tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base);
+ tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32));
+ tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20));
+
+ /*
+ * MCE propagates the security configuration values across the
+ * CCPLEX.
+ */
+ (void)mce_update_gsc_tzdram();
+ }
+}
diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index e53d5946e35025ca6697cd7aebe9f8f067aabaac..948fadec9b83d81aeb025b65c71e7c4df4cbc0b5 100644
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -5,58 +5,65 @@
*/
#include <arch.h>
-#include <arch_helpers.h>
#include <assert.h>
+#include <stdbool.h>
+#include <string.h>
+
+#include <arch_helpers.h>
#include <common/bl_common.h>
-#include <context.h>
-#include <lib/el3_runtime/context_mgmt.h>
#include <common/debug.h>
+#include <context.h>
#include <denver.h>
+#include <lib/el3_runtime/context_mgmt.h>
+#include <lib/psci/psci.h>
#include <mce.h>
+#include <mce_private.h>
#include <plat/common/platform.h>
-#include <lib/psci/psci.h>
+#include <se.h>
#include <smmu.h>
-#include <string.h>
-#include <tegra_private.h>
#include <t194_nvg.h>
+#include <tegra194_private.h>
+#include <tegra_platform.h>
+#include <tegra_private.h>
-extern void prepare_core_pwr_dwn(void);
-
-extern uint8_t tegra_fake_system_suspend;
-
-#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
-extern void tegra186_cpu_reset_handler(void);
-extern uint32_t __tegra186_cpu_reset_handler_data,
- __tegra186_cpu_reset_handler_end;
+extern void tegra194_cpu_reset_handler(void);
+extern uint32_t __tegra194_cpu_reset_handler_data,
+ __tegra194_cpu_reset_handler_end;
/* TZDRAM offset for saving SMMU context */
-#define TEGRA186_SMMU_CTX_OFFSET 16
-#endif
+#define TEGRA194_SMMU_CTX_OFFSET 16U
/* state id mask */
-#define TEGRA186_STATE_ID_MASK 0xF
+#define TEGRA194_STATE_ID_MASK 0xFU
/* constants to get power state's wake time */
-#define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0
-#define TEGRA186_WAKE_TIME_SHIFT 4
+#define TEGRA194_WAKE_TIME_MASK 0x0FFFFFF0U
+#define TEGRA194_WAKE_TIME_SHIFT 4U
/* default core wake mask for CPU_SUSPEND */
-#define TEGRA186_CORE_WAKE_MASK 0x180c
-/* context size to save during system suspend */
-#define TEGRA186_SE_CONTEXT_SIZE 3
+#define TEGRA194_CORE_WAKE_MASK 0x180cU
-static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE];
-static struct t18x_psci_percpu_data {
- unsigned int wake_time;
-} __aligned(CACHE_WRITEBACK_GRANULE) percpu_data[PLATFORM_CORE_COUNT];
+static struct t19x_psci_percpu_data {
+ uint32_t wake_time;
+} __aligned(CACHE_WRITEBACK_GRANULE) t19x_percpu_data[PLATFORM_CORE_COUNT];
-int32_t tegra_soc_validate_power_state(unsigned int power_state,
+/*
+ * tegra_fake_system_suspend acts as a boolean var controlling whether
+ * we are going to take fake system suspend code or normal system suspend code
+ * path. This variable is set inside the sip call handlers, when the kernel
+ * requests an SIP call to set the suspend debug flags.
+ */
+bool tegra_fake_system_suspend;
+
+int32_t tegra_soc_validate_power_state(uint32_t power_state,
psci_power_state_t *req_state)
{
- int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK;
- int cpu = plat_my_core_pos();
+ uint8_t state_id = (uint8_t)psci_get_pstate_id(power_state) &
+ TEGRA194_STATE_ID_MASK;
+ uint32_t cpu = plat_my_core_pos();
+ int32_t ret = PSCI_E_SUCCESS;
/* save the core wake time (in TSC ticks)*/
- percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK)
- << TEGRA186_WAKE_TIME_SHIFT;
+ t19x_percpu_data[cpu].wake_time = (power_state & TEGRA194_WAKE_TIME_MASK)
+ << TEGRA194_WAKE_TIME_SHIFT;
/*
* Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that
@@ -65,8 +72,8 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
* from DRAM in that function, because the L2 cache is not flushed
* unless the cluster is entering CC6/CC7.
*/
- clean_dcache_range((uint64_t)&percpu_data[cpu],
- sizeof(percpu_data[cpu]));
+ clean_dcache_range((uint64_t)&t19x_percpu_data[cpu],
+ sizeof(t19x_percpu_data[cpu]));
/* Sanity check the requested state id */
switch (state_id) {
@@ -81,148 +88,195 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
default:
ERROR("%s: unsupported state id (%d)\n", __func__, state_id);
- return PSCI_E_INVALID_PARAMS;
+ ret = PSCI_E_INVALID_PARAMS;
+ break;
}
- return PSCI_E_SUCCESS;
+ return ret;
}
-int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
+int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
{
const plat_local_state_t *pwr_domain_state;
- unsigned int stateid_afflvl0, stateid_afflvl2;
-#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
+ uint8_t stateid_afflvl0, stateid_afflvl2;
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
uint64_t smmu_ctx_base;
-#endif
uint32_t val;
- mce_cstate_info_t cstate_info = { 0 };
+ mce_cstate_info_t sc7_cstate_info = {
+ .cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6,
+ .system = (uint32_t)TEGRA_NVG_SYSTEM_SC7,
+ .system_state_force = 1U,
+ .update_wake_mask = 1U,
+ };
+ uint32_t cpu = plat_my_core_pos();
+ int32_t ret = 0;
/* get the state ID */
pwr_domain_state = target_state->pwr_domain_state;
stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] &
- TEGRA186_STATE_ID_MASK;
+ TEGRA194_STATE_ID_MASK;
stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
- TEGRA186_STATE_ID_MASK;
+ TEGRA194_STATE_ID_MASK;
if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ||
(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) {
/* Enter CPU idle/powerdown */
+ val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ?
+ (uint32_t)TEGRA_NVG_CORE_C6 : (uint32_t)TEGRA_NVG_CORE_C7;
+ ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val,
+ percpu_data[cpu].wake_time, 0);
+ assert(ret == 0);
} else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
- /* save SE registers */
- se_regs[0] = mmio_read_32(TEGRA_SE0_BASE +
- SE_MUTEX_WATCHDOG_NS_LIMIT);
- se_regs[1] = mmio_read_32(TEGRA_RNG1_BASE +
- RNG_MUTEX_WATCHDOG_NS_LIMIT);
- se_regs[2] = mmio_read_32(TEGRA_PKA1_BASE +
- PKA_MUTEX_WATCHDOG_NS_LIMIT);
-
/* save 'Secure Boot' Processor Feature Config Register */
val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG);
- mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV6, val);
+ mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val);
-#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
/* save SMMU context */
smmu_ctx_base = params_from_bl2->tzdram_base +
- ((uintptr_t)&__tegra186_cpu_reset_handler_data -
- (uintptr_t)tegra186_cpu_reset_handler) +
- TEGRA186_SMMU_CTX_OFFSET;
+ tegra194_get_smmu_ctx_offset();
tegra_smmu_save_context((uintptr_t)smmu_ctx_base);
-#else
- tegra_smmu_save_context(0);
-#endif
- if (tegra_fake_system_suspend == 0U) {
+ /*
+ * Suspend SE, RNG1 and PKA1 only on silcon and fpga,
+ * since VDK does not support atomic se ctx save
+ */
+ if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
+ ret = tegra_se_suspend();
+ assert(ret == 0);
+ }
+
+ if (!tegra_fake_system_suspend) {
/* Prepare for system suspend */
- cstate_info.cluster = TEGRA_NVG_CLUSTER_CC6;
- cstate_info.system = TEGRA_NVG_SYSTEM_SC7;
- cstate_info.system_state_force = 1;
- cstate_info.update_wake_mask = 1;
-
- mce_update_cstate_info(&cstate_info);
+ mce_update_cstate_info(&sc7_cstate_info);
do {
- val = mce_command_handler(
- MCE_CMD_IS_SC7_ALLOWED,
- TEGRA_NVG_CORE_C7,
+ val = (uint32_t)mce_command_handler(
+ (uint32_t)MCE_CMD_IS_SC7_ALLOWED,
+ (uint32_t)TEGRA_NVG_CORE_C7,
MCE_CORE_SLEEP_TIME_INFINITE,
- 0);
- } while (val == 0);
-
- /* Instruct the MCE to enter system suspend state */
- (void)mce_command_handler(MCE_CMD_ENTER_CSTATE,
- TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0);
+ 0U);
+ } while (val == 0U);
+
+ /* Instruct the MCE to enter system suspend state */
+ ret = mce_command_handler(
+ (uint64_t)MCE_CMD_ENTER_CSTATE,
+ (uint64_t)TEGRA_NVG_CORE_C7,
+ MCE_CORE_SLEEP_TIME_INFINITE,
+ 0U);
+ assert(ret == 0);
+
+ /* set system suspend state for house-keeping */
+ tegra194_set_system_suspend_entry();
}
+ } else {
+ ; /* do nothing */
}
return PSCI_E_SUCCESS;
}
/*******************************************************************************
- * Platform handler to calculate the proper target power level at the
- * specified affinity level
+ * Helper function to check if this is the last ON CPU in the cluster
******************************************************************************/
-plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
- const plat_local_state_t *states,
- unsigned int ncpu)
+static bool tegra_last_on_cpu_in_cluster(const plat_local_state_t *states,
+ uint32_t ncpu)
{
- plat_local_state_t target = *states;
- int cluster_powerdn = 1;
- int core_pos = read_mpidr() & MPIDR_CPU_MASK;
+ plat_local_state_t target;
+ bool last_on_cpu = true;
+ uint32_t num_cpus = ncpu, pos = 0;
+
+ do {
+ target = states[pos];
+ if (target != PLAT_MAX_OFF_STATE) {
+ last_on_cpu = false;
+ }
+ --num_cpus;
+ pos++;
+ } while (num_cpus != 0U);
- /* get the current core's power state */
- target = *(states + core_pos);
+ return last_on_cpu;
+}
+
+/*******************************************************************************
+ * Helper function to get target power state for the cluster
+ ******************************************************************************/
+static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *states,
+ uint32_t ncpu)
+{
+ uint32_t core_pos = (uint32_t)read_mpidr() & (uint32_t)MPIDR_CPU_MASK;
+ plat_local_state_t target = states[core_pos];
+ mce_cstate_info_t cstate_info = { 0 };
/* CPU suspend */
- if (lvl == MPIDR_AFFLVL1 && target == PSTATE_ID_CORE_POWERDN) {
+ if (target == PSTATE_ID_CORE_POWERDN) {
/* Program default wake mask */
-
- /* Check if CCx state is allowed. */
+ cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK;
+ cstate_info.update_wake_mask = 1;
+ mce_update_cstate_info(&cstate_info);
}
/* CPU off */
- if (lvl == MPIDR_AFFLVL1 && target == PLAT_MAX_OFF_STATE) {
-
- /* find out the number of ON cpus in the cluster */
- do {
- target = *states++;
- if (target != PLAT_MAX_OFF_STATE)
- cluster_powerdn = 0;
- } while (--ncpu);
+ if (target == PLAT_MAX_OFF_STATE) {
/* Enable cluster powerdn from last CPU in the cluster */
- if (cluster_powerdn) {
+ if (tegra_last_on_cpu_in_cluster(states, ncpu)) {
- /* Enable CC7 state and turn off wake mask */
+ /* Enable CC6 state and turn off wake mask */
+ cstate_info.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6;
+ cstate_info.update_wake_mask = 1U;
+ mce_update_cstate_info(&cstate_info);
} else {
/* Turn off wake_mask */
+ cstate_info.update_wake_mask = 1U;
+ mce_update_cstate_info(&cstate_info);
+ target = PSCI_LOCAL_STATE_RUN;
}
}
+ return target;
+}
+
+/*******************************************************************************
+ * Platform handler to calculate the proper target power level at the
+ * specified affinity level
+ ******************************************************************************/
+plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
+ const plat_local_state_t *states,
+ uint32_t ncpu)
+{
+ plat_local_state_t target = PSCI_LOCAL_STATE_RUN;
+ uint32_t cpu = plat_my_core_pos();
+
/* System Suspend */
- if ((lvl == MPIDR_AFFLVL2) || (target == PSTATE_ID_SOC_POWERDN))
- return PSTATE_ID_SOC_POWERDN;
+ if ((lvl == (uint32_t)MPIDR_AFFLVL2) && (states[cpu] == PSTATE_ID_SOC_POWERDN)) {
+ target = PSTATE_ID_SOC_POWERDN;
+ }
- /* default state */
- return PSCI_LOCAL_STATE_RUN;
+ /* CPU off, CPU suspend */
+ if (lvl == (uint32_t)MPIDR_AFFLVL1) {
+ target = tegra_get_afflvl1_pwr_state(states, ncpu);
+ }
+
+ /* target cluster/system state */
+ return target;
}
-#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
-int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
+int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
{
const plat_local_state_t *pwr_domain_state =
target_state->pwr_domain_state;
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
- unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
- TEGRA186_STATE_ID_MASK;
+ uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
+ TEGRA194_STATE_ID_MASK;
uint64_t val;
+ u_register_t ns_sctlr_el1;
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
/*
@@ -231,38 +285,64 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
* BL3-1 over to TZDRAM.
*/
val = params_from_bl2->tzdram_base +
- ((uintptr_t)&__tegra186_cpu_reset_handler_end -
- (uintptr_t)tegra186_cpu_reset_handler);
+ tegra194_get_cpu_reset_handler_size();
memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE,
(uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE);
+
+ /*
+ * In fake suspend mode, ensure that the loopback procedure
+ * towards system suspend exit is started, instead of calling
+ * WFI. This is done by disabling both MMU's of EL1 & El3
+ * and calling tegra_secure_entrypoint().
+ */
+ if (tegra_fake_system_suspend) {
+
+ /*
+ * Disable EL1's MMU.
+ */
+ ns_sctlr_el1 = read_sctlr_el1();
+ ns_sctlr_el1 &= (~((u_register_t)SCTLR_M_BIT));
+ write_sctlr_el1(ns_sctlr_el1);
+
+ /*
+ * Disable MMU to power up the CPU in a "clean"
+ * state
+ */
+ disable_mmu_el3();
+ tegra_secure_entrypoint();
+ panic();
+ }
}
return PSCI_E_SUCCESS;
}
-#endif
-int tegra_soc_pwr_domain_on(u_register_t mpidr)
+int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
{
- int target_cpu = mpidr & MPIDR_CPU_MASK;
- int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >>
+ uint64_t target_cpu = mpidr & MPIDR_CPU_MASK;
+ uint64_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >>
MPIDR_AFFINITY_BITS;
+ int32_t ret = 0;
- if (target_cluster > MPIDR_AFFLVL1) {
+ if (target_cluster > ((uint32_t)PLATFORM_CLUSTER_COUNT - 1U)) {
ERROR("%s: unsupported CPU (0x%lx)\n", __func__ , mpidr);
return PSCI_E_NOT_PRESENT;
}
/* construct the target CPU # */
- target_cpu |= (target_cluster << 2);
+ target_cpu += (target_cluster << 1U);
- mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0);
+ ret = mce_command_handler((uint64_t)MCE_CMD_ONLINE_CORE, target_cpu, 0U, 0U);
+ if (ret < 0) {
+ return PSCI_E_DENIED;
+ }
return PSCI_E_SUCCESS;
}
-int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
+int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
- int stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
+ uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
/*
* Reset power state info for CPUs when onlining, we set
@@ -278,14 +358,17 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
*/
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
- mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT,
- se_regs[0]);
- mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT,
- se_regs[1]);
- mmio_write_32(TEGRA_PKA1_BASE + PKA_MUTEX_WATCHDOG_NS_LIMIT,
- se_regs[2]);
+ /*
+ * Enable strict checking after programming the GSC for
+ * enabling TZSRAM and TZDRAM
+ */
+ mce_enable_strict_checking();
/* Init SMMU */
+ tegra_smmu_init();
+
+ /* Resume SE, RNG1 and PKA1 */
+ tegra_se_resume();
/*
* Reset power state info for the last core doing SC7
@@ -298,15 +381,22 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
return PSCI_E_SUCCESS;
}
-int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
+int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
{
- int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
+ uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
+ int32_t ret = 0;
+
+ (void)target_state;
/* Disable Denver's DCO operations */
- if (impl == DENVER_IMPL)
+ if (impl == DENVER_IMPL) {
denver_disable_dco();
+ }
/* Turn off CPU */
+ ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
+ (uint64_t)TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U);
+ assert(ret == 0);
return PSCI_E_SUCCESS;
}
@@ -325,7 +415,7 @@ __dead2 void tegra_soc_prepare_system_off(void)
}
}
-int tegra_soc_prepare_system_reset(void)
+int32_t tegra_soc_prepare_system_reset(void)
{
return PSCI_E_SUCCESS;
}
diff --git a/plat/nvidia/tegra/soc/t194/plat_secondary.c b/plat/nvidia/tegra/soc/t194/plat_secondary.c
index f5e56b9b07f0ed17a5ac33c4a703f7fae04a1602..c397c91ba043ab360c5e8c16d1599679d0655a05 100644
--- a/plat/nvidia/tegra/soc/t194/plat_secondary.c
+++ b/plat/nvidia/tegra/soc/t194/plat_secondary.c
@@ -9,21 +9,14 @@
#include <lib/mmio.h>
#include <mce.h>
#include <string.h>
+#include <tegra194_private.h>
#include <tegra_def.h>
#include <tegra_private.h>
-#define MISCREG_CPU_RESET_VECTOR 0x2000
-#define MISCREG_AA64_RST_LOW 0x2004
-#define MISCREG_AA64_RST_HIGH 0x2008
+#define MISCREG_AA64_RST_LOW 0x2004U
+#define MISCREG_AA64_RST_HIGH 0x2008U
-#define CPU_RESET_MODE_AA64 1
-
-extern void tegra_secure_entrypoint(void);
-
-#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
-extern void tegra186_cpu_reset_handler(void);
-extern uint64_t __tegra186_smmu_ctx_start;
-#endif
+#define CPU_RESET_MODE_AA64 1U
/*******************************************************************************
* Setup secondary CPU vectors
@@ -31,32 +24,33 @@ extern uint64_t __tegra186_smmu_ctx_start;
void plat_secondary_setup(void)
{
uint32_t addr_low, addr_high;
-#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
- uint64_t cpu_reset_handler_base = params_from_bl2->tzdram_base;
-#else
- uint64_t cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint;
-#endif
+ uint64_t cpu_reset_handler_base, cpu_reset_handler_size;
INFO("Setting up secondary CPU boot\n");
-#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
- memcpy((void *)((uintptr_t)cpu_reset_handler_base),
- (void *)(uintptr_t)tegra186_cpu_reset_handler,
- (uintptr_t)&__tegra186_smmu_ctx_start -
- (uintptr_t)tegra186_cpu_reset_handler);
-#endif
-
- addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64;
- addr_high = (uint32_t)((cpu_reset_handler_base >> 32) & 0x7ff);
+ /*
+ * The BL31 code resides in the TZSRAM which loses state
+ * when we enter System Suspend. Copy the wakeup trampoline
+ * code to TZDRAM to help us exit from System Suspend.
+ */
+ cpu_reset_handler_base = tegra194_get_cpu_reset_handler_base();
+ cpu_reset_handler_size = tegra194_get_cpu_reset_handler_size();
+ memcpy((void *)((uintptr_t)params_from_bl2->tzdram_base),
+ (void *)((uintptr_t)cpu_reset_handler_base),
+ cpu_reset_handler_size);
+
+ /* TZDRAM base will be used as the "resume" address */
+ addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64;
+ addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU);
/* write lower 32 bits first, then the upper 11 bits */
mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low);
mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high);
/* save reset vector to be used during SYSTEM_SUSPEND exit */
- mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_LO,
+ mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO,
addr_low);
- mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_HI,
+ mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI,
addr_high);
}
diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c
index a3a2515ca758222c1d77113cc137fb37e746d60a..8c5710557dee41cbd7cbfa4a492480102f6819d0 100644
--- a/plat/nvidia/tegra/soc/t194/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t194/plat_setup.c
@@ -19,19 +19,25 @@
#include <drivers/arm/gicv2.h>
#include <bl31/interrupt_mgmt.h>
#include <mce.h>
+#include <mce_private.h>
#include <plat/common/platform.h>
+#include <spe.h>
#include <tegra_def.h>
+#include <tegra_mc_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
+/* ID for spe-console */
+#define TEGRA_CONSOLE_SPE_ID 0xFE
+
/*******************************************************************************
* The Tegra power domain tree has a single system level power domain i.e. a
* single root node. The first entry in the power domain descriptor specifies
* the number of power domains at the highest power level.
*******************************************************************************
*/
-const unsigned char tegra_power_domain_tree_desc[] = {
+static const uint8_t tegra_power_domain_tree_desc[] = {
/* No of root nodes */
1,
/* No of clusters */
@@ -39,13 +45,17 @@ const unsigned char tegra_power_domain_tree_desc[] = {
/* No of CPU cores - cluster0 */
PLATFORM_MAX_CPUS_PER_CLUSTER,
/* No of CPU cores - cluster1 */
+ PLATFORM_MAX_CPUS_PER_CLUSTER,
+ /* No of CPU cores - cluster2 */
+ PLATFORM_MAX_CPUS_PER_CLUSTER,
+ /* No of CPU cores - cluster3 */
PLATFORM_MAX_CPUS_PER_CLUSTER
};
/*******************************************************************************
* This function returns the Tegra default topology tree information.
******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
+const uint8_t *plat_get_power_domain_tree_desc(void)
{
return tegra_power_domain_tree_desc;
}
@@ -54,44 +64,52 @@ const unsigned char *plat_get_power_domain_tree_desc(void)
* Table of regions to map using the MMU.
*/
static const mmap_region_t tegra_mmap[] = {
- MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000, /* 64KB */
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000, /* 64KB */
- MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+#if !ENABLE_CONSOLE_SPE
+ MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+#endif
+ MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+#if ENABLE_CONSOLE_SPE
+ MAP_REGION_FLAT(TEGRA_AON_HSP_SM_6_7_BASE, 0x10000U, /* 64KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+#endif
+ MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000U, /* 64KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000U, /* 64KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000U, /* 64KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
{0}
};
@@ -107,20 +125,21 @@ const mmap_region_t *plat_get_mmio_map(void)
/*******************************************************************************
* Handler to get the System Counter Frequency
******************************************************************************/
-unsigned int plat_get_syscnt_freq2(void)
+uint32_t plat_get_syscnt_freq2(void)
{
return 31250000;
}
+#if !ENABLE_CONSOLE_SPE
/*******************************************************************************
* Maximum supported UART controllers
******************************************************************************/
-#define TEGRA186_MAX_UART_PORTS 7
+#define TEGRA194_MAX_UART_PORTS 7
/*******************************************************************************
* This variable holds the UART port base addresses
******************************************************************************/
-static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
+static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = {
0, /* undefined - treated as an error case */
TEGRA_UARTA_BASE,
TEGRA_UARTB_BASE,
@@ -128,18 +147,49 @@ static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
TEGRA_UARTD_BASE,
TEGRA_UARTE_BASE,
TEGRA_UARTF_BASE,
- TEGRA_UARTG_BASE,
+ TEGRA_UARTG_BASE
};
+#endif
/*******************************************************************************
- * Retrieve the UART controller base to be used as the console
+ * Enable console corresponding to the console ID
******************************************************************************/
-uint32_t plat_get_console_from_id(int id)
+void plat_enable_console(int32_t id)
{
- if (id > TEGRA186_MAX_UART_PORTS)
- return 0;
+ uint32_t console_clock = 0U;
+
+#if ENABLE_CONSOLE_SPE
+ static console_spe_t spe_console;
+
+ if (id == TEGRA_CONSOLE_SPE_ID) {
+ (void)console_spe_register(TEGRA_CONSOLE_SPE_BASE,
+ console_clock,
+ TEGRA_CONSOLE_BAUDRATE,
+ &spe_console);
+ console_set_scope(&spe_console.console, CONSOLE_FLAG_BOOT |
+ CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
+ }
+#else
+ static console_16550_t uart_console;
+
+ if ((id > 0) && (id < TEGRA194_MAX_UART_PORTS)) {
+ /*
+ * Reference clock used by the FPGAs is a lot slower.
+ */
+ if (tegra_platform_is_fpga()) {
+ console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
+ } else {
+ console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
+ }
- return tegra186_uart_addresses[id];
+ (void)console_16550_register(tegra194_uart_addresses[id],
+ console_clock,
+ TEGRA_CONSOLE_BAUDRATE,
+ &uart_console);
+ console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT |
+ CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
+ }
+#endif
}
/*******************************************************************************
@@ -151,40 +201,61 @@ void plat_early_platform_setup(void)
/* sanity check MCE firmware compatibility */
mce_verify_firmware_version();
+ /* Program XUSB STREAMIDs
+ * Xavier XUSB has support for XUSB virtualization. It will have one
+ * physical function (PF) and four Virtual function (VF)
+ *
+ * There were below two SIDs for XUSB until T186.
+ * 1) #define TEGRA_SID_XUSB_HOST 0x1bU
+ * 2) #define TEGRA_SID_XUSB_DEV 0x1cU
+ *
+ * We have below four new SIDs added for VF(s)
+ * 3) #define TEGRA_SID_XUSB_VF0 0x5dU
+ * 4) #define TEGRA_SID_XUSB_VF1 0x5eU
+ * 5) #define TEGRA_SID_XUSB_VF2 0x5fU
+ * 6) #define TEGRA_SID_XUSB_VF3 0x60U
+ *
+ * When virtualization is enabled then we have to disable SID override
+ * and program above SIDs in below newly added SID registers in XUSB
+ * PADCTL MMIO space. These registers are TZ protected and so need to
+ * be done in ATF.
+ * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU)
+ * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU)
+ * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U)
+ * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U)
+ * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U)
+ * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)
+ *
+ * This change disables SID override and programs XUSB SIDs in
+ * above registers to support both virtualization and non-virtualization
+ *
+ * Known Limitations:
+ * If xusb interface disables SMMU in XUSB DT in non-virtualization
+ * setup then there will be SMMU fault. We need to use WAR at
+ * https:\\git-master.nvidia.com/r/1529227/ to the issue.
+ *
+ * More details can be found in the bug 1971161
+ */
+ mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+ XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
+ mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+ XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
+ mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+ XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
+ mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+ XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
+ mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+ XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
+ mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+ XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
}
-/* Secure IRQs for Tegra186 */
-static const irq_sec_cfg_t tegra186_sec_irqs[] = {
- [0] = {
- TEGRA186_BPMP_WDT_IRQ,
- TEGRA186_SEC_IRQ_TARGET_MASK,
- INTR_TYPE_EL3,
- },
- [1] = {
- TEGRA186_BPMP_WDT_IRQ,
- TEGRA186_SEC_IRQ_TARGET_MASK,
- INTR_TYPE_EL3,
- },
- [2] = {
- TEGRA186_SPE_WDT_IRQ,
- TEGRA186_SEC_IRQ_TARGET_MASK,
- INTR_TYPE_EL3,
- },
- [3] = {
- TEGRA186_SCE_WDT_IRQ,
- TEGRA186_SEC_IRQ_TARGET_MASK,
- INTR_TYPE_EL3,
- },
- [4] = {
- TEGRA186_TOP_WDT_IRQ,
- TEGRA186_SEC_IRQ_TARGET_MASK,
- INTR_TYPE_EL3,
- },
- [5] = {
- TEGRA186_AON_WDT_IRQ,
- TEGRA186_SEC_IRQ_TARGET_MASK,
- INTR_TYPE_EL3,
- },
+/* Secure IRQs for Tegra194 */
+static const interrupt_prop_t tegra194_interrupt_props[] = {
+ INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+ INTR_PROP_DESC(TEGRA194_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
};
/*******************************************************************************
@@ -192,15 +263,13 @@ static const irq_sec_cfg_t tegra186_sec_irqs[] = {
******************************************************************************/
void plat_gic_setup(void)
{
- tegra_gic_setup(tegra186_sec_irqs,
- sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0]));
+ tegra_gic_setup(tegra194_interrupt_props, ARRAY_SIZE(tegra194_interrupt_props));
+ tegra_gic_init();
/*
- * Initialize the FIQ handler only if the platform supports any
- * FIQ interrupt sources.
+ * Initialize the FIQ handler
*/
- if (sizeof(tegra186_sec_irqs) > 0)
- tegra_fiq_handler_setup();
+ tegra_fiq_handler_setup();
}
/*******************************************************************************
@@ -210,7 +279,7 @@ struct tegra_bl31_params *plat_get_bl31_params(void)
{
uint32_t val;
- val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO);
+ val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR);
return (struct tegra_bl31_params *)(uintptr_t)val;
}
@@ -222,7 +291,16 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
{
uint32_t val;
- val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI);
+ val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR);
return (plat_params_from_bl2_t *)(uintptr_t)val;
}
+
+void plat_late_platform_setup(void)
+{
+ /*
+ * Enable strict checking after programming the GSC for
+ * enabling TZSRAM and TZDRAM
+ */
+ mce_enable_strict_checking();
+}
diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
index eaad73a409d45aff7d614593accfaba1ae7cb184..8873358cd71dc3b6b96d06d274e1ec5bacd65bf8 100644
--- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
@@ -15,38 +15,20 @@
#include <memctrl.h>
#include <common/runtime_svc.h>
#include <tegra_private.h>
+#include <tegra_platform.h>
+#include <stdbool.h>
-extern uint32_t tegra186_system_powerdn_state;
+extern bool tegra_fake_system_suspend;
/*******************************************************************************
- * Tegra186 SiP SMCs
+ * Tegra194 SiP SMCs
******************************************************************************/
-#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0xC2FFFE01
-#define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0xC2FFFE02
-#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0xC2FFFF00
-#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0xC2FFFF01
-#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0xC2FFFF02
-#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0xC2FFFF03
-#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0xC2FFFF04
-#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0xC2FFFF05
-#define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0xC2FFFF06
-#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0xC2FFFF07
-#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0xC2FFFF08
-#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0xC2FFFF09
-#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0xC2FFFF0A
-#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0xC2FFFF0B
-#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0xC2FFFF0C
-#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0xC2FFFF0D
-#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0xC2FFFF0E
-#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0xC2FFFF0F
-#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0xC2FFFF10
-#define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0xC2FFFF11
-#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0xC2FFFF12
+#define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2FFFE03U
/*******************************************************************************
- * This function is responsible for handling all T186 SiP calls
+ * This function is responsible for handling all T194 SiP calls
******************************************************************************/
-int plat_sip_handler(uint32_t smc_fid,
+int32_t plat_sip_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
@@ -55,64 +37,27 @@ int plat_sip_handler(uint32_t smc_fid,
void *handle,
uint64_t flags)
{
- int mce_ret;
+ int32_t ret = -ENOTSUP;
- /*
- * Convert SMC FID to SMC64 until the linux driver uses
- * SMC64 encoding.
- */
- smc_fid |= (SMC_64 << FUNCID_CC_SHIFT);
-
- switch (smc_fid) {
-
- /*
- * Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 -
- * 0x82FFFFFF SiP SMC space
- */
- case TEGRA_SIP_MCE_CMD_ENTER_CSTATE:
- case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO:
- case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME:
- case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS:
- case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS:
- case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED:
- case TEGRA_SIP_MCE_CMD_CC3_CTRL:
- case TEGRA_SIP_MCE_CMD_ECHO_DATA:
- case TEGRA_SIP_MCE_CMD_READ_VERSIONS:
- case TEGRA_SIP_MCE_CMD_ENUM_FEATURES:
- case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
- case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA:
- case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA:
- case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE:
- case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE:
- case TEGRA_SIP_MCE_CMD_ENABLE_LATIC:
- case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ:
- case TEGRA_SIP_MCE_CMD_MISC_CCPLEX:
-
- /* clean up the high bits */
- smc_fid &= MCE_CMD_MASK;
-
- /* execute the command and store the result */
- mce_ret = mce_command_handler(smc_fid, x1, x2, x3);
- write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, mce_ret);
-
- return 0;
-
- case TEGRA_SIP_SYSTEM_SHUTDOWN_STATE:
-
- /* clean up the high bits */
- x1 = (uint32_t)x1;
+ (void)x1;
+ (void)x4;
+ (void)cookie;
+ (void)flags;
+ if (smc_fid == TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND) {
/*
- * SC8 is a special Tegra186 system state where the CPUs and
- * DRAM are powered down but the other subsystem is still
- * alive.
+ * System suspend mode is set if the platform ATF is
+ * running on VDK and there is a debug SIP call. This mode
+ * ensures that the debug path is exercised, instead of
+ * regular code path to suit the pre-silicon platform needs.
+ * This includes replacing the call to WFI, with calls to
+ * system suspend exit procedures.
*/
-
- return 0;
-
- default:
- break;
+ if (tegra_platform_is_virt_dev_kit()) {
+ tegra_fake_system_suspend = true;
+ ret = 0;
+ }
}
- return -ENOTSUP;
+ return ret;
}
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h b/plat/nvidia/tegra/soc/t194/plat_smmu.c
similarity index 89%
rename from plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h
rename to plat/nvidia/tegra/soc/t194/plat_smmu.c
index fc8669a0d3213a0c85f666caf522469d30db9577..1696d59108c4c5e862816eba3500b401c100c863 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h
+++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c
@@ -4,14 +4,25 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __SMMU_PLAT_CONFIG_H
-#define __SMMU_PLAT_CONFIG_H
-
-#include <mmio.h>
-#include <tegra_def.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
#include <smmu.h>
+#include <tegra_def.h>
+#include <tegra_mc_def.h>
-static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = {
+#define BOARD_SYSTEM_FPGA_BASE U(1)
+#define BASE_CONFIG_SMMU_DEVICES U(2)
+#define MAX_NUM_SMMU_DEVICES U(3)
+
+static uint32_t tegra_misc_read_32(uint32_t off)
+{
+ return mmio_read_32((uintptr_t)TEGRA_MISC_BASE + off);
+}
+
+/*******************************************************************************
+ * Array to hold SMMU context for Tegra194
+ ******************************************************************************/
+static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = {
_START_OF_TABLE_,
mc_make_sid_security_cfg(HDAR),
mc_make_sid_security_cfg(HOST1XDMAR),
@@ -400,29 +411,29 @@ static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = {
_END_OF_TABLE_,
};
-static inline uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off)
+/*******************************************************************************
+ * Handler to return the pointer to the SMMU's context struct
+ ******************************************************************************/
+smmu_regs_t *plat_get_smmu_ctx(void)
{
- if (smmu_id == 0)
- return mmio_read_32(TEGRA_SMMU0_BASE + off);
- else if (smmu_id == 1)
- return mmio_read_32(TEGRA_SMMU1_BASE + off);
- else if (smmu_id == 2)
- return mmio_read_32(TEGRA_SMMU2_BASE + off);
- else
- panic();
+ /* index of _END_OF_TABLE_ */
+ tegra194_smmu_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_smmu_context) - 1U;
+
+ return tegra194_smmu_context;
}
-static inline void tegra_smmu_write_32(uint32_t smmu_id,
- uint32_t off, uint32_t val)
+/*******************************************************************************
+ * Handler to return the support SMMU devices number
+ ******************************************************************************/
+uint32_t plat_get_num_smmu_devices(void)
{
- if (smmu_id == 0)
- mmio_write_32(TEGRA_SMMU0_BASE + off, val);
- else if (smmu_id == 1)
- mmio_write_32(TEGRA_SMMU1_BASE + off, val);
- else if (smmu_id == 2)
- mmio_write_32(TEGRA_SMMU2_BASE + off, val);
- else
- panic();
-}
+ uint32_t ret_num = MAX_NUM_SMMU_DEVICES;
+ uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >> \
+ BOARD_SHIFT_BITS) & BOARD_MASK_BITS);
-#endif //__SMMU_PLAT_CONFIG_H
+ if (board_revid == BOARD_SYSTEM_FPGA_BASE) {
+ ret_num = BASE_CONFIG_SMMU_DEVICES;
+ }
+
+ return ret_num;
+}
diff --git a/plat/nvidia/tegra/soc/t194/plat_trampoline.S b/plat/nvidia/tegra/soc/t194/plat_trampoline.S
index e3ee5e5a5025a002b57ee54c4c089d7356811017..33c7e6f7897f75fb6fa7c5284401397f5be5dacd 100644
--- a/plat/nvidia/tegra/soc/t194/plat_trampoline.S
+++ b/plat/nvidia/tegra/soc/t194/plat_trampoline.S
@@ -10,27 +10,36 @@
#include <memctrl_v2.h>
#include <tegra_def.h>
-#define TEGRA186_SMMU_CTX_SIZE 0x490
+#define TEGRA194_STATE_SYSTEM_SUSPEND 0x5C7
+#define TEGRA194_STATE_SYSTEM_RESUME 0x600D
+#define TEGRA194_SMMU_CTX_SIZE 0x490
.align 4
- .globl tegra186_cpu_reset_handler
+ .globl tegra194_cpu_reset_handler
/* CPU reset handler routine */
-func tegra186_cpu_reset_handler
- /*
- * The TZRAM loses state during System Suspend. We use this
- * information to decide if the reset handler is running after a
- * System Suspend. Resume from system suspend requires restoring
- * the entire state from TZDRAM to TZRAM.
- */
- mov x0, #BL31_BASE
- ldr x0, [x0]
- cbnz x0, boot_cpu
+func tegra194_cpu_reset_handler
+ /* check if we are exiting system suspend state */
+ adr x0, __tegra194_system_suspend_state
+ ldr x1, [x0]
+ mov x2, #TEGRA194_STATE_SYSTEM_SUSPEND
+ lsl x2, x2, #16
+ add x2, x2, #TEGRA194_STATE_SYSTEM_SUSPEND
+ cmp x1, x2
+ bne boot_cpu
- /* resume from system suspend */
+ /* set system resume state */
+ mov x1, #TEGRA194_STATE_SYSTEM_RESUME
+ lsl x1, x1, #16
+ mov x2, #TEGRA194_STATE_SYSTEM_RESUME
+ add x1, x1, x2
+ str x1, [x0]
+ dsb sy
+
+ /* prepare to relocate to TZSRAM */
mov x0, #BL31_BASE
- adr x1, __tegra186_cpu_reset_handler_end
- adr x2, __tegra186_cpu_reset_handler_data
+ adr x1, __tegra194_cpu_reset_handler_end
+ adr x2, __tegra194_cpu_reset_handler_data
ldr x2, [x2, #8]
/* memcpy16 */
@@ -50,13 +59,13 @@ m_loop1:
b.ne m_loop1
boot_cpu:
- adr x0, __tegra186_cpu_reset_handler_data
+ adr x0, __tegra194_cpu_reset_handler_data
ldr x0, [x0]
br x0
-endfunc tegra186_cpu_reset_handler
+endfunc tegra194_cpu_reset_handler
/*
- * Tegra186 reset data (offset 0x0 - 0x2490)
+ * Tegra194 reset data (offset 0x0 - 0x2490)
*
* 0x0000: secure world's entrypoint
* 0x0008: BL31 size (RO + RW)
@@ -65,19 +74,71 @@ endfunc tegra186_cpu_reset_handler
*/
.align 4
- .type __tegra186_cpu_reset_handler_data, %object
- .globl __tegra186_cpu_reset_handler_data
-__tegra186_cpu_reset_handler_data:
+ .type __tegra194_cpu_reset_handler_data, %object
+ .globl __tegra194_cpu_reset_handler_data
+__tegra194_cpu_reset_handler_data:
.quad tegra_secure_entrypoint
.quad __BL31_END__ - BL31_BASE
- .globl __tegra186_smmu_ctx_start
-__tegra186_smmu_ctx_start:
- .rept TEGRA186_SMMU_CTX_SIZE
+
+ .globl __tegra194_system_suspend_state
+__tegra194_system_suspend_state:
+ .quad 0
+
+ .align 4
+__tegra194_smmu_context:
+ .rept TEGRA194_SMMU_CTX_SIZE
.quad 0
.endr
- .size __tegra186_cpu_reset_handler_data, \
- . - __tegra186_cpu_reset_handler_data
+ .size __tegra194_cpu_reset_handler_data, \
+ . - __tegra194_cpu_reset_handler_data
.align 4
- .globl __tegra186_cpu_reset_handler_end
-__tegra186_cpu_reset_handler_end:
+ .globl __tegra194_cpu_reset_handler_end
+__tegra194_cpu_reset_handler_end:
+
+ .globl tegra194_get_cpu_reset_handler_size
+ .globl tegra194_get_cpu_reset_handler_base
+ .globl tegra194_get_smmu_ctx_offset
+ .globl tegra194_set_system_suspend_entry
+
+/* return size of the CPU reset handler */
+func tegra194_get_cpu_reset_handler_size
+ adr x0, __tegra194_cpu_reset_handler_end
+ adr x1, tegra194_cpu_reset_handler
+ sub x0, x0, x1
+ ret
+endfunc tegra194_get_cpu_reset_handler_size
+
+/* return the start address of the CPU reset handler */
+func tegra194_get_cpu_reset_handler_base
+ adr x0, tegra194_cpu_reset_handler
+ ret
+endfunc tegra194_get_cpu_reset_handler_base
+
+/* return the size of the SMMU context */
+func tegra194_get_smmu_ctx_offset
+ adr x0, __tegra194_smmu_context
+ adr x1, tegra194_cpu_reset_handler
+ sub x0, x0, x1
+ ret
+endfunc tegra194_get_smmu_ctx_offset
+
+/* set system suspend state before SC7 entry */
+func tegra194_set_system_suspend_entry
+ mov x0, #TEGRA_MC_BASE
+ mov x3, #MC_SECURITY_CFG3_0
+ ldr w1, [x0, x3]
+ lsl x1, x1, #32
+ mov x3, #MC_SECURITY_CFG0_0
+ ldr w2, [x0, x3]
+ orr x3, x1, x2 /* TZDRAM base */
+ adr x0, __tegra194_system_suspend_state
+ adr x1, tegra194_cpu_reset_handler
+ sub x2, x0, x1 /* offset in TZDRAM */
+ mov x0, #TEGRA194_STATE_SYSTEM_SUSPEND
+ lsl x0, x0, #16
+ add x0, x0, #TEGRA194_STATE_SYSTEM_SUSPEND
+ str x0, [x3, x2] /* set value in TZDRAM */
+ dsb sy
+ ret
+endfunc tegra194_set_system_suspend_entry
diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk
index b6bc442144861524007e29d31312cdc9f61445f4..5ec1af296660e385aed93450e3c40ff434225217 100644
--- a/plat/nvidia/tegra/soc/t194/platform_t194.mk
+++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk
@@ -5,15 +5,12 @@
#
# platform configs
-ENABLE_AFI_DEVICE := 0
-$(eval $(call add_define,ENABLE_AFI_DEVICE))
+ENABLE_CONSOLE_SPE := 0
+$(eval $(call add_define,ENABLE_CONSOLE_SPE))
ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 0
$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS))
-ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM := 1
-$(eval $(call add_define,ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM))
-
RELOCATE_TO_BL31_BASE := 1
$(eval $(call add_define,RELOCATE_TO_BL31_BASE))
@@ -23,9 +20,6 @@ $(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS))
ENABLE_SMMU_DEVICE := 1
$(eval $(call add_define,ENABLE_SMMU_DEVICE))
-NUM_SMMU_DEVICES := 3
-$(eval $(call add_define,NUM_SMMU_DEVICES))
-
RESET_TO_BL31 := 1
PROGRAMMABLE_RESET_ADDRESS := 1
@@ -36,32 +30,37 @@ COLD_BOOT_SINGLE_CPU := 1
TZDRAM_BASE := 0x40000000
$(eval $(call add_define,TZDRAM_BASE))
-PLATFORM_CLUSTER_COUNT := 2
+PLATFORM_CLUSTER_COUNT := 4
$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
-PLATFORM_MAX_CPUS_PER_CLUSTER := 4
+PLATFORM_MAX_CPUS_PER_CLUSTER := 2
$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
-MAX_XLAT_TABLES := 24
+MAX_XLAT_TABLES := 25
$(eval $(call add_define,MAX_XLAT_TABLES))
-MAX_MMAP_REGIONS := 24
+MAX_MMAP_REGIONS := 30
$(eval $(call add_define,MAX_MMAP_REGIONS))
# platform files
PLAT_INCLUDES += -I${SOC_DIR}/drivers/include
-BL31_SOURCES += lib/cpus/aarch64/denver.S \
+BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
+ lib/cpus/aarch64/denver.S \
${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \
${COMMON_DIR}/drivers/smmu/smmu.c \
${SOC_DIR}/drivers/mce/mce.c \
${SOC_DIR}/drivers/mce/nvg.c \
${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \
+ ${SOC_DIR}/drivers/se/se.c \
+ ${SOC_DIR}/plat_memctrl.c \
${SOC_DIR}/plat_psci_handlers.c \
${SOC_DIR}/plat_setup.c \
${SOC_DIR}/plat_secondary.c \
- ${SOC_DIR}/plat_sip_calls.c
+ ${SOC_DIR}/plat_sip_calls.c \
+ ${SOC_DIR}/plat_smmu.c \
+ ${SOC_DIR}/plat_trampoline.S
-ifeq (${ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM}, 1)
-BL31_SOURCES += ${SOC_DIR}/plat_trampoline.S
+ifeq (${ENABLE_CONSOLE_SPE},1)
+BL31_SOURCES += ${COMMON_DIR}/drivers/spe/shared_console.S
endif
diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c
index 2a2d102f7a8c5990aa86a4305883c1638cf1098d..bfa818419f451714ac71bc2f3c640c77cec3d850 100644
--- a/plat/nvidia/tegra/soc/t210/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t210/plat_setup.c
@@ -114,14 +114,30 @@ static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = {
};
/*******************************************************************************
- * Retrieve the UART controller base to be used as the console
+ * Enable console corresponding to the console ID
******************************************************************************/
-uint32_t plat_get_console_from_id(int id)
+void plat_enable_console(int32_t id)
{
- if (id > TEGRA210_MAX_UART_PORTS)
- return 0;
+ static console_16550_t uart_console;
+ uint32_t console_clock;
- return tegra210_uart_addresses[id];
+ if ((id > 0) && (id < TEGRA210_MAX_UART_PORTS)) {
+ /*
+ * Reference clock used by the FPGAs is a lot slower.
+ */
+ if (tegra_platform_is_fpga()) {
+ console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
+ } else {
+ console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
+ }
+
+ (void)console_16550_register(tegra210_uart_addresses[id],
+ console_clock,
+ TEGRA_CONSOLE_BAUDRATE,
+ &uart_console);
+ console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT |
+ CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
+ }
}
/*******************************************************************************