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adam.huang
Arm Trusted Firmware
Commits
535f185a
Commit
535f185a
authored
Dec 08, 2016
by
danh-arm
Committed by
GitHub
Dec 08, 2016
Browse files
Merge pull request #770 from yatharth-arm/yk/AArch32_fixes
AArch32: Miscellaneous fixes in the AArch32 code
parents
7ffd088f
69d59e0c
Changes
3
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Side-by-side
drivers/arm/pl011/aarch32/pl011_console.S
View file @
535f185a
...
...
@@ -118,15 +118,15 @@ func console_core_putc
1
:
/
*
Check
if
the
transmit
FIFO
is
full
*/
ldr
r2
,
[
r1
,
#
UARTFR
]
tst
r2
,
#
PL011_UARTFR_TXFF
_BIT
be
q
1
b
tst
r2
,
#
PL011_UARTFR_TXFF
b
n
e
1
b
mov
r2
,
#
0xD
str
r2
,
[
r1
,
#
UARTDR
]
2
:
/
*
Check
if
the
transmit
FIFO
is
full
*/
ldr
r2
,
[
r1
,
#
UARTFR
]
tst
r2
,
#
PL011_UARTFR_TXFF
_BIT
be
q
2
b
tst
r2
,
#
PL011_UARTFR_TXFF
b
n
e
2
b
str
r0
,
[
r1
,
#
UARTDR
]
bx
lr
putc_error
:
...
...
@@ -149,8 +149,8 @@ func console_core_getc
1
:
/
*
Check
if
the
receive
FIFO
is
empty
*/
ldr
r1
,
[
r0
,
#
UARTFR
]
tst
r1
,
#
PL011_UARTFR_RXFE
_BIT
be
q
1
b
tst
r1
,
#
PL011_UARTFR_RXFE
b
n
e
1
b
ldr
r1
,
[
r0
,
#
UARTDR
]
mov
r0
,
r1
bx
lr
...
...
include/lib/aarch32/smcc_macros.S
View file @
535f185a
...
...
@@ -109,7 +109,13 @@
msr
spsr_und
,
r9
msr
sp_und
,
r10
msr
lr_und
,
r11
msr
spsr
,
r12
/
*
*
Use
the
`
_fsxc
`
suffix
explicitly
to
instruct
the
assembler
*
to
update
all
the
32
bits
of
SPSR
.
Else
,
by
default
,
the
*
assembler
assumes
`
_fc
`
suffix
which
only
modifies
*
f
->[
31
:
24
]
and
c
->[
7
:
0
]
bits
of
SPSR
.
*/
msr
spsr_fsxc
,
r12
/
*
Restore
the
rest
of
the
general
purpose
registers
*/
ldm
r0
,
{
r0
-
r12
}
...
...
plat/common/aarch32/platform_helpers.S
View file @
535f185a
...
...
@@ -31,26 +31,11 @@
#include <arch.h>
#include <asm_macros.S>
.
weak
plat_my_core_pos
.
weak
plat_reset_handler
.
weak
plat_disable_acp
.
weak
platform_mem_init
.
weak
plat_panic_handler
/
*
-----------------------------------------------------
*
int
plat_my_core_pos
(
void
)
;
*
With
this
function
:
CorePos
=
(
ClusterId
*
4
)
+
*
CoreId
*
-----------------------------------------------------
*/
func
plat_my_core_pos
ldcopr
r0
,
MPIDR
and
r1
,
r0
,
#
MPIDR_CPU_MASK
and
r0
,
r0
,
#
MPIDR_CLUSTER_MASK
add
r0
,
r1
,
r0
,
LSR
#
6
bx
lr
endfunc
plat_my_core_pos
/
*
-----------------------------------------------------
*
Placeholder
function
which
should
be
redefined
by
*
each
platform
.
...
...
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