Commit 54718418 authored by Soby Mathew's avatar Soby Mathew
Browse files

Remove the IMF_READ_INTERRUPT_ID build option

The IMF_READ_INTERRUPT_ID build option enables a feature where the interrupt
ID of the highest priority pending interrupt is passed as a parameter to the
interrupt handler registered for that type of interrupt. This additional read
of highest pending interrupt id from GIC is problematic as it is possible that
the original interrupt may get deasserted and another interrupt of different
type maybe become the highest pending interrupt. Hence it is safer to prevent
such behaviour by removing the IMF_READ_INTERRUPT_ID build option.

The `id` parameter of the interrupt handler `interrupt_type_handler_t` is
now made a reserved parameter with this patch. It will always contain
INTR_ID_UNAVAILABLE.

Fixes ARM-software/tf-issues#307

Change-Id: I2173aae1dd37edad7ba6bdfb1a99868635fa34de
parent b39908af
...@@ -130,16 +130,6 @@ ...@@ -130,16 +130,6 @@
mov x21, x0 mov x21, x0
mov x0, #INTR_ID_UNAVAILABLE mov x0, #INTR_ID_UNAVAILABLE
#if IMF_READ_INTERRUPT_ID
/*
* Read the id of the highest priority pending interrupt. If
* no interrupt is asserted then return to where we came from.
*/
mov x19, #INTR_ID_UNAVAILABLE
bl plat_ic_get_pending_interrupt_id
cmp x19, x0
b.eq interrupt_exit_\label
#endif
/* Set the current security state in the 'flags' parameter */ /* Set the current security state in the 'flags' parameter */
mrs x2, scr_el3 mrs x2, scr_el3
......
...@@ -60,13 +60,6 @@ endif ...@@ -60,13 +60,6 @@ endif
BL31_LINKERFILE := bl31/bl31.ld.S BL31_LINKERFILE := bl31/bl31.ld.S
# Flag used by the generic interrupt management framework to determine if
# upon the assertion of an interrupt, it should pass the interrupt id or not
IMF_READ_INTERRUPT_ID := 0
$(eval $(call assert_boolean,IMF_READ_INTERRUPT_ID))
$(eval $(call add_define,IMF_READ_INTERRUPT_ID))
# Flag used to inidicate if Crash reporting via console should be included # Flag used to inidicate if Crash reporting via console should be included
# in BL3-1. This defaults to being present in DEBUG builds only # in BL3-1. This defaults to being present in DEBUG builds only
ifndef CRASH_REPORTING ifndef CRASH_REPORTING
......
...@@ -293,11 +293,9 @@ This component declares the following prototype for a handler of an interrupt ty ...@@ -293,11 +293,9 @@ This component declares the following prototype for a handler of an interrupt ty
void *handle, void *handle,
void *cookie); void *cookie);
The value of the `id` parameter depends upon the definition of the The `id` is parameter is reserved and could be used in the future for passing
`IMF_READ_INTERRUPT_ID` build time flag. When the flag is defined, `id` contains the interrupt id of the highest pending interrupt only if there is a foolproof
the number of the highest priority pending interrupt of the type that this way of determining the id. Currently it contains `INTR_ID_UNAVAILABLE`.
handler was registered for. When the flag is not defined `id` contains
`INTR_ID_UNAVAILABLE`.
The `flags` parameter contains miscellaneous information as follows. The `flags` parameter contains miscellaneous information as follows.
...@@ -583,11 +581,10 @@ responsible for: ...@@ -583,11 +581,10 @@ responsible for:
irrecoverable error condition. irrecoverable error condition.
6. Calling the registered handler function for the interrupt type generated. 6. Calling the registered handler function for the interrupt type generated.
The firmware also determines the interrupt id if the IMF_READ_INTERRUPT_ID The `id` parameter is set to `INTR_ID_UNAVAILABLE` currently. The id along
build time flag is set. The id is set to `INTR_ID_UNAVAILABLE` if the flag with the current security state and a reference to the `cpu_context_t`
is not set. The id along with the current security state and a reference to structure for the current security state are passed to the handler function
the `cpu_context_t` structure for the current security state are passed to as its arguments.
the handler function as its arguments.
The handler function returns a reference to the per-cpu `cpu_context_t` The handler function returns a reference to the per-cpu `cpu_context_t`
structure for the target security state. structure for the target security state.
......
...@@ -1473,9 +1473,8 @@ of interrupt depends upon the id value as follows. ...@@ -1473,9 +1473,8 @@ of interrupt depends upon the id value as follows.
Return : uint32_t Return : uint32_t
This API returns the id of the highest priority pending interrupt at the This API returns the id of the highest priority pending interrupt at the
platform IC. The IMF passes the id returned by this API to the registered platform IC. INTR_ID_UNAVAILABLE is returned when there is no interrupt
handler for the pending interrupt if the `IMF_READ_INTERRUPT_ID` build time flag pending.
is set. INTR_ID_UNAVAILABLE is returned when there is no interrupt pending.
ARM standard platforms read the _Highest Priority Pending Interrupt ARM standard platforms read the _Highest Priority Pending Interrupt
Register_ (`GICC_HPPIR`) to determine the id of the pending interrupt. The id Register_ (`GICC_HPPIR`) to determine the id of the pending interrupt. The id
......
...@@ -250,11 +250,6 @@ performed. ...@@ -250,11 +250,6 @@ performed.
is used to determine the number of valid slave interfaces available in the is used to determine the number of valid slave interfaces available in the
ARM CCI driver. Default is 400 (that is, CCI-400). ARM CCI driver. Default is 400 (that is, CCI-400).
* `IMF_READ_INTERRUPT_ID`: Boolean flag used by the interrupt management
framework to enable passing of the interrupt id to its handler. The id is
read using a platform GIC API. `INTR_ID_UNAVAILABLE` is passed instead if
this option set to 0. Default is 0.
* `RESET_TO_BL31`: Enable BL3-1 entrypoint as the CPU reset vector instead * `RESET_TO_BL31`: Enable BL3-1 entrypoint as the CPU reset vector instead
of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
entrypoint) or 1 (CPU reset to BL3-1 entrypoint). entrypoint) or 1 (CPU reset to BL3-1 entrypoint).
......
...@@ -85,11 +85,6 @@ static uint64_t opteed_sel1_interrupt_handler(uint32_t id, ...@@ -85,11 +85,6 @@ static uint64_t opteed_sel1_interrupt_handler(uint32_t id,
/* Check the security state when the exception was generated */ /* Check the security state when the exception was generated */
assert(get_interrupt_src_ss(flags) == NON_SECURE); assert(get_interrupt_src_ss(flags) == NON_SECURE);
#if IMF_READ_INTERRUPT_ID
/* Check the security status of the interrupt */
assert(plat_ic_get_interrupt_type(id) == INTR_TYPE_S_EL1);
#endif
/* Sanity check the pointer to this cpu's context */ /* Sanity check the pointer to this cpu's context */
assert(handle == cm_get_context(NON_SECURE)); assert(handle == cm_get_context(NON_SECURE));
......
...@@ -106,11 +106,6 @@ static uint64_t tspd_sel1_interrupt_handler(uint32_t id, ...@@ -106,11 +106,6 @@ static uint64_t tspd_sel1_interrupt_handler(uint32_t id,
/* Check the security state when the exception was generated */ /* Check the security state when the exception was generated */
assert(get_interrupt_src_ss(flags) == NON_SECURE); assert(get_interrupt_src_ss(flags) == NON_SECURE);
#if IMF_READ_INTERRUPT_ID
/* Check the security status of the interrupt */
assert(plat_ic_get_interrupt_type(id) == INTR_TYPE_S_EL1);
#endif
/* Sanity check the pointer to this cpu's context */ /* Sanity check the pointer to this cpu's context */
assert(handle == cm_get_context(NON_SECURE)); assert(handle == cm_get_context(NON_SECURE));
...@@ -173,10 +168,6 @@ static uint64_t tspd_ns_interrupt_handler(uint32_t id, ...@@ -173,10 +168,6 @@ static uint64_t tspd_ns_interrupt_handler(uint32_t id,
/* Check the security state when the exception was generated */ /* Check the security state when the exception was generated */
assert(get_interrupt_src_ss(flags) == SECURE); assert(get_interrupt_src_ss(flags) == SECURE);
#if IMF_READ_INTERRUPT_ID
/* Check the security status of the interrupt */
assert(plat_ic_get_interrupt_type(id) == INTR_TYPE_NS);
#endif
/* /*
* Disable the routing of NS interrupts from secure world to EL3 while * Disable the routing of NS interrupts from secure world to EL3 while
* interrupted on this core. * interrupted on this core.
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment