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Commit 5747ecab authored by danh-arm's avatar danh-arm Committed by GitHub
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Merge pull request #959 from hzhuang1/hikey960_v1 

Hikey960 v1
parents f9a050e4 7fe08b2b
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plat/hisilicon/hikey960/include/hi3660_crg.h 0 → 100644
View file @ 5747ecab
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HI3660_CRG_H__
#define __HI3660_CRG_H__
#define CRG_REG_BASE 0xFFF35000
#define CRG_PEREN0_REG (CRG_REG_BASE + 0x000)
#define CRG_PERDIS0_REG (CRG_REG_BASE + 0x004)
#define CRG_PERSTAT0_REG (CRG_REG_BASE + 0x008)
#define PEREN0_GT_CLK_AOMM (1 << 31)
#define CRG_PEREN1_REG (CRG_REG_BASE + 0x010)
#define CRG_PERDIS1_REG (CRG_REG_BASE + 0x014)
#define CRG_PERSTAT1_REG (CRG_REG_BASE + 0x018)
#define CRG_PEREN2_REG (CRG_REG_BASE + 0x020)
#define CRG_PERDIS2_REG (CRG_REG_BASE + 0x024)
#define CRG_PERSTAT2_REG (CRG_REG_BASE + 0x028)
#define PEREN2_HKADCSSI (1 << 24)
#define CRG_PEREN3_REG (CRG_REG_BASE + 0x030)
#define CRG_PERDIS3_REG (CRG_REG_BASE + 0x034)
#define CRG_PEREN4_REG (CRG_REG_BASE + 0x040)
#define CRG_PERDIS4_REG (CRG_REG_BASE + 0x044)
#define CRG_PERCLKEN4_REG (CRG_REG_BASE + 0x048)
#define CRG_PERSTAT4_REG (CRG_REG_BASE + 0x04C)
#define GT_ACLK_USB3OTG (1 << 1)
#define GT_CLK_USB3OTG_REF (1 << 0)
#define CRG_PEREN5_REG (CRG_REG_BASE + 0x050)
#define CRG_PERDIS5_REG (CRG_REG_BASE + 0x054)
#define CRG_PERSTAT5_REG (CRG_REG_BASE + 0x058)
#define CRG_PERRSTEN0_REG (CRG_REG_BASE + 0x060)
#define CRG_PERRSTDIS0_REG (CRG_REG_BASE + 0x064)
#define CRG_PERRSTSTAT0_REG (CRG_REG_BASE + 0x068)
#define CRG_PERRSTEN1_REG (CRG_REG_BASE + 0x06C)
#define CRG_PERRSTDIS1_REG (CRG_REG_BASE + 0x070)
#define CRG_PERRSTSTAT1_REG (CRG_REG_BASE + 0x074)
#define CRG_PERRSTEN2_REG (CRG_REG_BASE + 0x078)
#define CRG_PERRSTDIS2_REG (CRG_REG_BASE + 0x07C)
#define CRG_PERRSTSTAT2_REG (CRG_REG_BASE + 0x080)
#define PERRSTEN2_HKADCSSI (1 << 24)
#define CRG_PERRSTEN3_REG (CRG_REG_BASE + 0x084)
#define CRG_PERRSTDIS3_REG (CRG_REG_BASE + 0x088)
#define CRG_PERRSTSTAT3_REG (CRG_REG_BASE + 0x08C)
#define CRG_PERRSTEN4_REG (CRG_REG_BASE + 0x090)
#define CRG_PERRSTDIS4_REG (CRG_REG_BASE + 0x094)
#define CRG_PERRSTSTAT4_REG (CRG_REG_BASE + 0x098)
#define IP_RST_USB3OTG_MUX (1 << 8)
#define IP_RST_USB3OTG_AHBIF (1 << 7)
#define IP_RST_USB3OTG_32K (1 << 6)
#define IP_RST_USB3OTG (1 << 5)
#define IP_RST_USB3OTGPHY_POR (1 << 3)
#define CRG_PERRSTEN5_REG (CRG_REG_BASE + 0x09C)
#define CRG_PERRSTDIS5_REG (CRG_REG_BASE + 0x0A0)
#define CRG_PERRSTSTAT5_REG (CRG_REG_BASE + 0x0A4)
/* bit fields in CRG_PERI */
#define PERI_PCLK_PCTRL_BIT (1 << 31)
#define PERI_TIMER12_BIT (1 << 25)
#define PERI_TIMER11_BIT (1 << 24)
#define PERI_TIMER10_BIT (1 << 23)
#define PERI_TIMER9_BIT (1 << 22)
#define PERI_UART5_BIT (1 << 15)
#define PERI_UFS_BIT (1 << 12)
#define PERI_ARST_UFS_BIT (1 << 7)
#define PERI_PPLL2_EN_CPU (1 << 3)
#define PERI_PWM_BIT (1 << 0)
#define PERI_DDRC_BIT (1 << 0)
#define PERI_DDRC_D_BIT (1 << 4)
#define PERI_DDRC_C_BIT (1 << 3)
#define PERI_DDRC_B_BIT (1 << 2)
#define PERI_DDRC_A_BIT (1 << 1)
#define PERI_DDRC_DMUX_BIT (1 << 0)
#define CRG_CLKDIV0_REG (CRG_REG_BASE + 0x0A0)
#define SC_DIV_LPMCU_MASK ((0x1F << 5) << 16)
#define SC_DIV_LPMCU(x) (((x) & 0x1F) << 5)
#define CRG_CLKDIV1_REG (CRG_REG_BASE + 0x0B0)
#define SEL_LPMCU_PLL_MASK ((1 << 1) << 16)
#define SEL_SYSBUS_MASK ((1 << 0) << 16)
#define SEL_LPMCU_PLL1 (1 << 1)
#define SEL_LPMCU_PLL0 (0 << 1)
#define SEL_SYSBUS_PLL0 (1 << 0)
#define SEL_SYSBUS_PLL1 (0 << 0)
#define CRG_CLKDIV3_REG (CRG_REG_BASE + 0x0B4)
#define CRG_CLKDIV5_REG (CRG_REG_BASE + 0x0BC)
#define CRG_CLKDIV8_REG (CRG_REG_BASE + 0x0C8)
#define CRG_CLKDIV12_REG (CRG_REG_BASE + 0x0D8)
#define SC_DIV_A53HPM_MASK (0x7 << 13)
#define SC_DIV_A53HPM(x) (((x) & 0x7) << 13)
#define CRG_CLKDIV16_REG (CRG_REG_BASE + 0x0E8)
#define DDRC_CLK_SW_REQ_CFG_MASK (0x3 << 12)
#define DDRC_CLK_SW_REQ_CFG(x) (((x) & 0x3) << 12)
#define SC_DIV_UFSPHY_CFG_MASK (0x3 << 9)
#define SC_DIV_UFSPHY_CFG(x) (((x) & 0x3) << 9)
#define DDRCPLL_SW (1 << 8)
#define CRG_CLKDIV17_REG (CRG_REG_BASE + 0x0EC)
#define SC_DIV_UFS_PERIBUS (1 << 14)
#define CRG_CLKDIV18_REG (CRG_REG_BASE + 0x0F0)
#define CRG_CLKDIV19_REG (CRG_REG_BASE + 0x0F4)
#define CRG_CLKDIV20_REG (CRG_REG_BASE + 0x0F8)
#define CLKDIV20_GT_CLK_AOMM (1 << 3)
#define CRG_CLKDIV22_REG (CRG_REG_BASE + 0x100)
#define SEL_PLL_320M_MASK (1 << 16)
#define SEL_PLL2_320M (1 << 0)
#define SEL_PLL0_320M (0 << 0)
#define CRG_CLKDIV23_REG (CRG_REG_BASE + 0x104)
#define PERI_DDRC_SW_BIT (1 << 13)
#define DIV_CLK_DDRSYS_MASK (0x3 << 10)
#define DIV_CLK_DDRSYS(x) (((x) & 0x3) << 10)
#define GET_DIV_CLK_DDRSYS(x) (((x) & DIV_CLK_DDRSYS_MASK) >> 10)
#define DIV_CLK_DDRCFG_MASK (0x6 << 5)
#define DIV_CLK_DDRCFG(x) (((x) & 0x6) << 5)
#define GET_DIV_CLK_DDRCFG(x) (((x) & DIV_CLK_DDRCFG_MASK) >> 5)
#define DIV_CLK_DDRC_MASK 0x1F
#define DIV_CLK_DDRC(x) ((x) & DIV_CLK_DDRC_MASK)
#define GET_DIV_CLK_DDRC(x) ((x) & DIV_CLK_DDRC_MASK)
#define CRG_CLKDIV25_REG (CRG_REG_BASE + 0x10C)
#define DIV_SYSBUS_PLL_MASK (0xF << 16)
#define DIV_SYSBUS_PLL(x) ((x) & 0xF)
#define CRG_PERI_CTRL2_REG (CRG_REG_BASE + 0x128)
#define PERI_TIME_STAMP_CLK_MASK (0x7 << 28)
#define PERI_TIME_STAMP_CLK_DIV(x) (((x) & 0x7) << 22)
#define CRG_ISODIS_REG (CRG_REG_BASE + 0x148)
#define CRG_PERPWREN_REG (CRG_REG_BASE + 0x150)
#define CRG_PEREN7_REG (CRG_REG_BASE + 0x420)
#define CRG_PERDIS7_REG (CRG_REG_BASE + 0x424)
#define CRG_PERSTAT7_REG (CRG_REG_BASE + 0x428)
#define GT_CLK_UFSPHY_CFG (1 << 14)
#define CRG_PEREN8_REG (CRG_REG_BASE + 0x430)
#define CRG_PERDIS8_REG (CRG_REG_BASE + 0x434)
#define CRG_PERSTAT8_REG (CRG_REG_BASE + 0x438)
#define PERI_DMC_D_BIT (1 << 22)
#define PERI_DMC_C_BIT (1 << 21)
#define PERI_DMC_B_BIT (1 << 20)
#define PERI_DMC_A_BIT (1 << 19)
#define PERI_DMC_BIT (1 << 18)
#define CRG_PEREN11_REG (CRG_REG_BASE + 0x460)
#define PPLL1_GATE_CPU (1 << 18)
#define CRG_PERSTAT11_REG (CRG_REG_BASE + 0x46C)
#define PPLL3_EN_STAT (1 << 21)
#define PPLL2_EN_STAT (1 << 20)
#define PPLL1_EN_STAT (1 << 19)
#define CRG_IVP_SEC_RSTDIS_REG (CRG_REG_BASE + 0xC04)
#define CRG_ISP_SEC_RSTDIS_REG (CRG_REG_BASE + 0xC84)
#define CRG_RVBAR(c, n) (0xE00 + (0x10 * c) + (0x4 * n))
#define CRG_GENERAL_SEC_RSTEN_REG (CRG_REG_BASE + 0xE20)
#define CRG_GENERAL_SEC_RSTDIS_REG (CRG_REG_BASE + 0xE24)
#define IP_RST_GPIO0_SEC (1 << 2)
#define CRG_GENERAL_SEC_CLKDIV0_REG (CRG_REG_BASE + 0xE90)
#define SC_DIV_AO_HISE_MASK 3
#define SC_DIV_AO_HISE(x) ((x) & 0x3)
#endif /* __HI3660_CRG_H__ */
plat/hisilicon/hikey960/include/hi3660_hkadc.h 0 → 100644
View file @ 5747ecab
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HI3660_HKADC_H__
#define __HI3660_HKADC_H__
#define HKADC_SSI_REG_BASE 0xE82B8000
#define HKADC_DSP_START_REG (HKADC_SSI_REG_BASE + 0x000)
#define HKADC_WR_NUM_REG (HKADC_SSI_REG_BASE + 0x008)
#define HKADC_DSP_START_CLR_REG (HKADC_SSI_REG_BASE + 0x01C)
#define HKADC_WR01_DATA_REG (HKADC_SSI_REG_BASE + 0x020)
#define WR1_WRITE_MODE (1 << 31)
#define WR1_READ_MODE (0 << 31)
#define WR1_ADDR(x) (((x) & 0x7F) << 24)
#define WR1_DATA(x) (((x) & 0xFF) << 16)
#define WR0_WRITE_MODE (1 << 15)
#define WR0_READ_MODE (0 << 15)
#define WR0_ADDR(x) (((x) & 0x7F) << 8)
#define WR0_DATA(x) ((x) & 0xFF)
#define HKADC_WR23_DATA_REG (HKADC_SSI_REG_BASE + 0x024)
#define HKADC_WR45_DATA_REG (HKADC_SSI_REG_BASE + 0x028)
#define HKADC_DELAY01_REG (HKADC_SSI_REG_BASE + 0x030)
#define HKADC_DELAY23_REG (HKADC_SSI_REG_BASE + 0x034)
#define HKADC_DELAY45_REG (HKADC_SSI_REG_BASE + 0x038)
#define HKADC_DSP_RD2_DATA_REG (HKADC_SSI_REG_BASE + 0x048)
#define HKADC_DSP_RD3_DATA_REG (HKADC_SSI_REG_BASE + 0x04C)
/* HKADC Internal Registers */
#define HKADC_CTRL_ADDR 0x00
#define HKADC_START_ADDR 0x01
#define HKADC_DATA1_ADDR 0x03 /* high 8 bits */
#define HKADC_DATA0_ADDR 0x04 /* low 8 bits */
#define HKADC_MODE_CFG 0x0A
#define HKADC_VALUE_HIGH 0x0FF0
#define HKADC_VALUE_LOW 0x000F
#define HKADC_VALID_VALUE 0x0FFF
#define HKADC_CHANNEL_MAX 15
#define HKADC_VREF_1V8 1800
#define HKADC_ACCURACY 0x0FFF
#define HKADC_WR01_VALUE ((HKADC_START_ADDR << 24) | \
(0x1 << 16))
#define HKADC_WR23_VALUE ((0x1 << 31) | \
(HKADC_DATA0_ADDR << 24) | \
(1 << 15) | \
(HKADC_DATA1_ADDR << 8))
#define HKADC_WR45_VALUE (0x80)
#define HKADC_CHANNEL0_DELAY01_VALUE ((0x0700 << 16) | 0xFFFF)
#define HKADC_DELAY01_VALUE ((0x0700 << 16) | 0x0200)
#define HKADC_DELAY23_VALUE ((0x00C8 << 16) | 0x00C8)
#define START_DELAY_TIMEOUT 2000
#define HKADC_WR_NUM_VALUE 4
#endif /* __HI3660_HKADC_H__ */
plat/hisilicon/hikey960/include/hi3660_mem_map.h 0 → 100644
View file @ 5747ecab
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HI3660_MEM_MAP__
#define __HI3660_MEM_MAP__
#define HISI_DATA_HEAD_BASE (0x89C44400)
#define HISI_RESERVED_MEM_BASE (0x89C80000)
#define HISI_RESERVED_MEM_SIZE (0x00040000)
#define HISI_DATA0_BASE (0x89C96180)
#define HISI_DATA0_SIZE (0x000003A0)
#define HISI_DATA1_BASE (0x89C93480)
#define HISI_DATA1_SIZE (0x00002D00)
#endif /* __HI3660_MEM_MAP__ */
plat/hisilicon/hikey960/include/hisi_ipc.h 0 → 100644
View file @ 5747ecab
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HISI_IPC_H__
#define __HISI_IPC_H__
enum pm_mode {
PM_ON = 0,
PM_OFF,
};
void hisi_ipc_pm_on_off(unsigned int core, unsigned int cluster,
enum pm_mode mode);
void hisi_ipc_pm_suspend(unsigned int core, unsigned int cluster,
unsigned int affinity_level);
void hisi_ipc_psci_system_off(unsigned int core, unsigned int cluster);
void hisi_ipc_psci_system_reset(unsigned int core, unsigned int cluster,
unsigned int cmd_id);
int hisi_ipc_init(void);
#endif /* __HISI_IPC_H__ */
plat/hisilicon/hikey960/include/plat_macros.S 0 → 100644
View file @ 5747ecab
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __PLAT_MACROS_S__
#define __PLAT_MACROS_S__
#include <cci.h>
#include <hi3660.h>
#include <gic_v2.h>
#include <platform_def.h>
.section .rodata.gic_reg_name, "aS"
gicc_regs:
.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
gicd_pend_reg:
.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
" Offset:\t\t\tvalue\n"
newline:
.asciz "\n"
spacer:
.asciz ":\t\t0x"
.section .rodata.cci_reg_name, "aS"
cci_iface_regs:
.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
/* ---------------------------------------------
* The below macro prints out relevant GIC
* registers whenever an unhandled exception is
* taken in BL31.
* ---------------------------------------------
*/
.macro plat_crash_print_regs
mov_imm x16, GICD_REG_BASE
mov_imm x17, GICC_REG_BASE
/* Load the gicc reg list to x6 */
adr x6, gicc_regs
/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
ldr w8, [x17, #GICC_HPPIR]
ldr w9, [x17, #GICC_AHPPIR]
ldr w10, [x17, #GICC_CTLR]
/* Store to the crash buf and print to cosole */
bl str_in_crash_buf_print
/* Print the GICD_ISPENDR regs */
add x7, x16, #GICD_ISPENDR
adr x4, gicd_pend_reg
bl asm_print_str
2:
sub x4, x7, x16
cmp x4, #0x280
b.eq 1f
bl asm_print_hex
adr x4, spacer
bl asm_print_str
ldr x4, [x7], #8
bl asm_print_hex
adr x4, newline
bl asm_print_str
b 2b
1:
adr x6, cci_iface_regs
/* Store in x7 the base address of the first interface */
mov_imm x7, (CCI400_REG_BASE + SLAVE_IFACE_OFFSET( \
CCI400_SL_IFACE3_CLUSTER_IX))
ldr w8, [x7, #SNOOP_CTRL_REG]
/* Store in x7 the base address of the second interface */
mov_imm x7, (CCI400_REG_BASE + SLAVE_IFACE_OFFSET( \
CCI400_SL_IFACE4_CLUSTER_IX))
ldr w9, [x7, #SNOOP_CTRL_REG]
/* Store to the crash buf and print to console */
bl str_in_crash_buf_print
.endm
#endif /* __PLAT_MACROS_S__ */
plat/hisilicon/hikey960/include/platform_def.h 0 → 100644
View file @ 5747ecab
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __PLATFORM_DEF_H__
#define __PLATFORM_DEF_H__
#include <arch.h>
#include "../hikey960_def.h"
/*
* Generic platform constants
*/
/* Size of cacheable stacks */
#define PLATFORM_STACK_SIZE 0x800
#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
#define PLATFORM_CACHE_LINE_SIZE 64
#define PLATFORM_CLUSTER_COUNT 2
#define PLATFORM_CORE_COUNT_PER_CLUSTER 4
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
PLATFORM_CORE_COUNT_PER_CLUSTER)
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
PLATFORM_CLUSTER_COUNT + 1)
#define PLAT_MAX_RET_STATE 1
#define PLAT_MAX_OFF_STATE 2
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
/* UFS RPMB and UFS User Data */
#define MAX_IO_BLOCK_DEVICES 2
/*
* Platform memory map related constants
*/
/*
* BL1 specific defines.
*/
#define BL1_RO_BASE (0x1AC00000)
#define BL1_RO_LIMIT (BL1_RO_BASE + 0x10000)
#define BL1_RW_BASE (BL1_RO_LIMIT) /* 1AC1_0000 */
#define BL1_RW_SIZE (0x00188000)
#define BL1_RW_LIMIT (0x1B000000)
/*
* BL2 specific defines.
*/
#define BL2_BASE (BL1_RW_BASE + 0x8000) /* 1AC1_8000 */
#define BL2_LIMIT (BL2_BASE + 0x40000) /* 1AC5_8000 */
/*
* BL31 specific defines.
*/
#define BL31_BASE (BL2_LIMIT) /* 1AC5_8000 */
#define BL31_LIMIT (BL31_BASE + 0x40000) /* 1AC9_8000 */
#define NS_BL1U_BASE (BL31_LIMIT) /* 1AC9_8000 */
#define NS_BL1U_SIZE (0x00100000)
#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
#define HIKEY960_NS_IMAGE_OFFSET (0x1AC18000) /* offset in l-loader */
#define HIKEY960_NS_TMP_OFFSET (0x1AE00000)
#define SCP_BL2_BASE BL31_BASE
#define SCP_MEM_BASE (0x89C80000)
#define SCP_MEM_SIZE (0x00040000)
/*
* Platform specific page table and MMU setup constants
*/
#define ADDR_SPACE_SIZE (1ull << 32)
#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL31
#define MAX_XLAT_TABLES 3
#endif
#define MAX_MMAP_REGIONS 16
/*
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
* to the platform as it might have a combination of integrated and external
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
* line at any cache level. They could belong to different cpus/clusters &
* get written while being protected by different locks causing corruption of
* a valid mailbox address.
*/
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
#endif /* __PLATFORM_DEF_H__ */
plat/hisilicon/hikey960/platform.mk 0 → 100644
View file @ 5747ecab
#
# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
CRASH_CONSOLE_BASE := PL011_UART6_BASE
COLD_BOOT_SINGLE_CPU := 1
PROGRAMMABLE_RESET_ADDRESS := 1
# Process flags
$(eval $(call add_define,CRASH_CONSOLE_BASE))
$(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw))
ENABLE_PLAT_COMPAT := 0
USE_COHERENT_MEM := 1
PLAT_INCLUDES := -Iinclude/common/tbbr \
-Iplat/hisilicon/hikey960/include
PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
lib/aarch64/xlat_tables.c \
plat/hisilicon/hikey960/aarch64/hikey960_common.c \
plat/hisilicon/hikey960/hikey960_boardid.c
HIKEY960_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
plat/common/plat_gicv2.c
BL1_SOURCES += bl1/tbbr/tbbr_img_desc.c \
drivers/io/io_block.c \
drivers/io/io_fip.c \
drivers/io/io_storage.c \
drivers/synopsys/ufs/dw_ufs.c \
drivers/ufs/ufs.c \
lib/cpus/aarch64/cortex_a53.S \
plat/hisilicon/hikey960/aarch64/hikey960_helpers.S \
plat/hisilicon/hikey960/hikey960_bl1_setup.c \
plat/hisilicon/hikey960/hikey960_io_storage.c \
${HIKEY960_GIC_SOURCES}
BL2_SOURCES += drivers/io/io_block.c \
drivers/io/io_fip.c \
drivers/io/io_storage.c \
drivers/ufs/ufs.c \
plat/hisilicon/hikey960/hikey960_bl2_setup.c \
plat/hisilicon/hikey960/hikey960_io_storage.c \
plat/hisilicon/hikey960/hikey960_mcu_load.c
BL31_SOURCES += drivers/arm/cci/cci.c \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a72.S \
lib/cpus/aarch64/cortex_a73.S \
plat/common/aarch64/plat_psci_common.c \
plat/hisilicon/hikey960/aarch64/hikey960_helpers.S \
plat/hisilicon/hikey960/hikey960_bl31_setup.c \
plat/hisilicon/hikey960/hikey960_pm.c \
plat/hisilicon/hikey960/hikey960_topology.c \
plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c \
plat/hisilicon/hikey960/drivers/ipc/hisi_ipc.c \
${HIKEY960_GIC_SOURCES}
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