juno: Implement plat_interrupt_type_to_line() function

Change-Id: I87083b5891fa8037cdee567ebadeaa1952f52d0c

plat/juno/plat_gic.c

@@ -168,3 +168,30 @@ void gic_setup(void)
 	gic_cpuif_setup(GICC_BASE);
 	gic_distif_setup(GICD_BASE);
 }
+
+/*******************************************************************************
+ * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
+ * The interrupt controller knows which pin/line it uses to signal a type of
+ * interrupt. The platform knows which interrupt controller type is being used
+ * in a particular security state e.g. with an ARM GIC, normal world could use
+ * the GICv2 features while the secure world could use GICv3 features and vice
+ * versa.
+ * This function is exported by the platform to let the interrupt management
+ * framework determine for a type of interrupt and security state, which line
+ * should be used in the SCR_EL3 to control its routing to EL3. The interrupt
+ * line is represented as the bit position of the IRQ or FIQ bit in the SCR_EL3.
+ ******************************************************************************/
+uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
+{
+	assert(type == INTR_TYPE_S_EL1 ||
+	       type == INTR_TYPE_EL3 ||
+	       type == INTR_TYPE_NS);
+
+	assert(security_state == NON_SECURE || security_state == SECURE);
+
+	/*
+	 * We ignore the security state parameter because Juno is GICv2 only
+	 * so both normal and secure worlds are using ARM GICv2.
+	 */
+	return gicv2_interrupt_type_to_line(GICC_BASE, type);
+}

plat/juno/platform.h

@@ -388,6 +388,8 @@ extern void gic_cpuif_deactivate(unsigned int);
 extern void gic_cpuif_setup(unsigned int);
 extern void gic_pcpu_distif_setup(unsigned int);
 extern void gic_setup(void);
+extern uint32_t plat_interrupt_type_to_line(uint32_t type,
+					    uint32_t security_state);
 
 /* Declarations for fvp_topology.c */
 extern int plat_setup_topology(void);