rcar_gen3: drivers: qos: H3: Drop extra level of nesting

The extra level of nesting is not necessary, drop it.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I7b55a6fa53145ff0427e05656234917f486031df

drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c

@@ -235,8 +235,6 @@ void qos_init_h3_v11(void)
 	io_write_32(0xFFC51800, 0x00000001U);
 
 	/* CCI bus Leaf setting */
-	{
-
 	uint32_t modemr = io_read_32(RCAR_MODEMR);
 
 	modemr &= MODEMR_BOOT_CPU_MASK;
@@ -248,7 +246,6 @@ void qos_init_h3_v11(void)
 		io_write_32(0xF1380800, 0x00000001U);
 		io_write_32(0xF13C0800, 0x00000001U);
 	}
-	}
 
 	/* Resource Alloc start */
 	io_write_32(QOSCTRL_RAEN, 0x00000001U);

drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c

@@ -187,7 +187,6 @@ void qos_init_h3_v20(void)
 	io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
 
-	{
 	uint32_t i;
 
 	for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
@@ -210,7 +209,6 @@ void qos_init_h3_v20(void)
 		io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
 	}
 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-	}
 
 	/* 3DG bus Leaf setting */
 	io_write_32(GPU_ACT0, 0x00000000U);

drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c

@@ -194,7 +194,6 @@ void qos_init_h3_v30(void)
 	io_write_32(QOSCTRL_REF_ARS,
 		    ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_30 << 16)));
 
-	{
 	uint32_t i;
 
 	for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
@@ -217,7 +216,6 @@ void qos_init_h3_v30(void)
 		io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
 	}
 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-	}
 
 	/* AXI setting */
 	io_write_32(AXI_MMCR, 0x00010008U);

drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c

@@ -188,7 +188,6 @@ void qos_init_h3n_v30(void)
 	io_write_32(QOSCTRL_REF_ARS,
 		    ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N << 16)));
 
-	{
 	uint32_t i;
 
 	for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
@@ -211,7 +210,6 @@ void qos_init_h3n_v30(void)
 		io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
 	}
 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-	}
 
 	/* AXI setting */
 	io_write_32(AXI_MMCR, 0x00010008U);