diff --git a/include/lib/cpus/aarch64/cortex_matterhorn_elp_arm.h b/include/lib/cpus/aarch64/cortex_matterhorn_elp_arm.h
new file mode 100644
index 0000000000000000000000000000000000000000..309578ecd0e2e120a4cc9d6e7581ae4c7d9ed1c3
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_matterhorn_elp_arm.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_MATTERHORN_ELP_ARM_H
+#define CORTEX_MATTERHORN_ELP_ARM_H
+
+#define CORTEX_MATTERHORN_ELP_ARM_MIDR					U(0x410FD480)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_MATTERHORN_ELP_ARM_CPUECTLR_EL1				S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1			S3_0_C15_C2_7
+#define CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
+
+#endif /* CORTEX_MATTERHORN_ELP_ARM_H */
diff --git a/lib/cpus/aarch64/cortex_matterhorn_elp_arm.S b/lib/cpus/aarch64/cortex_matterhorn_elp_arm.S
new file mode 100644
index 0000000000000000000000000000000000000000..b0f81a20a3f287567c79766e01ddc7b1766057fc
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_matterhorn_elp_arm.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_matterhorn_elp_arm.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex Matterhorn ELP ARM must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex Matterhorn ELP ARM supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+	/* ----------------------------------------------------
+	 * HW will do the cache maintenance while powering down
+	 * ----------------------------------------------------
+	 */
+func cortex_matterhorn_elp_arm_core_pwr_dwn
+	/* ---------------------------------------------------
+	 * Enable CPU power down bit in power control register
+	 * ---------------------------------------------------
+	 */
+	mrs	x0, CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1
+	orr	x0, x0, #CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+	msr	CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1, x0
+	isb
+	ret
+endfunc cortex_matterhorn_elp_arm_core_pwr_dwn
+
+	/*
+	 * Errata printing function for Cortex Matterhorn_elp_arm. Must follow AAPCS.
+	 */
+#if REPORT_ERRATA
+func cortex_matterhorn_elp_arm_errata_report
+	ret
+endfunc cortex_matterhorn_elp_arm_errata_report
+#endif
+
+func cortex_matterhorn_elp_arm_reset_func
+	/* Disable speculative loads */
+	msr	SSBS, xzr
+	isb
+	ret
+endfunc cortex_matterhorn_elp_arm_reset_func
+
+	/* ---------------------------------------------
+	 * This function provides Cortex-Matterhorn_elp_arm specific
+	 * register information for crash reporting.
+	 * It needs to return with x6 pointing to
+	 * a list of register names in ascii and
+	 * x8 - x15 having values of registers to be
+	 * reported.
+	 * ---------------------------------------------
+	 */
+.section .rodata.cortex_matterhorn_elp_arm_regs, "aS"
+cortex_matterhorn_elp_arm_regs:  /* The ascii list of register names to be reported */
+	.asciz	"cpuectlr_el1", ""
+
+func cortex_matterhorn_elp_arm_cpu_reg_dump
+	adr	x6, cortex_matterhorn_elp_arm_regs
+	mrs	x8, CORTEX_MATTERHORN_ELP_ARM_CPUECTLR_EL1
+	ret
+endfunc cortex_matterhorn_elp_arm_cpu_reg_dump
+
+declare_cpu_ops cortex_matterhorn_elp_arm, CORTEX_MATTERHORN_ELP_ARM_MIDR, \
+	cortex_matterhorn_elp_arm_reset_func, \
+	cortex_matterhorn_elp_arm_core_pwr_dwn