From 6152de3b347203e062d974b1af9b286b1f5c138c Mon Sep 17 00:00:00 2001 From: Anthony Zhou Date: Wed, 20 Sep 2017 17:18:56 +0800 Subject: [PATCH] Tegra194: mce: fix defects flagged by MISRA scan Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Fix variable essential type doesn't match [Rule 10.3] Added curly braces ({}) around if/while statements in order to make them compound [Rule 15.6] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: Iaae2ecaba3caf1469c44910d4e6aed0661597a51 Signed-off-by: Anthony Zhou --- .../soc/t194/drivers/include/mce_private.h | 40 +++++++------- plat/nvidia/tegra/soc/t194/drivers/mce/mce.c | 52 +++++++++---------- plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 40 +++++++------- 3 files changed, 66 insertions(+), 66 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h index 415dc0f89..91e15247c 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -14,42 +14,42 @@ * Macros to prepare CSTATE info request ******************************************************************************/ /* Description of the parameters for UPDATE_CSTATE_INFO request */ -#define CLUSTER_CSTATE_MASK 0x7UL -#define CLUSTER_CSTATE_SHIFT 0X0UL -#define CLUSTER_CSTATE_UPDATE_BIT (1UL << 7) -#define CCPLEX_CSTATE_MASK 0x3UL -#define CCPLEX_CSTATE_SHIFT 8UL -#define CCPLEX_CSTATE_UPDATE_BIT (1UL << 15) -#define SYSTEM_CSTATE_MASK 0xFUL -#define SYSTEM_CSTATE_SHIFT 16UL -#define SYSTEM_CSTATE_UPDATE_BIT (1UL << 23) -#define CSTATE_WAKE_MASK_UPDATE_BIT (1UL << 31) -#define CSTATE_WAKE_MASK_SHIFT 32UL -#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFUL +#define CLUSTER_CSTATE_MASK 0x7U +#define CLUSTER_CSTATE_SHIFT 0X0U +#define CLUSTER_CSTATE_UPDATE_BIT (1U << 7) +#define CCPLEX_CSTATE_MASK 0x3U +#define CCPLEX_CSTATE_SHIFT 8U +#define CCPLEX_CSTATE_UPDATE_BIT (1U << 15) +#define SYSTEM_CSTATE_MASK 0xFU +#define SYSTEM_CSTATE_SHIFT 16U +#define SYSTEM_CSTATE_UPDATE_BIT (1U << 23) +#define CSTATE_WAKE_MASK_UPDATE_BIT (1U << 31) +#define CSTATE_WAKE_MASK_SHIFT 32U +#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFU /******************************************************************************* * Auto-CC3 control macros ******************************************************************************/ -#define MCE_AUTO_CC3_FREQ_MASK 0xFFUL -#define MCE_AUTO_CC3_FREQ_SHIFT 0UL -#define MCE_AUTO_CC3_ENABLE_BIT (1UL << 31) +#define MCE_AUTO_CC3_FREQ_MASK 0xFFU +#define MCE_AUTO_CC3_FREQ_SHIFT 0U +#define MCE_AUTO_CC3_ENABLE_BIT (1U << 31) /******************************************************************************* * Core ID mask (bits 3:0 in the online request) ******************************************************************************/ -#define MCE_CORE_ID_MASK 0xFUL +#define MCE_CORE_ID_MASK 0xFU /******************************************************************************* * Cache control macros ******************************************************************************/ -#define CACHE_CLEAN_SET (1UL << 0) -#define CACHE_CLEAN_INVAL_SET (1UL << 1) -#define CACHE_CLEAN_INVAL_TR_SET (1UL << 2) +#define CACHE_CLEAN_SET (1U << 0) +#define CACHE_CLEAN_INVAL_SET (1U << 1) +#define CACHE_CLEAN_INVAL_TR_SET (1U << 2) /******************************************************************************* * C-state statistics macros ******************************************************************************/ -#define MCE_STAT_ID_SHIFT 16UL +#define MCE_STAT_ID_SHIFT 16U /* declarations for NVG handler functions */ uint64_t nvg_get_version(void); diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c index 355a5474e..08f5db82c 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c @@ -46,11 +46,11 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, cpu_context_t *ctx = cm_get_context(NON_SECURE); gp_regs_t *gp_regs = get_gpregs_ctx(ctx); - assert(ctx); - assert(gp_regs); + assert(ctx != NULL); + assert(gp_regs != NULL); switch (cmd) { - case MCE_CMD_ENTER_CSTATE: + case (uint64_t)MCE_CMD_ENTER_CSTATE: ret = nvg_enter_cstate((uint32_t)arg0, (uint32_t)arg1); if (ret < 0) { ERROR("%s: enter_cstate failed(%d)\n", __func__, ret); @@ -58,14 +58,14 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, break; - case MCE_CMD_UPDATE_CSTATE_INFO: + case (uint64_t)MCE_CMD_UPDATE_CSTATE_INFO: /* * get the parameters required for the update cstate info * command */ - arg3 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X4)); - arg4 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X5)); - arg5 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X6)); + arg3 = read_ctx_reg(gp_regs, CTX_GPREG_X4); + arg4 = read_ctx_reg(gp_regs, CTX_GPREG_X5); + arg5 = read_ctx_reg(gp_regs, CTX_GPREG_X6); /* arg0 cluster * arg1 ccplex @@ -77,13 +77,13 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, nvg_update_cstate_info((uint32_t)arg0, (uint32_t)arg1, (uint32_t)arg2, (uint32_t)arg4, (uint8_t)arg5); - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X4), (arg3)); - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X5), (arg4)); - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X6), (arg5)); + write_ctx_reg(gp_regs, CTX_GPREG_X4, arg3); + write_ctx_reg(gp_regs, CTX_GPREG_X5, arg4); + write_ctx_reg(gp_regs, CTX_GPREG_X6, arg5); break; - case MCE_CMD_UPDATE_CROSSOVER_TIME: + case (uint64_t)MCE_CMD_UPDATE_CROSSOVER_TIME: ret = nvg_update_crossover_time((uint32_t)arg0, (uint32_t)arg1); if (ret < 0) { ERROR("%s: update_crossover_time failed(%d)\n", @@ -92,21 +92,21 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, break; - case MCE_CMD_READ_CSTATE_STATS: + case (uint64_t)MCE_CMD_READ_CSTATE_STATS: ret64 = nvg_get_cstate_stat_query_value(); /* update context to return cstate stats value */ - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), (ret64)); - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X2), (ret64)); + write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64); + write_ctx_reg(gp_regs, CTX_GPREG_X2, ret64); break; - case MCE_CMD_WRITE_CSTATE_STATS: + case (uint64_t)MCE_CMD_WRITE_CSTATE_STATS: ret = nvg_set_cstate_stat_query_value(arg0); break; - case MCE_CMD_IS_SC7_ALLOWED: + case (uint64_t)MCE_CMD_IS_SC7_ALLOWED: ret = nvg_is_sc7_allowed(); if (ret < 0) { ERROR("%s: is_sc7_allowed failed(%d)\n", __func__, ret); @@ -114,12 +114,12 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, } /* update context to return SC7 status value */ - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), ((uint64_t)ret)); - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X3), ((uint64_t)ret)); + write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint64_t)ret); + write_ctx_reg(gp_regs, CTX_GPREG_X3, (uint64_t)ret); break; - case MCE_CMD_ONLINE_CORE: + case (uint64_t)MCE_CMD_ONLINE_CORE: ret = nvg_online_core((uint32_t)arg0); if (ret < 0) { ERROR("%s: online_core failed(%d)\n", __func__, ret); @@ -127,7 +127,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, break; - case MCE_CMD_CC3_CTRL: + case (uint64_t)MCE_CMD_CC3_CTRL: ret = nvg_cc3_ctrl((uint32_t)arg0, (uint8_t)arg2); if (ret < 0) { ERROR("%s: cc3_ctrl failed(%d)\n", __func__, ret); @@ -135,7 +135,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, break; - case MCE_CMD_READ_VERSIONS: + case (uint64_t)MCE_CMD_READ_VERSIONS: /* get the MCE firmware version */ ret64 = nvg_get_version(); @@ -143,12 +143,12 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, * version = minor(63:32) | major(31:0). Update context * to return major and minor version number. */ - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), (ret64 & (uint64_t)0xFFFF)); - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X2), (ret64 >> 32)); + write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64 & 0xFFFFULL)); + write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64 >> 32U)); break; - case MCE_CMD_ROC_FLUSH_CACHE_TRBITS: + case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE_TRBITS: ret = nvg_roc_clean_cache_trbits(); if (ret < 0) { ERROR("%s: flush cache_trbits failed(%d)\n", __func__, @@ -157,7 +157,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, break; - case MCE_CMD_ROC_FLUSH_CACHE: + case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE: ret = nvg_roc_flush_cache(); if (ret < 0) { ERROR("%s: flush cache failed(%d)\n", __func__, ret); @@ -165,7 +165,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, break; - case MCE_CMD_ROC_CLEAN_CACHE: + case (uint64_t)MCE_CMD_ROC_CLEAN_CACHE: ret = nvg_roc_clean_cache(); if (ret < 0) { ERROR("%s: clean cache failed(%d)\n", __func__, ret); diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c index 6451f02c5..d608bfa4d 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -25,7 +25,7 @@ */ uint64_t nvg_get_version(void) { - nvg_set_request(TEGRA_NVG_CHANNEL_VERSION); + nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_VERSION); return (uint64_t)nvg_get_result(); } @@ -37,7 +37,7 @@ uint64_t nvg_get_version(void) */ int32_t nvg_enable_power_perf_mode(void) { - nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_PERF, 1U); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 1U); return 0; } @@ -49,7 +49,7 @@ int32_t nvg_enable_power_perf_mode(void) */ int32_t nvg_disable_power_perf_mode(void) { - nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_PERF, 0U); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 0U); return 0; } @@ -61,7 +61,7 @@ int32_t nvg_disable_power_perf_mode(void) */ int32_t nvg_enable_power_saver_modes(void) { - nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_MODES, 1U); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 1U); return 0; } @@ -73,7 +73,7 @@ int32_t nvg_enable_power_saver_modes(void) */ int32_t nvg_disable_power_saver_modes(void) { - nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_MODES, 0U); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 0U); return 0; } @@ -87,7 +87,7 @@ int32_t nvg_disable_power_saver_modes(void) void nvg_set_wake_time(uint32_t wake_time) { /* time (TSC ticks) until the core is expected to get a wake event */ - nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time); } /* @@ -135,7 +135,7 @@ void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, val |= ((uint64_t)wake_mask & CSTATE_WAKE_MASK_CLEAR) << CSTATE_WAKE_MASK_SHIFT; /* set the updated cstate info */ - nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_INFO, val); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val); } /* @@ -151,18 +151,18 @@ int32_t nvg_update_crossover_time(uint32_t type, uint32_t time) int32_t ret = 0; switch (type) { - case TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND: - nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND, + case (uint32_t)TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND: + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND, (uint64_t)time); break; - case TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND: - nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND, + case (uint32_t)TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND: + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND, (uint64_t)time); break; - case TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND: - nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND, + case (uint32_t)TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND: + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND, (uint64_t)time); break; @@ -196,7 +196,7 @@ int32_t nvg_set_cstate_stat_query_value(uint64_t data) (uint32_t)(data & MCE_CORE_ID_MASK)); ret = EINVAL; } else { - nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST, data); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST, data); } return ret; @@ -209,7 +209,7 @@ int32_t nvg_set_cstate_stat_query_value(uint64_t data) */ uint64_t nvg_get_cstate_stat_query_value(void) { - nvg_set_request(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE); + nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE); return (uint64_t)nvg_get_result(); } @@ -222,7 +222,7 @@ uint64_t nvg_get_cstate_stat_query_value(void) int32_t nvg_is_sc7_allowed(void) { /* issue command to check if SC7 is allowed */ - nvg_set_request(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED); + nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED); /* 1 = SC7 allowed, 0 = SC7 not allowed */ return (int32_t)nvg_get_result(); @@ -244,8 +244,8 @@ int32_t nvg_online_core(uint32_t core) ret = EINVAL; } else { /* get a core online */ - nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE, - (uint64_t)core & MCE_CORE_ID_MASK); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE, + (uint64_t)core & MCE_CORE_ID_MASK); } return ret; @@ -275,7 +275,7 @@ int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable) if (enable != 0U) { val = ((uint64_t)freq & MCE_AUTO_CC3_FREQ_MASK) | MCE_AUTO_CC3_ENABLE_BIT; } - nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, val); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CC3_CTRL, val); return 0; } @@ -295,7 +295,7 @@ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx) ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx); ret = EINVAL; } else { - nvg_set_request_data(TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC, + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC, (uint64_t)gsc_idx); } -- GitLab