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Commit 63a0b127 authored by Konstantin Porotchkin's avatar Konstantin Porotchkin Committed by Marcin Wojtas
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plat: marvell: armada: platform definitions cleanup 



- Remove
    TRUSTED_DRAM_BASE
    TRUSTED_DRAM_SIZE
    MARVELL_TRUSTED_SRAM_BASE
- Rename
    PLAT_MARVELL_TRUSTED_DRAM_* -> PLAT_MARVELL_TRUSTED_RAM_*
    PLAT_MARVELL_TRUSTED_SRAM_* -> MARVELL_TRUSTED_DRAM_*
    MARVELL_MAP_SHARED_RAM -> MARVELL_MAP_SECURE_RAM
- Move
    MARVELL_TRUSTED_DRAM_SIZE to marvell_def.h
- Enable MARVELL_MAP_SECURE_RAM region in BL2U memory map
- Add dependency of MARVELL_MAP_SHARED_RAM on LLC_SRAM
- Add minor style improvents

Change-Id: Iebc03361e4f88489af1597f54e137b27c241814c
Signed-off-by: default avatarKonstantin Porotchkin <kostap@marvell.com>
[Improve patch after rebase]
Signed-off-by: default avatarMarcin Wojtas <mw@semihalf.com>
parent c96aa7fb
Show whitespace changes
Inline Side-by-side
include/plat/marvell/armada/a3k/common/board_marvell_def.h
View file @ 63a0b127
......@@ -71,6 +71,4 @@
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
#define PLAT_MARVELL_TRUSTED_SRAM_SIZE 0x80000 /* 512 KB */
#endif /* BOARD_MARVELL_DEF_H */
include/plat/marvell/armada/a3k/common/marvell_def.h
View file @ 63a0b127
......@@ -49,15 +49,17 @@
*/
#define MARVELL_LOCAL_STATE_OFF 2
/* This leaves a gap between end of DRAM and start of ROM block */
#define MARVELL_TRUSTED_DRAM_SIZE 0x80000 /* 512 KB */
/* The first 4KB of Trusted SRAM are used as shared memory */
#define MARVELL_TRUSTED_SRAM_BASE PLAT_MARVELL_ATF_BASE
#define MARVELL_SHARED_RAM_BASE MARVELL_TRUSTED_SRAM_BASE
#define MARVELL_SHARED_RAM_BASE PLAT_MARVELL_ATF_BASE
#define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
/* The remaining Trusted SRAM is used to load the BL images */
#define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \
MARVELL_SHARED_RAM_SIZE)
#define MARVELL_BL_RAM_SIZE (PLAT_MARVELL_TRUSTED_SRAM_SIZE - \
#define MARVELL_BL_RAM_SIZE (MARVELL_TRUSTED_DRAM_SIZE - \
MARVELL_SHARED_RAM_SIZE)
#define MARVELL_DRAM_BASE ULL(0x0)
......@@ -86,7 +88,6 @@
MARVELL_DRAM_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
/*
* The number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
......@@ -177,8 +178,8 @@
* BL32 specific defines.
*****************************************************************************
*/
#define BL32_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE
#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_DRAM_SIZE)
#define BL32_BASE PLAT_MARVELL_TRUSTED_RAM_BASE
#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_RAM_SIZE)
#ifdef SPD_none
#undef BL32_BASE
......
include/plat/marvell/armada/a8k/common/board_marvell_def.h
View file @ 63a0b127
......@@ -71,7 +71,4 @@
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
#define PLAT_MARVELL_TRUSTED_SRAM_SIZE 0x80000 /* 512 KB */
#endif /* BOARD_MARVELL_DEF_H */
include/plat/marvell/armada/a8k/common/marvell_def.h
View file @ 63a0b127
......@@ -47,15 +47,17 @@
*/
#define MARVELL_LOCAL_STATE_OFF 2
/* This leaves a gap between end of DRAM and start of ROM block */
#define MARVELL_TRUSTED_DRAM_SIZE 0x80000 /* 512 KB */
/* The first 4KB of Trusted SRAM are used as shared memory */
#define MARVELL_TRUSTED_SRAM_BASE PLAT_MARVELL_ATF_BASE
#define MARVELL_SHARED_RAM_BASE MARVELL_TRUSTED_SRAM_BASE
#define MARVELL_SHARED_RAM_BASE PLAT_MARVELL_ATF_BASE
#define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
/* The remaining Trusted SRAM is used to load the BL images */
#define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \
MARVELL_SHARED_RAM_SIZE)
#define MARVELL_BL_RAM_SIZE (PLAT_MARVELL_TRUSTED_SRAM_SIZE - \
#define MARVELL_BL_RAM_SIZE (MARVELL_TRUSTED_DRAM_SIZE - \
MARVELL_SHARED_RAM_SIZE)
/* Non-shared DRAM */
#define MARVELL_DRAM_BASE ULL(0x0)
......@@ -75,17 +77,25 @@
#define MARVELL_IRQ_SEC_SGI_6 14
#define MARVELL_IRQ_SEC_SGI_7 15
#define MARVELL_MAP_SHARED_RAM MAP_REGION_FLAT( \
MARVELL_SHARED_RAM_BASE,\
MARVELL_SHARED_RAM_SIZE,\
#if LLC_SRAM
/* The entire LLC SRAM should be marked as secure in MMU tables,
* otherwise any access to it will produce exception
*/
#define MARVELL_MAP_SECURE_RAM MAP_REGION_FLAT( \
PLAT_MARVELL_LLC_SRAM_BASE,\
PLAT_MARVELL_LLC_SRAM_SIZE,\
MT_MEMORY | MT_RW | MT_SECURE)
#else
#define MARVELL_MAP_SECURE_RAM MAP_REGION_FLAT( \
MARVELL_SHARED_RAM_BASE, \
MARVELL_SHARED_RAM_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
#endif
#define MARVELL_MAP_DRAM MAP_REGION_FLAT( \
MARVELL_DRAM_BASE, \
MARVELL_DRAM_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
/*
* The number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
......@@ -180,8 +190,8 @@
/*******************************************************************************
* BL32 specific defines.
******************************************************************************/
#define BL32_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE
#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_DRAM_SIZE)
#define BL32_BASE PLAT_MARVELL_TRUSTED_RAM_BASE
#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_RAM_SIZE)
#ifdef SPD_none
#undef BL32_BASE
......
plat/marvell/armada/a3k/common/include/platform_def.h
View file @ 63a0b127
......@@ -84,8 +84,8 @@
/* 64 MB TODO: reduce this to minimum needed according to fip image size*/
#define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x04000000
/* Reserve 16M for SCP (Secure PayLoad) Trusted DRAM */
#define PLAT_MARVELL_TRUSTED_DRAM_BASE 0x04400000
#define PLAT_MARVELL_TRUSTED_DRAM_SIZE 0x01000000 /* 16 MB */
#define PLAT_MARVELL_TRUSTED_RAM_BASE 0x04400000
#define PLAT_MARVELL_TRUSTED_RAM_SIZE 0x01000000 /* 16 MB */
/*
* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
......@@ -169,8 +169,7 @@
#define PLAT_MARVELL_NSTIMER_FRAME_ID 1
/* Mailbox base address */
#define PLAT_MARVELL_MAILBOX_BASE \
(MARVELL_TRUSTED_SRAM_BASE + 0x400)
#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_SHARED_RAM_BASE + 0x400)
#define PLAT_MARVELL_MAILBOX_SIZE 0x100
#define PLAT_MARVELL_MAILBOX_MAGIC_NUM 0x6D72766C /* mrvl */
......
plat/marvell/armada/a8k/common/aarch64/a8k_common.c
View file @ 63a0b127
......@@ -18,14 +18,14 @@
*/
#if IMAGE_BL1
const mmap_region_t plat_marvell_mmap[] = {
MARVELL_MAP_SHARED_RAM,
MARVELL_MAP_SECURE_RAM,
MAP_DEVICE0,
{0}
};
#endif
#if IMAGE_BL2
const mmap_region_t plat_marvell_mmap[] = {
MARVELL_MAP_SHARED_RAM,
MARVELL_MAP_SECURE_RAM,
MAP_DEVICE0,
MARVELL_MAP_DRAM,
{0}
......@@ -34,6 +34,7 @@ const mmap_region_t plat_marvell_mmap[] = {
#if IMAGE_BL2U
const mmap_region_t plat_marvell_mmap[] = {
MARVELL_MAP_SECURE_RAM,
MAP_DEVICE0,
{0}
};
......@@ -48,7 +49,7 @@ const mmap_region_t plat_marvell_mmap[] = {
#if IMAGE_BL31
const mmap_region_t plat_marvell_mmap[] = {
MARVELL_MAP_SHARED_RAM,
MARVELL_MAP_SECURE_RAM,
MAP_DEVICE0,
MARVELL_MAP_DRAM,
{0}
......@@ -56,6 +57,7 @@ const mmap_region_t plat_marvell_mmap[] = {
#endif
#if IMAGE_BL32
const mmap_region_t plat_marvell_mmap[] = {
MARVELL_MAP_SECURE_RAM,
MAP_DEVICE0,
{0}
};
......
plat/marvell/armada/a8k/common/include/platform_def.h
View file @ 63a0b127
......@@ -92,13 +92,16 @@
#define PLAT_MARVELL_CORE_COUNT (PLAT_MARVELL_CLUSTER_COUNT * \
PLAT_MARVELL_CLUSTER_CORE_COUNT)
/* DRAM[2MB..66MB] is used as Trusted ROM */
/* Part of DRAM that is used as Trusted ROM */
#define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR
/* 64 MB TODO: reduce this to minimum needed according to fip image size */
#define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x04000000
/* Reserve 16M for SCP (Secure PayLoad) Trusted DRAM */
#define PLAT_MARVELL_TRUSTED_DRAM_BASE 0x04400000
#define PLAT_MARVELL_TRUSTED_DRAM_SIZE 0x01000000 /* 16 MB */
/* Reserve 16M for SCP (Secure PayLoad) Trusted RAM */
#define PLAT_MARVELL_TRUSTED_RAM_BASE 0x04400000
#define PLAT_MARVELL_TRUSTED_RAM_SIZE 0x01000000 /* 16 MB DRAM */
#define PLAT_MARVELL_LLC_SRAM_BASE PLAT_MARVELL_TRUSTED_RAM_BASE
#define PLAT_MARVELL_LLC_SRAM_SIZE 0x00100000 /* 1 MB SRAM */
/*
* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
......@@ -182,7 +185,7 @@
/* Mailbox base address (note the lower memory space
* is reserved for BLE data)
*/
#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_TRUSTED_SRAM_BASE \
#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_SHARED_RAM_BASE \
+ 0x400)
#define PLAT_MARVELL_MAILBOX_SIZE 0x100
#define PLAT_MARVELL_MAILBOX_MAGIC_NUM 0x6D72766C /* mrvl */
......
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