Commit 64aa08fb authored by Varun Wadekar's avatar Varun Wadekar
Browse files

Tegra: bpmp: fix multiple MISRA issues



This patch fixes violations for the following MISRA rules

* Rule 5.7  "A tag name shall be a unique identifier"
* Rule 10.1 "Operands shall not be of an inappropriate essential type"
* Rule 10.3 "The value of an expression shall not be assigned to an object
             with a narrower essential type or of a different essential type
             category"
* Rule 10.4 "Both operands of an operator in which the usual arithmetic
             conversions are performed shall have the same essential type
             category"
* Rule 20.7 "Expressions resulting from the expansion of macro parameters
             shall be enclosed in parentheses"
* Rule 21.1 "#define and #undef shall not be used on a reserved identifier
             or reserved macro name"

Change-Id: I83cbe659c2d72e76dd4759959870b57c58adafdf
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
parent 8d4107f0
...@@ -316,7 +316,7 @@ int tegra_bpmp_ipc_enable_clock(uint32_t clk_id) ...@@ -316,7 +316,7 @@ int tegra_bpmp_ipc_enable_clock(uint32_t clk_id)
/* prepare the MRQ_CLK command */ /* prepare the MRQ_CLK command */
req.cmd_and_id = make_mrq_clk_cmd(CMD_CLK_ENABLE, clk_id); req.cmd_and_id = make_mrq_clk_cmd(CMD_CLK_ENABLE, clk_id);
ret = tegra_bpmp_ipc_send_req_atomic(MRQ_CLK, &req, sizeof(req), ret = tegra_bpmp_ipc_send_req_atomic(MRQ_CLK, &req, (uint32_t)sizeof(req),
NULL, 0); NULL, 0);
if (ret != 0) { if (ret != 0) {
ERROR("%s: failed for module %d with error %d\n", __func__, ERROR("%s: failed for module %d with error %d\n", __func__,
...@@ -339,7 +339,7 @@ int tegra_bpmp_ipc_disable_clock(uint32_t clk_id) ...@@ -339,7 +339,7 @@ int tegra_bpmp_ipc_disable_clock(uint32_t clk_id)
/* prepare the MRQ_CLK command */ /* prepare the MRQ_CLK command */
req.cmd_and_id = make_mrq_clk_cmd(CMD_CLK_DISABLE, clk_id); req.cmd_and_id = make_mrq_clk_cmd(CMD_CLK_DISABLE, clk_id);
ret = tegra_bpmp_ipc_send_req_atomic(MRQ_CLK, &req, sizeof(req), ret = tegra_bpmp_ipc_send_req_atomic(MRQ_CLK, &req, (uint32_t)sizeof(req),
NULL, 0); NULL, 0);
if (ret != 0) { if (ret != 0) {
ERROR("%s: failed for module %d with error %d\n", __func__, ERROR("%s: failed for module %d with error %d\n", __func__,
......
/* /*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#ifndef INTF_H #ifndef BPMP_INTF_H
#define INTF_H #define BPMP_INTF_H
/** /**
* Flags used in IPC req * Flags used in IPC req
...@@ -77,16 +77,16 @@ struct __attribute__((packed)) mrq_reset_request { ...@@ -77,16 +77,16 @@ struct __attribute__((packed)) mrq_reset_request {
* *
*/ */
enum { enum {
CMD_CLK_GET_RATE = 1, CMD_CLK_GET_RATE = U(1),
CMD_CLK_SET_RATE = 2, CMD_CLK_SET_RATE = U(2),
CMD_CLK_ROUND_RATE = 3, CMD_CLK_ROUND_RATE = U(3),
CMD_CLK_GET_PARENT = 4, CMD_CLK_GET_PARENT = U(4),
CMD_CLK_SET_PARENT = 5, CMD_CLK_SET_PARENT = U(5),
CMD_CLK_IS_ENABLED = 6, CMD_CLK_IS_ENABLED = U(6),
CMD_CLK_ENABLE = 7, CMD_CLK_ENABLE = U(7),
CMD_CLK_DISABLE = 8, CMD_CLK_DISABLE = U(8),
CMD_CLK_GET_ALL_INFO = 14, CMD_CLK_GET_ALL_INFO = U(14),
CMD_CLK_GET_MAX_CLK_ID = 15, CMD_CLK_GET_MAX_CLK_ID = U(15),
CMD_CLK_MAX, CMD_CLK_MAX,
}; };
...@@ -124,4 +124,4 @@ struct mrq_clk_request { ...@@ -124,4 +124,4 @@ struct mrq_clk_request {
*/ */
#define make_mrq_clk_cmd(cmd, id) (((cmd) << 24) | (id & 0xFFFFFF)) #define make_mrq_clk_cmd(cmd, id) (((cmd) << 24) | (id & 0xFFFFFF))
#endif /* INTF_H */ #endif /* BPMP_INTF_H */
/* /*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2017-2020, NVIDIA Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#ifndef IVC_H #ifndef BPMP_IVC_H
#define IVC_H #define BPMP_IVC_H
#include <lib/utils_def.h> #include <lib/utils_def.h>
#include <stdint.h> #include <stdint.h>
...@@ -15,22 +15,21 @@ ...@@ -15,22 +15,21 @@
#define IVC_CHHDR_TX_FIELDS U(16) #define IVC_CHHDR_TX_FIELDS U(16)
#define IVC_CHHDR_RX_FIELDS U(16) #define IVC_CHHDR_RX_FIELDS U(16)
struct ivc;
struct ivc_channel_header; struct ivc_channel_header;
/* callback handler for notify on receiving a response */
typedef void (* ivc_notify_function)(const struct ivc *);
struct ivc { struct ivc {
struct ivc_channel_header *rx_channel; struct ivc_channel_header *rx_channel;
struct ivc_channel_header *tx_channel; struct ivc_channel_header *tx_channel;
uint32_t w_pos; uint32_t w_pos;
uint32_t r_pos; uint32_t r_pos;
ivc_notify_function notify; void (*notify)(const struct ivc *);
uint32_t nframes; uint32_t nframes;
uint32_t frame_size; uint32_t frame_size;
}; };
/* callback handler for notify on receiving a response */
typedef void (* ivc_notify_function)(const struct ivc *);
int32_t tegra_ivc_init(struct ivc *ivc, uintptr_t rx_base, uintptr_t tx_base, int32_t tegra_ivc_init(struct ivc *ivc, uintptr_t rx_base, uintptr_t tx_base,
uint32_t nframes, uint32_t frame_size, uint32_t nframes, uint32_t frame_size,
ivc_notify_function notify); ivc_notify_function notify);
...@@ -48,4 +47,4 @@ bool tegra_ivc_tx_empty(const struct ivc *ivc); ...@@ -48,4 +47,4 @@ bool tegra_ivc_tx_empty(const struct ivc *ivc);
bool tegra_ivc_can_write(const struct ivc *ivc); bool tegra_ivc_can_write(const struct ivc *ivc);
bool tegra_ivc_can_read(const struct ivc *ivc); bool tegra_ivc_can_read(const struct ivc *ivc);
#endif /* IVC_H */ #endif /* BPMP_IVC_H */
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