Merge pull request #1528 from antonio-nino-diaz-arm/an/libc

libc: Cleanup library

lib/xlat_tables_v2/xlat_tables_core.c

@@ -10,8 +10,8 @@
 #include <errno.h>
 #include <platform_def.h>
 #include <stdbool.h>
+#include <stdint.h>
 #include <string.h>
-#include <types.h>
 #include <utils_def.h>
 #include <xlat_tables_defs.h>
 #include <xlat_tables_v2.h>

lib/xlat_tables_v2/xlat_tables_utils.c

@@ -10,7 +10,8 @@
 #include <errno.h>
 #include <platform_def.h>
 #include <stdbool.h>
-#include <types.h>
+#include <stdint.h>
+#include <stdio.h>
 #include <utils_def.h>
 #include <xlat_tables_defs.h>
 #include <xlat_tables_v2.h>
@@ -33,16 +34,16 @@ void xlat_tables_print(__unused xlat_ctx_t *ctx)
 
 void xlat_mmap_print(const mmap_region_t *mmap)
 {
-	tf_printf("mmap:\n");
+	printf("mmap:\n");
 	const mmap_region_t *mm = mmap;
 
 	while (mm->size != 0U) {
-		tf_printf(" VA:0x%lx  PA:0x%llx  size:0x%zx  attr:0x%x "
-			  "granularity:0x%zx\n", mm->base_va, mm->base_pa,
-			  mm->size, mm->attr, mm->granularity);
+		printf(" VA:0x%lx  PA:0x%llx  size:0x%zx  attr:0x%x  granularity:0x%zx\n",
+		       mm->base_va, mm->base_pa, mm->size, mm->attr,
+		       mm->granularity);
 		++mm;
 	};
-	tf_printf("\n");
+	printf("\n");
 }
 
 /* Print the attributes of the specified block descriptor. */
@@ -52,18 +53,18 @@ static void xlat_desc_print(const xlat_ctx_t *ctx, uint64_t desc)
 	int xlat_regime = ctx->xlat_regime;
 
 	if (mem_type_index == ATTR_IWBWA_OWBWA_NTR_INDEX) {
-		tf_printf("MEM");
+		printf("MEM");
 	} else if (mem_type_index == ATTR_NON_CACHEABLE_INDEX) {
-		tf_printf("NC");
+		printf("NC");
 	} else {
 		assert(mem_type_index == ATTR_DEVICE_INDEX);
-		tf_printf("DEV");
+		printf("DEV");
 	}
 
 	if ((xlat_regime == EL3_REGIME) || (xlat_regime == EL2_REGIME)) {
 		/* For EL3 and EL2 only check the AP[2] and XN bits. */
-		tf_printf(((desc & LOWER_ATTRS(AP_RO)) != 0ULL) ? "-RO" : "-RW");
-		tf_printf(((desc & UPPER_ATTRS(XN)) != 0ULL) ? "-XN" : "-EXEC");
+		printf(((desc & LOWER_ATTRS(AP_RO)) != 0ULL) ? "-RO" : "-RW");
+		printf(((desc & UPPER_ATTRS(XN)) != 0ULL) ? "-XN" : "-EXEC");
 	} else {
 		assert(xlat_regime == EL1_EL0_REGIME);
 		/*
@@ -81,18 +82,18 @@ static void xlat_desc_print(const xlat_ctx_t *ctx, uint64_t desc)
 
 		assert((xn_perm == xn_mask) || (xn_perm == 0ULL));
 #endif
-		tf_printf(((desc & LOWER_ATTRS(AP_RO)) != 0ULL) ? "-RO" : "-RW");
+		printf(((desc & LOWER_ATTRS(AP_RO)) != 0ULL) ? "-RO" : "-RW");
 		/* Only check one of PXN and UXN, the other one is the same. */
-		tf_printf(((desc & UPPER_ATTRS(PXN)) != 0ULL) ? "-XN" : "-EXEC");
+		printf(((desc & UPPER_ATTRS(PXN)) != 0ULL) ? "-XN" : "-EXEC");
 		/*
 		 * Privileged regions can only be accessed from EL1, user
 		 * regions can be accessed from EL1 and EL0.
 		 */
-		tf_printf(((desc & LOWER_ATTRS(AP_ACCESS_UNPRIVILEGED)) != 0ULL)
+		printf(((desc & LOWER_ATTRS(AP_ACCESS_UNPRIVILEGED)) != 0ULL)
 			  ? "-USER" : "-PRIV");
 	}
 
-	tf_printf(((LOWER_ATTRS(NS) & desc) != 0ULL) ? "-NS" : "-S");
+	printf(((LOWER_ATTRS(NS) & desc) != 0ULL) ? "-NS" : "-S");
 }
 
 static const char * const level_spacers[] = {
@@ -135,18 +136,18 @@ static void xlat_tables_print_internal(xlat_ctx_t *ctx, uintptr_t table_base_va,
 		if ((desc & DESC_MASK) == INVALID_DESC) {
 
 			if (invalid_row_count == 0) {
-				tf_printf("%sVA:0x%lx size:0x%zx\n",
-					  level_spacers[level],
-					  table_idx_va, level_size);
+				printf("%sVA:0x%lx size:0x%zx\n",
+				       level_spacers[level],
+				       table_idx_va, level_size);
 			}
 			invalid_row_count++;
 
 		} else {
 
 			if (invalid_row_count > 1) {
-				tf_printf(invalid_descriptors_ommited,
-					  level_spacers[level],
-					  invalid_row_count - 1);
+				printf(invalid_descriptors_ommited,
+				       level_spacers[level],
+				       invalid_row_count - 1);
 			}
 			invalid_row_count = 0;
 
@@ -163,9 +164,9 @@ static void xlat_tables_print_internal(xlat_ctx_t *ctx, uintptr_t table_base_va,
 				 * but instead points to the next translation
 				 * table in the translation table walk.
 				 */
-				tf_printf("%sVA:0x%lx size:0x%zx\n",
-					  level_spacers[level],
-					  table_idx_va, level_size);
+				printf("%sVA:0x%lx size:0x%zx\n",
+				       level_spacers[level],
+				       table_idx_va, level_size);
 
 				uintptr_t addr_inner = desc & TABLE_ADDR_MASK;
 
@@ -173,13 +174,12 @@ static void xlat_tables_print_internal(xlat_ctx_t *ctx, uintptr_t table_base_va,
 					(uint64_t *)addr_inner,
 					XLAT_TABLE_ENTRIES, level + 1U);
 			} else {
-				tf_printf("%sVA:0x%lx PA:0x%llx size:0x%zx ",
-					  level_spacers[level],
-					  table_idx_va,
-					  (uint64_t)(desc & TABLE_ADDR_MASK),
-					  level_size);
+				printf("%sVA:0x%lx PA:0x%llx size:0x%zx ",
+				       level_spacers[level], table_idx_va,
+				       (uint64_t)(desc & TABLE_ADDR_MASK),
+				       level_size);
 				xlat_desc_print(ctx, desc);
-				tf_printf("\n");
+				printf("\n");
 			}
 		}
 
@@ -188,8 +188,8 @@ static void xlat_tables_print_internal(xlat_ctx_t *ctx, uintptr_t table_base_va,
 	}
 
 	if (invalid_row_count > 1) {
-		tf_printf(invalid_descriptors_ommited,
-			  level_spacers[level], invalid_row_count - 1);
+		printf(invalid_descriptors_ommited,
+		       level_spacers[level], invalid_row_count - 1);
 	}
 }
 
@@ -364,7 +364,7 @@ static int xlat_get_mem_attributes_internal(const xlat_ctx_t *ctx,
 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
 	VERBOSE("Attributes: ");
 	xlat_desc_print(ctx, desc);
-	tf_printf("\n");
+	printf("\n");
 #endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */
 
 	assert(attributes != NULL);

plat/arm/css/drivers/scp/css_scp.h

 /*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,7 +9,7 @@
 
 #include <cassert.h>
 #include <platform_def.h>
-#include <types.h>
+#include <stdint.h>
 
 /* Forward declarations */
 struct psci_power_state;

plat/hisilicon/hikey/hikey_security.c

@@ -8,7 +8,7 @@
 #include <debug.h>
 #include <platform_def.h>
 #include <stdint.h>
-#include <strings.h>
+#include <string.h>
 #include <utils_def.h>
 #include "hikey_private.h"
 

plat/hisilicon/hikey/hisi_ipc.c

@@ -11,6 +11,7 @@
 #include <mmio.h>
 #include <platform_def.h>
 #include <stdarg.h>
+#include <stdio.h>
 #include <string.h>
 
 static int ipc_init;
@@ -63,7 +64,7 @@ int hisi_cpus_powered_off_besides_curr(unsigned int cpu)
 static void hisi_ipc_send(unsigned int ipc_num)
 {
 	if (!ipc_init) {
-		tf_printf("error ipc base is null!!!\n");
+		printf("error ipc base is null!!!\n");
 		return;
 	}
 

plat/imx/common/include/imx8_lpuart.h

@@ -52,7 +52,7 @@
 
 #ifndef __ASSEMBLY__
 
-#include <types.h>
+#include <stdint.h>
 
 typedef struct {
 	console_t console;

plat/imx/common/include/sci/sci_scfw.h

@@ -9,7 +9,7 @@
 
 /* Includes */
 
-#include <types.h>
+#include <stdint.h>
 
 #ifdef __cplusplus
   #define   __I     volatile             /*!< Defines 'read only' permissions                 */

plat/imx/common/sci/imx8_mu.h

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <types.h>
+#include <stdint.h>
 
 #define MU_ATR0_OFFSET1		0x0
 #define MU_ARR0_OFFSET1		0x10

plat/imx/imx8qm/imx8qm_psci.c

@@ -35,7 +35,7 @@ int imx_pwr_domain_on(u_register_t mpidr)
 	cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
 	cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
 
-	tf_printf("imx_pwr_domain_on cluster_id %d, cpu_id %d\n", cluster_id, cpu_id);
+	printf("imx_pwr_domain_on cluster_id %d, cpu_id %d\n", cluster_id, cpu_id);
 
 	if (cluster_id == 0) {
 		sc_pm_set_resource_power_mode(ipc_handle, SC_R_A53,
@@ -94,7 +94,7 @@ void imx_pwr_domain_off(const psci_power_state_t *target_state)
 		SC_PM_WAKE_SRC_NONE);
 	if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
 		cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
-	tf_printf("turn off cluster:%d core:%d\n", cluster_id, cpu_id);
+	printf("turn off cluster:%d core:%d\n", cluster_id, cpu_id);
 }
 
 void imx_domain_suspend(const psci_power_state_t *target_state)

plat/imx/imx8qx/imx8qx_psci.c

@@ -25,7 +25,7 @@ int imx_pwr_domain_on(u_register_t mpidr)
 
 	cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
 
-	tf_printf("imx_pwr_domain_on cpu_id %d\n", cpu_id);
+	printf("imx_pwr_domain_on cpu_id %d\n", cpu_id);
 
 	if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id],
 	    SC_PM_PW_MODE_ON) != SC_ERR_NONE) {
@@ -61,7 +61,7 @@ void imx_pwr_domain_off(const psci_power_state_t *target_state)
 	plat_gic_cpuif_disable();
 	sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id],
 		SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_NONE);
-	tf_printf("turn off core:%d\n", cpu_id);
+	printf("turn off core:%d\n", cpu_id);
 }
 
 void imx_domain_suspend(const psci_power_state_t *target_state)

plat/layerscape/board/ls1043/ls1043_psci.c

@@ -5,15 +5,15 @@
  */
 
 #include <arch_helpers.h>
+#include <assert.h>
 #include <debug.h>
+#include <delay_timer.h>
+#include <endian.h>
 #include <errno.h>
-#include <assert.h>
+#include <gicv2.h>
+#include <mmio.h>
 #include <platform.h>
 #include <psci.h>
-#include <mmio.h>
-#include <sys/endian.h>
-#include <gicv2.h>
-#include <delay_timer.h>
 #include "platform_def.h"
 
 #define LS_SCFG_BASE			0x01570000

plat/layerscape/common/include/ls_16550.h

@@ -65,7 +65,7 @@
 
 #ifndef __ASSEMBLY__
 
-#include <types.h>
+#include <stdint.h>
 
 typedef struct {
 	console_t console;

plat/layerscape/common/include/plat_ls.h

@@ -7,8 +7,8 @@
 #ifndef __PLAT_LS_H__
 #define __PLAT_LS_H__
 
-#include <sys/types.h>
 #include <cpu_data.h>
+#include <stdint.h>
 
 /* BL1 utility functions */
 void ls_bl1_platform_setup(void);

plat/nvidia/tegra/common/drivers/smmu/smmu.c

 /*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,6 +12,8 @@
 #include <string.h>
 #include <tegra_private.h>
 
+extern void memcpy16(void *dest, const void *src, unsigned int length);
+
 /* SMMU IDs currently supported by the driver */
 enum {
 	TEGRA_SMMU0,

plat/nvidia/tegra/common/tegra_bl31_setup.c

@@ -28,6 +28,7 @@
 /* length of Trusty's input parameters (in bytes) */
 #define TRUSTY_PARAMS_LEN_BYTES	(4096*2)
 
+extern void memcpy16(void *dest, const void *src, unsigned int length);
 extern void zeromem16(void *mem, unsigned int length);
 
 /*******************************************************************************

plat/nvidia/tegra/include/drivers/memctrl_v2.h

 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,7 +11,7 @@
 
 #ifndef __ASSEMBLY__
 
-#include <sys/types.h>
+#include <stdint.h>
 
 /*******************************************************************************
  * StreamID to indicate no SMMU translations (requests to be steered on the

plat/nvidia/tegra/include/tegra_platform.h

 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,7 +7,7 @@
 #ifndef __TEGRA_PLATFORM_H__
 #define __TEGRA_PLATFORM_H__
 
-#include <sys/cdefs.h>
+#include <cdefs.h>
 
 /*
  * Tegra chip major/minor version

plat/nvidia/tegra/soc/t186/drivers/mce/ari.c

 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,10 +10,10 @@
 #include <debug.h>
 #include <delay_timer.h>
 #include <denver.h>
+#include <errno.h>
 #include <mce_private.h>
 #include <mmio.h>
 #include <platform.h>
-#include <sys/errno.h>
 #include <t18x_ari.h>
 
 /*******************************************************************************

plat/nvidia/tegra/soc/t186/drivers/mce/mce.c

 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,11 +12,11 @@
 #include <context_mgmt.h>
 #include <debug.h>
 #include <denver.h>
+#include <errno.h>
 #include <mce.h>
 #include <mce_private.h>
 #include <mmio.h>
 #include <string.h>
-#include <sys/errno.h>
 #include <t18x_ari.h>
 #include <tegra_def.h>
 #include <tegra_platform.h>

plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c

 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,9 +8,9 @@
 #include <arch_helpers.h>
 #include <debug.h>
 #include <denver.h>
+#include <errno.h>
 #include <mce_private.h>
 #include <mmio.h>
-#include <sys/errno.h>
 #include <t18x_ari.h>
 
 int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time)