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Commit 6de8b24f authored by davidcunado-arm's avatar davidcunado-arm Committed by GitHub
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Merge pull request #953 from vwadekar/tegra-misra-fixes-v1 

Tegra misra fixes v1
parents 0dc3c353 ab712fd8
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plat/nvidia/tegra/common/tegra_gic.c
View file @ 6de8b24f
......@@ -24,7 +24,7 @@
(GIC_HIGHEST_NS_PRIORITY << 24))
static const irq_sec_cfg_t *g_irq_sec_ptr;
static unsigned int g_num_irqs;
static uint32_t g_num_irqs;
/*******************************************************************************
* Place the cpu interface in a state where it can never make a cpu exit wfi as
......@@ -32,7 +32,7 @@ static unsigned int g_num_irqs;
******************************************************************************/
void tegra_gic_cpuif_deactivate(void)
{
unsigned int val;
uint32_t val;
/* Disable secure, non-secure interrupts and disable their bypass */
val = gicc_read_ctlr(TEGRA_GICC_BASE);
......@@ -46,9 +46,9 @@ void tegra_gic_cpuif_deactivate(void)
* Enable secure interrupts and set the priority mask register to allow all
* interrupts to trickle in.
******************************************************************************/
static void tegra_gic_cpuif_setup(unsigned int gicc_base)
static void tegra_gic_cpuif_setup(uint32_t gicc_base)
{
unsigned int val;
uint32_t val;
val = ENABLE_GRP0 | ENABLE_GRP1 | FIQ_EN | FIQ_BYP_DIS_GRP0;
val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
......@@ -61,14 +61,14 @@ static void tegra_gic_cpuif_setup(unsigned int gicc_base)
* Per cpu gic distributor setup which will be done by all cpus after a cold
* boot/hotplug. This marks out the secure interrupts & enables them.
******************************************************************************/
static void tegra_gic_pcpu_distif_setup(unsigned int gicd_base)
static void tegra_gic_pcpu_distif_setup(uint32_t gicd_base)
{
unsigned int index, sec_ppi_sgi_mask = 0;
uint32_t index, sec_ppi_sgi_mask = 0;
assert(gicd_base);
assert(gicd_base != 0U);
/* Setup PPI priorities doing four at a time */
for (index = 0; index < 32; index += 4) {
for (index = 0U; index < 32U; index += 4U) {
gicd_write_ipriorityr(gicd_base, index,
GICD_IPRIORITYR_DEF_VAL);
}
......@@ -87,9 +87,9 @@ static void tegra_gic_pcpu_distif_setup(unsigned int gicd_base)
* cold boot. It marks out the non secure SPIs, PPIs & SGIs and enables them.
* It then enables the secure GIC distributor interface.
******************************************************************************/
static void tegra_gic_distif_setup(unsigned int gicd_base)
static void tegra_gic_distif_setup(uint32_t gicd_base)
{
unsigned int index, num_ints, irq_num;
uint32_t index, num_ints, irq_num;
uint8_t target_cpus;
uint32_t val;
......@@ -99,22 +99,23 @@ static void tegra_gic_distif_setup(unsigned int gicd_base)
* number of IT_LINES
*/
num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK;
num_ints = (num_ints + 1) << 5;
for (index = MIN_SPI_ID; index < num_ints; index += 32)
gicd_write_igroupr(gicd_base, index, ~0);
num_ints = (num_ints + 1U) << 5;
for (index = MIN_SPI_ID; index < num_ints; index += 32U) {
gicd_write_igroupr(gicd_base, index, 0xFFFFFFFFU);
}
/* Setup SPI priorities doing four at a time */
for (index = MIN_SPI_ID; index < num_ints; index += 4) {
for (index = MIN_SPI_ID; index < num_ints; index += 4U) {
gicd_write_ipriorityr(gicd_base, index,
GICD_IPRIORITYR_DEF_VAL);
}
/* Configure SPI secure interrupts now */
if (g_irq_sec_ptr) {
if (g_irq_sec_ptr != NULL) {
for (index = 0; index < g_num_irqs; index++) {
irq_num = (g_irq_sec_ptr + index)->irq;
target_cpus = (g_irq_sec_ptr + index)->target_cpus;
for (index = 0U; index < g_num_irqs; index++) {
irq_num = g_irq_sec_ptr[index].irq;
target_cpus = (uint8_t)g_irq_sec_ptr[index].target_cpus;
if (irq_num >= MIN_SPI_ID) {
......@@ -122,14 +123,15 @@ static void tegra_gic_distif_setup(unsigned int gicd_base)
gicd_clr_igroupr(gicd_base, irq_num);
/* Configure SPI priority */
mmio_write_8(gicd_base + GICD_IPRIORITYR +
irq_num,
mmio_write_8((uint64_t)gicd_base +
(uint64_t)GICD_IPRIORITYR +
(uint64_t)irq_num,
GIC_HIGHEST_SEC_PRIORITY &
GIC_PRI_MASK);
/* Configure as level triggered */
val = gicd_read_icfgr(gicd_base, irq_num);
val |= (3 << ((irq_num & 0xF) << 1));
val |= (3U << ((irq_num & 0xFU) << 1U));
gicd_write_icfgr(gicd_base, irq_num, val);
/* Route SPI to the target CPUs */
......@@ -153,7 +155,7 @@ static void tegra_gic_distif_setup(unsigned int gicd_base)
gicd_write_ctlr(gicd_base, ENABLE_GRP0 | ENABLE_GRP1);
}
void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, unsigned int num_irqs)
void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, uint32_t num_irqs)
{
g_irq_sec_ptr = irq_sec_ptr;
g_num_irqs = num_irqs;
......@@ -172,12 +174,12 @@ void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, unsigned int num_irqs)
* SCR_EL3 to control its routing to EL3. The interrupt line is represented as
* the bit position of the IRQ or FIQ bit in the SCR_EL3.
******************************************************************************/
uint32_t tegra_gic_interrupt_type_to_line(uint32_t type,
static uint32_t tegra_gic_interrupt_type_to_line(uint32_t type,
uint32_t security_state)
{
assert(type == INTR_TYPE_S_EL1 ||
type == INTR_TYPE_EL3 ||
type == INTR_TYPE_NS);
assert((type == INTR_TYPE_S_EL1) ||
(type == INTR_TYPE_EL3) ||
(type == INTR_TYPE_NS));
assert(sec_state_is_valid(security_state));
......@@ -199,25 +201,29 @@ uint32_t tegra_gic_interrupt_type_to_line(uint32_t type,
* the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
* interrupt pending.
******************************************************************************/
uint32_t tegra_gic_get_pending_interrupt_type(void)
static uint32_t tegra_gic_get_pending_interrupt_type(void)
{
uint32_t id;
unsigned int index;
uint32_t index;
uint32_t ret = INTR_TYPE_NS;
id = gicc_read_hppir(TEGRA_GICC_BASE) & INT_ID_MASK;
/* get the interrupt type */
if (id < 1022) {
for (index = 0; index < g_num_irqs; index++) {
if (id == (g_irq_sec_ptr + index)->irq)
return (g_irq_sec_ptr + index)->type;
if (id < 1022U) {
for (index = 0U; index < g_num_irqs; index++) {
if (id == g_irq_sec_ptr[index].irq) {
ret = g_irq_sec_ptr[index].type;
break;
}
}
} else {
if (id == GIC_SPURIOUS_INTERRUPT) {
ret = INTR_TYPE_INVAL;
}
}
if (id == GIC_SPURIOUS_INTERRUPT)
return INTR_TYPE_INVAL;
return INTR_TYPE_NS;
return ret;
}
/*******************************************************************************
......@@ -225,30 +231,32 @@ uint32_t tegra_gic_get_pending_interrupt_type(void)
* the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
* interrupt pending.
******************************************************************************/
uint32_t tegra_gic_get_pending_interrupt_id(void)
static uint32_t tegra_gic_get_pending_interrupt_id(void)
{
uint32_t id;
uint32_t id, ret;
id = gicc_read_hppir(TEGRA_GICC_BASE) & INT_ID_MASK;
if (id < 1022)
return id;
if (id == 1023)
return INTR_ID_UNAVAILABLE;
if (id < 1022UL) {
ret = id;
} else if (id == 1023UL) {
ret = 0xFFFFFFFFUL; /* INTR_ID_UNAVAILABLE */
} else {
/*
* Find out which non-secure interrupt it is under the assumption that
* the GICC_CTLR.AckCtl bit is 0.
*/
ret = gicc_read_ahppir(TEGRA_GICC_BASE) & INT_ID_MASK;
}
/*
* Find out which non-secure interrupt it is under the assumption that
* the GICC_CTLR.AckCtl bit is 0.
*/
return gicc_read_ahppir(TEGRA_GICC_BASE) & INT_ID_MASK;
return ret;
}
/*******************************************************************************
* This functions reads the GIC cpu interface Interrupt Acknowledge register
* to start handling the pending interrupt. It returns the contents of the IAR.
******************************************************************************/
uint32_t tegra_gic_acknowledge_interrupt(void)
static uint32_t tegra_gic_acknowledge_interrupt(void)
{
return gicc_read_IAR(TEGRA_GICC_BASE);
}
......@@ -257,7 +265,7 @@ uint32_t tegra_gic_acknowledge_interrupt(void)
* This functions writes the GIC cpu interface End Of Interrupt register with
* the passed value to finish handling the active interrupt
******************************************************************************/
void tegra_gic_end_of_interrupt(uint32_t id)
static void tegra_gic_end_of_interrupt(uint32_t id)
{
gicc_write_EOIR(TEGRA_GICC_BASE, id);
}
......@@ -267,22 +275,25 @@ void tegra_gic_end_of_interrupt(uint32_t id)
* this interrupt has been configured under by the interrupt controller i.e.
* group0 or group1.
******************************************************************************/
uint32_t tegra_gic_get_interrupt_type(uint32_t id)
static uint32_t tegra_gic_get_interrupt_type(uint32_t id)
{
uint32_t group;
unsigned int index;
uint32_t index;
uint32_t ret = INTR_TYPE_NS;
group = gicd_get_igroupr(TEGRA_GICD_BASE, id);
/* get the interrupt type */
if (group == GRP0) {
for (index = 0; index < g_num_irqs; index++) {
if (id == (g_irq_sec_ptr + index)->irq)
return (g_irq_sec_ptr + index)->type;
for (index = 0U; index < g_num_irqs; index++) {
if (id == g_irq_sec_ptr[index].irq) {
ret = g_irq_sec_ptr[index].type;
break;
}
}
}
return INTR_TYPE_NS;
return ret;
}
#else
......
plat/nvidia/tegra/common/tegra_pm.c
View file @ 6de8b24f
......@@ -107,7 +107,7 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state)
{
/* all affinities use system suspend state id */
for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN;
}
......
plat/nvidia/tegra/common/tegra_sip_calls.c
View file @ 6de8b24f
......@@ -11,6 +11,7 @@
#include <debug.h>
#include <errno.h>
#include <memctrl.h>
#include <mmio.h>
#include <runtime_svc.h>
#include <tegra_private.h>
#include <tegra_platform.h>
......@@ -57,6 +58,7 @@ uint64_t tegra_sip_handler(uint32_t smc_fid,
void *handle,
uint64_t flags)
{
uint32_t regval;
int err;
/* Check if this is a SoC specific SiP */
......@@ -87,6 +89,18 @@ uint64_t tegra_sip_handler(uint32_t smc_fid,
SMC_RET1(handle, -ENOTSUP);
}
/*
* The GPU is the user of the Video Memory region. In order to
* transition to the new memory region smoothly, we program the
* new base/size ONLY if the GPU is in reset mode.
*/
regval = mmio_read_32(TEGRA_CAR_RESET_BASE +
TEGRA_GPU_RESET_REG_OFFSET);
if ((regval & GPU_RESET_BIT) == 0U) {
ERROR("GPU not in reset! Video Memory setup failed\n");
SMC_RET1(handle, -ENOTSUP);
}
/* new video memory carveout settings */
tegra_memctrl_videomem_setup(x1, x2);
......
plat/nvidia/tegra/include/drivers/mce.h
View file @ 6de8b24f
......@@ -63,14 +63,14 @@ typedef struct mce_cstate_info {
} mce_cstate_info_t;
/* public interfaces */
int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
int mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
uint64_t arg2);
int mce_update_reset_vector(void);
int mce_update_gsc_videomem(void);
int mce_update_gsc_tzdram(void);
int mce_update_gsc_tzram(void);
__dead2 void mce_enter_ccplex_state(uint32_t state_idx);
void mce_update_cstate_info(mce_cstate_info_t *cstate);
void mce_update_cstate_info(const mce_cstate_info_t *cstate);
void mce_verify_firmware_version(void);
#endif /* __MCE_H__ */
plat/nvidia/tegra/include/drivers/pmc.h
View file @ 6de8b24f
......@@ -9,20 +9,21 @@
#include <mmio.h>
#include <tegra_def.h>
#include <utils_def.h>
#define PMC_CONFIG 0x0U
#define PMC_PWRGATE_STATUS 0x38U
#define PMC_PWRGATE_TOGGLE 0x30U
#define PMC_TOGGLE_START 0x100U
#define PMC_SCRATCH39 0x138U
#define PMC_SECURE_DISABLE2 0x2c4U
#define PMC_SECURE_DISABLE2_WRITE22_ON (1U << 28)
#define PMC_SECURE_SCRATCH22 0x338U
#define PMC_SECURE_DISABLE3 0x2d8U
#define PMC_SECURE_DISABLE3_WRITE34_ON (1U << 20)
#define PMC_SECURE_DISABLE3_WRITE35_ON (1U << 22)
#define PMC_SECURE_SCRATCH34 0x368U
#define PMC_SECURE_SCRATCH35 0x36cU
#define PMC_CONFIG U(0x0)
#define PMC_PWRGATE_STATUS U(0x38)
#define PMC_PWRGATE_TOGGLE U(0x30)
#define PMC_TOGGLE_START U(0x100)
#define PMC_SCRATCH39 U(0x138)
#define PMC_SECURE_DISABLE2 U(0x2c4)
#define PMC_SECURE_DISABLE2_WRITE22_ON (U(1) << 28)
#define PMC_SECURE_SCRATCH22 U(0x338)
#define PMC_SECURE_DISABLE3 U(0x2d8)
#define PMC_SECURE_DISABLE3_WRITE34_ON (U(1) << 20)
#define PMC_SECURE_DISABLE3_WRITE35_ON (U(1) << 22)
#define PMC_SECURE_SCRATCH34 U(0x368)
#define PMC_SECURE_SCRATCH35 U(0x36c)
static inline uint32_t tegra_pmc_read_32(uint32_t off)
{
......@@ -36,7 +37,7 @@ static inline void tegra_pmc_write_32(uint32_t off, uint32_t val)
void tegra_pmc_cpu_setup(uint64_t reset_addr);
void tegra_pmc_lock_cpu_vectors(void);
void tegra_pmc_cpu_on(int cpu);
void tegra_pmc_cpu_on(int32_t cpu);
__dead2 void tegra_pmc_system_reset(void);
#endif /* __PMC_H__ */
plat/nvidia/tegra/include/platform_def.h
View file @ 6de8b24f
......@@ -10,6 +10,7 @@
#include <arch.h>
#include <common_def.h>
#include <tegra_def.h>
#include <utils_def.h>
/*******************************************************************************
* Generic platform constants
......@@ -17,10 +18,10 @@
/* Size of cacheable stacks */
#ifdef IMAGE_BL31
#define PLATFORM_STACK_SIZE 0x400
#define PLATFORM_STACK_SIZE U(0x400)
#endif
#define TEGRA_PRIMARY_CPU 0x0
#define TEGRA_PRIMARY_CPU U(0x0)
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
......@@ -31,20 +32,20 @@
/*******************************************************************************
* Platform console related constants
******************************************************************************/
#define TEGRA_CONSOLE_BAUDRATE 115200
#define TEGRA_BOOT_UART_CLK_IN_HZ 408000000
#define TEGRA_CONSOLE_BAUDRATE U(115200)
#define TEGRA_BOOT_UART_CLK_IN_HZ U(408000000)
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
/* Size of trusted dram */
#define TZDRAM_SIZE 0x00400000
#define TZDRAM_SIZE U(0x00400000)
#define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE)
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
#define BL31_SIZE 0x40000
#define BL31_SIZE U(0x40000)
#define BL31_BASE TZDRAM_BASE
#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
#define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
......@@ -53,8 +54,8 @@
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 35)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 35)
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
/*******************************************************************************
* Some data must be aligned on the biggest cache line size in the platform.
......@@ -62,6 +63,6 @@
* integrated and external caches.
******************************************************************************/
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
#endif /* __PLATFORM_DEF_H__ */
plat/nvidia/tegra/include/t132/tegra_def.h
View file @ 6de8b24f
......@@ -7,11 +7,13 @@
#ifndef __TEGRA_DEF_H__
#define __TEGRA_DEF_H__
#include <utils_def.h>
/*******************************************************************************
* This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
* call as the `state-id` field in the 'power state' parameter.
******************************************************************************/
#define PSTATE_ID_SOC_POWERDN 0xD
#define PSTATE_ID_SOC_POWERDN U(0xD)
/*******************************************************************************
* Platform power states (used by PSCI framework)
......@@ -19,80 +21,82 @@
* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
******************************************************************************/
#define PLAT_MAX_RET_STATE 1
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1)
#define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
/*******************************************************************************
* GIC memory map
******************************************************************************/
#define TEGRA_GICD_BASE 0x50041000
#define TEGRA_GICC_BASE 0x50042000
#define TEGRA_GICD_BASE U(0x50041000)
#define TEGRA_GICC_BASE U(0x50042000)
/*******************************************************************************
* Tegra micro-seconds timer constants
******************************************************************************/
#define TEGRA_TMRUS_BASE 0x60005010
#define TEGRA_TMRUS_SIZE 0x1000
#define TEGRA_TMRUS_BASE U(0x60005010)
#define TEGRA_TMRUS_SIZE U(0x1000)
/*******************************************************************************
* Tegra Clock and Reset Controller constants
******************************************************************************/
#define TEGRA_CAR_RESET_BASE 0x60006000
#define TEGRA_CAR_RESET_BASE U(0x60006000)
#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
#define GPU_RESET_BIT (U(1) << 24)
/*******************************************************************************
* Tegra Flow Controller constants
******************************************************************************/
#define TEGRA_FLOWCTRL_BASE 0x60007000
#define TEGRA_FLOWCTRL_BASE U(0x60007000)
/*******************************************************************************
* Tegra Secure Boot Controller constants
******************************************************************************/
#define TEGRA_SB_BASE 0x6000C200
#define TEGRA_SB_BASE U(0x6000C200)
/*******************************************************************************
* Tegra Exception Vectors constants
******************************************************************************/
#define TEGRA_EVP_BASE 0x6000F000
#define TEGRA_EVP_BASE U(0x6000F000)
/*******************************************************************************
* Tegra Miscellaneous register constants
******************************************************************************/
#define TEGRA_MISC_BASE 0x70000000
#define HARDWARE_REVISION_OFFSET 0x804
#define TEGRA_MISC_BASE U(0x70000000)
#define HARDWARE_REVISION_OFFSET U(0x804)
/*******************************************************************************
* Tegra UART controller base addresses
******************************************************************************/
#define TEGRA_UARTA_BASE 0x70006000
#define TEGRA_UARTB_BASE 0x70006040
#define TEGRA_UARTC_BASE 0x70006200
#define TEGRA_UARTD_BASE 0x70006300
#define TEGRA_UARTE_BASE 0x70006400
#define TEGRA_UARTA_BASE U(0x70006000)
#define TEGRA_UARTB_BASE U(0x70006040)
#define TEGRA_UARTC_BASE U(0x70006200)
#define TEGRA_UARTD_BASE U(0x70006300)
#define TEGRA_UARTE_BASE U(0x70006400)
/*******************************************************************************
* Tegra Power Mgmt Controller constants
******************************************************************************/
#define TEGRA_PMC_BASE 0x7000E400
#define TEGRA_PMC_BASE U(0x7000E400)
/*******************************************************************************
* Tegra Memory Controller constants
******************************************************************************/
#define TEGRA_MC_BASE 0x70019000
#define TEGRA_MC_BASE U(0x70019000)
/* TZDRAM carveout configuration registers */
#define MC_SECURITY_CFG0_0 0x70
#define MC_SECURITY_CFG1_0 0x74
#define MC_SECURITY_CFG3_0 0x9BC
#define MC_SECURITY_CFG0_0 U(0x70)
#define MC_SECURITY_CFG1_0 U(0x74)
#define MC_SECURITY_CFG3_0 U(0x9BC)
/* Video Memory carveout configuration registers */
#define MC_VIDEO_PROTECT_BASE_HI 0x978
#define MC_VIDEO_PROTECT_BASE_LO 0x648
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
/*******************************************************************************
* Tegra TZRAM constants
******************************************************************************/
#define TEGRA_TZRAM_BASE 0x7C010000
#define TEGRA_TZRAM_SIZE 0x10000
#define TEGRA_TZRAM_BASE U(0x7C010000)
#define TEGRA_TZRAM_SIZE U(0x10000)
#endif /* __TEGRA_DEF_H__ */
plat/nvidia/tegra/include/t186/tegra_def.h
View file @ 6de8b24f
......@@ -7,6 +7,8 @@
#ifndef __TEGRA_DEF_H__
#define __TEGRA_DEF_H__
#include <utils_def.h>
/*******************************************************************************
* MCE apertures used by the ARI interface
*
......@@ -17,34 +19,34 @@
* Aperture 4 - Cpu4 (Denver15)
* Aperture 5 - Cpu5 (Denver15)
******************************************************************************/
#define MCE_ARI_APERTURE_0_OFFSET 0x0
#define MCE_ARI_APERTURE_1_OFFSET 0x10000
#define MCE_ARI_APERTURE_2_OFFSET 0x20000
#define MCE_ARI_APERTURE_3_OFFSET 0x30000
#define MCE_ARI_APERTURE_4_OFFSET 0x40000
#define MCE_ARI_APERTURE_5_OFFSET 0x50000
#define MCE_ARI_APERTURE_0_OFFSET U(0x0)
#define MCE_ARI_APERTURE_1_OFFSET U(0x10000)
#define MCE_ARI_APERTURE_2_OFFSET U(0x20000)
#define MCE_ARI_APERTURE_3_OFFSET U(0x30000)
#define MCE_ARI_APERTURE_4_OFFSET U(0x40000)
#define MCE_ARI_APERTURE_5_OFFSET U(0x50000)
#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET
/* number of apertures */
#define MCE_ARI_APERTURES_MAX 6
#define MCE_ARI_APERTURES_MAX U(6)
/* each ARI aperture is 64KB */
#define MCE_ARI_APERTURE_SIZE 0x10000
#define MCE_ARI_APERTURE_SIZE U(0x10000)
/*******************************************************************************
* CPU core id macros for the MCE_ONLINE_CORE ARI
******************************************************************************/
#define MCE_CORE_ID_MAX 8
#define MCE_CORE_ID_MASK 0x7
#define MCE_CORE_ID_MAX U(8)
#define MCE_CORE_ID_MASK U(0x7)
/*******************************************************************************
* These values are used by the PSCI implementation during the `CPU_SUSPEND`
* and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
* parameter.
******************************************************************************/
#define PSTATE_ID_CORE_IDLE 6
#define PSTATE_ID_CORE_POWERDN 7
#define PSTATE_ID_SOC_POWERDN 2
#define PSTATE_ID_CORE_IDLE U(6)
#define PSTATE_ID_CORE_POWERDN U(7)
#define PSTATE_ID_SOC_POWERDN U(2)
/*******************************************************************************
* Platform power states (used by PSCI framework)
......@@ -52,209 +54,197 @@
* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
******************************************************************************/
#define PLAT_MAX_RET_STATE 1
#define PLAT_MAX_OFF_STATE 8
/*******************************************************************************
* Implementation defined ACTLR_EL3 bit definitions
******************************************************************************/
#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
ACTLR_EL3_L2ECTLR_BIT | \
ACTLR_EL3_L2CTLR_BIT | \
ACTLR_EL3_CPUECTLR_BIT | \
ACTLR_EL3_CPUACTLR_BIT)
#define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE U(8)
/*******************************************************************************
* Secure IRQ definitions
******************************************************************************/
#define TEGRA186_TOP_WDT_IRQ 49
#define TEGRA186_AON_WDT_IRQ 50
#define TEGRA186_TOP_WDT_IRQ U(49)
#define TEGRA186_AON_WDT_IRQ U(50)
#define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */
#define TEGRA186_SEC_IRQ_TARGET_MASK U(0xF3) /* 4 A57 - 2 Denver */
/*******************************************************************************
* Tegra Miscellanous register constants
******************************************************************************/
#define TEGRA_MISC_BASE 0x00100000
#define HARDWARE_REVISION_OFFSET 0x4
#define TEGRA_MISC_BASE U(0x00100000)
#define HARDWARE_REVISION_OFFSET U(0x4)
#define MISCREG_PFCFG 0x200C
#define MISCREG_PFCFG U(0x200C)
/*******************************************************************************
* Tegra TSA Controller constants
******************************************************************************/
#define TEGRA_TSA_BASE 0x02400000
#define TEGRA_TSA_BASE U(0x02400000)
/*******************************************************************************
* TSA configuration registers
******************************************************************************/
#define TSA_CONFIG_STATIC0_CSW_SESWR 0x4010
#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_ETRW 0x4038
#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5010
#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_AXISW 0x7008
#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_HDAW 0xA008
#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x100
#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xB018
#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0xD018
#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0xD028
#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0x12018
#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x13008
#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_AFIW 0x13018
#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_SATAW 0x13028
#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x13038
#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x15008
#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x15018
#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11)
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11)
#define TSA_CONFIG_STATIC0_CSW_SESWR U(0x4010)
#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_ETRW U(0x4038)
#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB U(0x5010)
#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_AXISW U(0x7008)
#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_HDAW U(0xA008)
#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET U(0x100)
#define TSA_CONFIG_STATIC0_CSW_AONDMAW U(0xB018)
#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_SCEDMAW U(0xD018)
#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW U(0xD028)
#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_APEDMAW U(0x12018)
#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_UFSHCW U(0x13008)
#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_AFIW U(0x13018)
#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_SATAW U(0x13028)
#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_EQOSW U(0x13038)
#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW U(0x15008)
#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET U(0x1100)
#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW U(0x15018)
#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET U(0x1100)
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (U(0x3) << 11)
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (U(0) << 11)
/*******************************************************************************
* Tegra Memory Controller constants
******************************************************************************/
#define TEGRA_MC_STREAMID_BASE 0x02C00000
#define TEGRA_MC_BASE 0x02C10000
#define TEGRA_MC_STREAMID_BASE U(0x02C00000)
#define TEGRA_MC_BASE U(0x02C10000)
/* General Security Carveout register macros */
#define MC_GSC_CONFIG_REGS_SIZE 0x40UL
#define MC_GSC_LOCK_CFG_SETTINGS_BIT (1UL << 1)
#define MC_GSC_ENABLE_TZ_LOCK_BIT (1UL << 0)
#define MC_GSC_SIZE_RANGE_4KB_SHIFT 27UL
#define MC_GSC_BASE_LO_SHIFT 12UL
#define MC_GSC_BASE_LO_MASK 0xFFFFFUL
#define MC_GSC_BASE_HI_SHIFT 0UL
#define MC_GSC_BASE_HI_MASK 3UL
#define MC_GSC_CONFIG_REGS_SIZE U(0x40)
#define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1)
#define MC_GSC_ENABLE_TZ_LOCK_BIT (U(1) << 0)
#define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27)
#define MC_GSC_BASE_LO_SHIFT U(12)
#define MC_GSC_BASE_LO_MASK U(0xFFFFF)
#define MC_GSC_BASE_HI_SHIFT U(0)
#define MC_GSC_BASE_HI_MASK U(3)
/* TZDRAM carveout configuration registers */
#define MC_SECURITY_CFG0_0 0x70
#define MC_SECURITY_CFG1_0 0x74
#define MC_SECURITY_CFG3_0 0x9BC
#define MC_SECURITY_CFG0_0 U(0x70)
#define MC_SECURITY_CFG1_0 U(0x74)
#define MC_SECURITY_CFG3_0 U(0x9BC)
/* Video Memory carveout configuration registers */
#define MC_VIDEO_PROTECT_BASE_HI 0x978
#define MC_VIDEO_PROTECT_BASE_LO 0x648
#define MC_VIDEO_PROTECT_SIZE_MB 0x64C
#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64C)
/*
* Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
* non-overlapping Video memory region
*/
#define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0
#define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4
#define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8
#define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC
#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0
#define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0)
#define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4)
#define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8)
#define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC)
#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0)
/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
#define MC_TZRAM_CARVEOUT_CFG 0x2190
#define MC_TZRAM_BASE_LO 0x2194
#define MC_TZRAM_BASE_HI 0x2198
#define MC_TZRAM_SIZE 0x219C
#define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0
#define MC_TZRAM_CARVEOUT_CFG U(0x2190)
#define MC_TZRAM_BASE_LO U(0x2194)
#define MC_TZRAM_BASE_HI U(0x2198)
#define MC_TZRAM_SIZE U(0x219C)
#define MC_TZRAM_CLIENT_ACCESS_CFG0 U(0x21A0)
/*******************************************************************************
* Tegra UART Controller constants
******************************************************************************/
#define TEGRA_UARTA_BASE 0x03100000
#define TEGRA_UARTB_BASE 0x03110000
#define TEGRA_UARTC_BASE 0x0C280000
#define TEGRA_UARTD_BASE 0x03130000
#define TEGRA_UARTE_BASE 0x03140000
#define TEGRA_UARTF_BASE 0x03150000
#define TEGRA_UARTG_BASE 0x0C290000
#define TEGRA_UARTA_BASE U(0x03100000)
#define TEGRA_UARTB_BASE U(0x03110000)
#define TEGRA_UARTC_BASE U(0x0C280000)
#define TEGRA_UARTD_BASE U(0x03130000)
#define TEGRA_UARTE_BASE U(0x03140000)
#define TEGRA_UARTF_BASE U(0x03150000)
#define TEGRA_UARTG_BASE U(0x0C290000)
/*******************************************************************************
* Tegra Fuse Controller related constants
******************************************************************************/
#define TEGRA_FUSE_BASE 0x03820000
#define OPT_SUBREVISION 0x248
#define SUBREVISION_MASK 0xFF
#define TEGRA_FUSE_BASE U(0x03820000)
#define OPT_SUBREVISION U(0x248)
#define SUBREVISION_MASK U(0xFF)
/*******************************************************************************
* GICv2 & interrupt handling related constants
******************************************************************************/
#define TEGRA_GICD_BASE 0x03881000
#define TEGRA_GICC_BASE 0x03882000
#define TEGRA_GICD_BASE U(0x03881000)
#define TEGRA_GICC_BASE U(0x03882000)
/*******************************************************************************
* Security Engine related constants
******************************************************************************/
#define TEGRA_SE0_BASE 0x03AC0000
#define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C
#define TEGRA_PKA1_BASE 0x03AD0000
#define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144
#define TEGRA_RNG1_BASE 0x03AE0000
#define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0
#define TEGRA_SE0_BASE U(0x03AC0000)
#define SE_MUTEX_WATCHDOG_NS_LIMIT U(0x6C)
#define TEGRA_PKA1_BASE U(0x03AD0000)
#define PKA_MUTEX_WATCHDOG_NS_LIMIT U(0x8144)
#define TEGRA_RNG1_BASE U(0x03AE0000)
#define RNG_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0)
/*******************************************************************************
* Tegra Clock and Reset Controller constants
******************************************************************************/
#define TEGRA_CAR_RESET_BASE 0x05000000
#define TEGRA_CAR_RESET_BASE U(0x05000000)
#define TEGRA_GPU_RESET_REG_OFFSET U(0x30)
#define GPU_RESET_BIT (U(1) << 0)
/*******************************************************************************
* Tegra micro-seconds timer constants
******************************************************************************/
#define TEGRA_TMRUS_BASE 0x0C2E0000
#define TEGRA_TMRUS_SIZE 0x1000
#define TEGRA_TMRUS_BASE U(0x0C2E0000)
#define TEGRA_TMRUS_SIZE U(0x1000)
/*******************************************************************************
* Tegra Power Mgmt Controller constants
******************************************************************************/
#define TEGRA_PMC_BASE 0x0C360000
#define TEGRA_PMC_BASE U(0x0C360000)
/*******************************************************************************
* Tegra scratch registers constants
******************************************************************************/
#define TEGRA_SCRATCH_BASE 0x0C390000
#define SECURE_SCRATCH_RSV1_LO 0x658
#define SECURE_SCRATCH_RSV1_HI 0x65C
#define SECURE_SCRATCH_RSV6 0x680
#define SECURE_SCRATCH_RSV11_LO 0x6A8
#define SECURE_SCRATCH_RSV11_HI 0x6AC
#define SECURE_SCRATCH_RSV53_LO 0x7F8
#define SECURE_SCRATCH_RSV53_HI 0x7FC
#define SECURE_SCRATCH_RSV54_HI 0x804
#define SECURE_SCRATCH_RSV55_LO 0x808
#define SECURE_SCRATCH_RSV55_HI 0x80C
#define TEGRA_SCRATCH_BASE U(0x0C390000)
#define SECURE_SCRATCH_RSV1_LO U(0x658)
#define SECURE_SCRATCH_RSV1_HI U(0x65C)
#define SECURE_SCRATCH_RSV6 U(0x680)
#define SECURE_SCRATCH_RSV11_LO U(0x6A8)
#define SECURE_SCRATCH_RSV11_HI U(0x6AC)
#define SECURE_SCRATCH_RSV53_LO U(0x7F8)
#define SECURE_SCRATCH_RSV53_HI U(0x7FC)
#define SECURE_SCRATCH_RSV54_HI U(0x804)
#define SECURE_SCRATCH_RSV55_LO U(0x808)
#define SECURE_SCRATCH_RSV55_HI U(0x80C)
/*******************************************************************************
* Tegra Memory Mapped Control Register Access constants
******************************************************************************/
#define TEGRA_MMCRAB_BASE 0x0E000000
#define TEGRA_MMCRAB_BASE U(0x0E000000)
/*******************************************************************************
* Tegra Memory Mapped Activity Monitor Register Access constants
******************************************************************************/
#define TEGRA_ARM_ACTMON_CTR_BASE 0x0E060000
#define TEGRA_DENVER_ACTMON_CTR_BASE 0x0E070000
#define TEGRA_ARM_ACTMON_CTR_BASE U(0x0E060000)
#define TEGRA_DENVER_ACTMON_CTR_BASE U(0x0E070000)
/*******************************************************************************
* Tegra SMMU Controller constants
******************************************************************************/
#define TEGRA_SMMU0_BASE 0x12000000
#define TEGRA_SMMU0_BASE U(0x12000000)
/*******************************************************************************
* Tegra TZRAM constants
******************************************************************************/
#define TEGRA_TZRAM_BASE 0x30000000
#define TEGRA_TZRAM_SIZE 0x40000
#define TEGRA_TZRAM_BASE U(0x30000000)
#define TEGRA_TZRAM_SIZE U(0x40000)
#endif /* __TEGRA_DEF_H__ */
plat/nvidia/tegra/include/t210/tegra_def.h
View file @ 6de8b24f
......@@ -7,13 +7,15 @@
#ifndef __TEGRA_DEF_H__
#define __TEGRA_DEF_H__
#include <utils_def.h>
/*******************************************************************************
* Power down state IDs
******************************************************************************/
#define PSTATE_ID_CORE_POWERDN 7
#define PSTATE_ID_CLUSTER_IDLE 16
#define PSTATE_ID_CLUSTER_POWERDN 17
#define PSTATE_ID_SOC_POWERDN 27
#define PSTATE_ID_CORE_POWERDN U(7)
#define PSTATE_ID_CLUSTER_IDLE U(16)
#define PSTATE_ID_CLUSTER_POWERDN U(17)
#define PSTATE_ID_SOC_POWERDN U(27)
/*******************************************************************************
* This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
......@@ -27,26 +29,26 @@
* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
******************************************************************************/
#define PLAT_MAX_RET_STATE 1
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1)
#define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
/*******************************************************************************
* GIC memory map
******************************************************************************/
#define TEGRA_GICD_BASE 0x50041000
#define TEGRA_GICC_BASE 0x50042000
#define TEGRA_GICD_BASE U(0x50041000)
#define TEGRA_GICC_BASE U(0x50042000)
/*******************************************************************************
* Tegra Memory Select Switch Controller constants
******************************************************************************/
#define TEGRA_MSELECT_BASE 0x50060000
#define MSELECT_CONFIG 0x0
#define ENABLE_WRAP_INCR_MASTER2_BIT (1 << 29)
#define ENABLE_WRAP_INCR_MASTER1_BIT (1 << 28)
#define ENABLE_WRAP_INCR_MASTER0_BIT (1 << 27)
#define UNSUPPORTED_TX_ERR_MASTER2_BIT (1 << 25)
#define UNSUPPORTED_TX_ERR_MASTER1_BIT (1 << 24)
#define TEGRA_MSELECT_BASE U(0x50060000)
#define MSELECT_CONFIG U(0x0)
#define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29))
#define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28))
#define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27))
#define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25))
#define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24))
#define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \
UNSUPPORTED_TX_ERR_MASTER1_BIT)
#define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \
......@@ -56,68 +58,70 @@
/*******************************************************************************
* Tegra micro-seconds timer constants
******************************************************************************/
#define TEGRA_TMRUS_BASE 0x60005010
#define TEGRA_TMRUS_SIZE 0x1000
#define TEGRA_TMRUS_BASE U(0x60005010)
#define TEGRA_TMRUS_SIZE U(0x1000)
/*******************************************************************************
* Tegra Clock and Reset Controller constants
******************************************************************************/
#define TEGRA_CAR_RESET_BASE 0x60006000
#define TEGRA_CAR_RESET_BASE U(0x60006000)
#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
#define GPU_RESET_BIT (U(1) << 24)
/*******************************************************************************
* Tegra Flow Controller constants
******************************************************************************/
#define TEGRA_FLOWCTRL_BASE 0x60007000
#define TEGRA_FLOWCTRL_BASE U(0x60007000)
/*******************************************************************************
* Tegra Secure Boot Controller constants
******************************************************************************/
#define TEGRA_SB_BASE 0x6000C200
#define TEGRA_SB_BASE U(0x6000C200)
/*******************************************************************************
* Tegra Exception Vectors constants
******************************************************************************/
#define TEGRA_EVP_BASE 0x6000F000
#define TEGRA_EVP_BASE U(0x6000F000)
/*******************************************************************************
* Tegra Miscellaneous register constants
******************************************************************************/
#define TEGRA_MISC_BASE 0x70000000
#define HARDWARE_REVISION_OFFSET 0x804
#define TEGRA_MISC_BASE U(0x70000000)
#define HARDWARE_REVISION_OFFSET U(0x804)
/*******************************************************************************
* Tegra UART controller base addresses
******************************************************************************/
#define TEGRA_UARTA_BASE 0x70006000
#define TEGRA_UARTB_BASE 0x70006040
#define TEGRA_UARTC_BASE 0x70006200
#define TEGRA_UARTD_BASE 0x70006300
#define TEGRA_UARTE_BASE 0x70006400
#define TEGRA_UARTA_BASE U(0x70006000)
#define TEGRA_UARTB_BASE U(0x70006040)
#define TEGRA_UARTC_BASE U(0x70006200)
#define TEGRA_UARTD_BASE U(0x70006300)
#define TEGRA_UARTE_BASE U(0x70006400)
/*******************************************************************************
* Tegra Power Mgmt Controller constants
******************************************************************************/
#define TEGRA_PMC_BASE 0x7000E400
#define TEGRA_PMC_BASE U(0x7000E400)
/*******************************************************************************
* Tegra Memory Controller constants
******************************************************************************/
#define TEGRA_MC_BASE 0x70019000
#define TEGRA_MC_BASE U(0x70019000)
/* TZDRAM carveout configuration registers */
#define MC_SECURITY_CFG0_0 0x70
#define MC_SECURITY_CFG1_0 0x74
#define MC_SECURITY_CFG3_0 0x9BC
#define MC_SECURITY_CFG0_0 U(0x70)
#define MC_SECURITY_CFG1_0 U(0x74)
#define MC_SECURITY_CFG3_0 U(0x9BC)
/* Video Memory carveout configuration registers */
#define MC_VIDEO_PROTECT_BASE_HI 0x978
#define MC_VIDEO_PROTECT_BASE_LO 0x648
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
/*******************************************************************************
* Tegra TZRAM constants
******************************************************************************/
#define TEGRA_TZRAM_BASE 0x7C010000
#define TEGRA_TZRAM_SIZE 0x10000
#define TEGRA_TZRAM_BASE U(0x7C010000)
#define TEGRA_TZRAM_SIZE U(0x10000)
#endif /* __TEGRA_DEF_H__ */
plat/nvidia/tegra/include/tegra_private.h
View file @ 6de8b24f
......@@ -15,8 +15,8 @@
/*******************************************************************************
* Tegra DRAM memory base address
******************************************************************************/
#define TEGRA_DRAM_BASE 0x80000000ULL
#define TEGRA_DRAM_END 0x27FFFFFFFULL
#define TEGRA_DRAM_BASE ULL(0x80000000)
#define TEGRA_DRAM_END ULL(0x27FFFFFFF)
/*******************************************************************************
* Struct for parameters received from BL2
......@@ -71,8 +71,8 @@ int tegra_fiq_get_intr_context(void);
void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint);
/* Declarations for tegra_gic.c */
void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, unsigned int num_irqs);
void tegra_gic_cpuif_deactivate(void);
void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, uint32_t num_irqs);
/* Declarations for tegra_security.c */
void tegra_security_setup(void);
......
plat/nvidia/tegra/platform.mk
View file @ 6de8b24f
......@@ -34,3 +34,6 @@ include ${SOC_DIR}/platform_${TARGET_SOC}.mk
# modify BUILD_PLAT to point to SoC specific build directory
BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${TARGET_SOC}/${BUILD_TYPE}
# enable signed comparison checks
CFLAGS += -Wsign-compare
plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
View file @ 6de8b24f
......@@ -49,7 +49,7 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
}
/* Set lower power states to PLAT_MAX_OFF_STATE */
for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
/* Set the SYSTEM_SUSPEND state-id */
......
plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h
View file @ 6de8b24f
......@@ -14,127 +14,68 @@
* Macros to prepare CSTATE info request
******************************************************************************/
/* Description of the parameters for UPDATE_CSTATE_INFO request */
#define CLUSTER_CSTATE_MASK 0x7ULL
#define CLUSTER_CSTATE_SHIFT 0U
#define CLUSTER_CSTATE_UPDATE_BIT (1ULL << 7)
#define CCPLEX_CSTATE_MASK 0x3ULL
#define CCPLEX_CSTATE_SHIFT 8ULL
#define CCPLEX_CSTATE_UPDATE_BIT (1ULL << 15)
#define SYSTEM_CSTATE_MASK 0xFULL
#define SYSTEM_CSTATE_SHIFT 16ULL
#define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT 22ULL
#define SYSTEM_CSTATE_FORCE_UPDATE_BIT (1ULL << 22)
#define SYSTEM_CSTATE_UPDATE_BIT (1ULL << 23)
#define CSTATE_WAKE_MASK_UPDATE_BIT (1ULL << 31)
#define CSTATE_WAKE_MASK_SHIFT 32ULL
#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFU
#define CLUSTER_CSTATE_MASK ULL(0x7)
#define CLUSTER_CSTATE_SHIFT U(0)
#define CLUSTER_CSTATE_UPDATE_BIT (ULL(1) << 7)
#define CCPLEX_CSTATE_MASK ULL(0x3)
#define CCPLEX_CSTATE_SHIFT ULL(8)
#define CCPLEX_CSTATE_UPDATE_BIT (ULL(1) << 15)
#define SYSTEM_CSTATE_MASK ULL(0xF)
#define SYSTEM_CSTATE_SHIFT ULL(16)
#define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT ULL(22)
#define SYSTEM_CSTATE_FORCE_UPDATE_BIT (ULL(1) << 22)
#define SYSTEM_CSTATE_UPDATE_BIT (ULL(1) << 23)
#define CSTATE_WAKE_MASK_UPDATE_BIT (ULL(1) << 31)
#define CSTATE_WAKE_MASK_SHIFT ULL(32)
#define CSTATE_WAKE_MASK_CLEAR U(0xFFFFFFFF)
/*******************************************************************************
* Auto-CC3 control macros
******************************************************************************/
#define MCE_AUTO_CC3_FREQ_MASK 0x1FFU
#define MCE_AUTO_CC3_FREQ_SHIFT 0U
#define MCE_AUTO_CC3_VTG_MASK 0x7FU
#define MCE_AUTO_CC3_VTG_SHIFT 16U
#define MCE_AUTO_CC3_ENABLE_BIT (1U << 31)
#define MCE_AUTO_CC3_FREQ_MASK U(0x1FF)
#define MCE_AUTO_CC3_FREQ_SHIFT U(0)
#define MCE_AUTO_CC3_VTG_MASK U(0x7F)
#define MCE_AUTO_CC3_VTG_SHIFT U(16)
#define MCE_AUTO_CC3_ENABLE_BIT (U(1) << 31)
/*******************************************************************************
* Macros for the 'IS_SC7_ALLOWED' command
******************************************************************************/
#define MCE_SC7_ALLOWED_MASK 0x7U
#define MCE_SC7_WAKE_TIME_SHIFT 32U
#define MCE_SC7_ALLOWED_MASK U(0x7)
#define MCE_SC7_WAKE_TIME_SHIFT U(32)
/*******************************************************************************
* Macros for 'read/write ctats' commands
******************************************************************************/
#define MCE_CSTATE_STATS_TYPE_SHIFT 32ULL
#define MCE_CSTATE_WRITE_DATA_LO_MASK 0xFU
#define MCE_CSTATE_STATS_TYPE_SHIFT ULL(32)
#define MCE_CSTATE_WRITE_DATA_LO_MASK U(0xF)
/*******************************************************************************
* Macros for 'update crossover threshold' command
******************************************************************************/
#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32U
#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT U(32)
/*******************************************************************************
* MCA command struct
* MCA argument macros
******************************************************************************/
typedef union mca_cmd {
struct command {
uint8_t cmd;
uint8_t idx;
uint8_t subidx;
} command;
struct input {
uint32_t low;
uint32_t high;
} input;
uint64_t data;
} mca_cmd_t;
/*******************************************************************************
* MCA argument struct
******************************************************************************/
typedef union mca_arg {
struct err {
uint32_t error:8;
uint32_t unused:24;
uint32_t unused2:24;
uint32_t finish:8;
} err;
struct arg {
uint32_t low;
uint32_t high;
} arg;
uint64_t data;
} mca_arg_t;
#define MCA_ARG_ERROR_MASK U(0xFF)
#define MCA_ARG_FINISH_SHIFT U(24)
#define MCA_ARG_FINISH_MASK U(0xFF)
/*******************************************************************************
* Uncore PERFMON ARI struct
******************************************************************************/
typedef union uncore_perfmon_req {
struct perfmon_command {
/*
* Commands: 0 = READ, 1 = WRITE
*/
uint32_t cmd:8;
/*
* The unit group: L2=0, L3=1, ROC=2, MC=3, IOB=4
*/
uint32_t grp:4;
/*
* Unit selector: Selects the unit instance, with 0 = Unit
* = (number of units in group) - 1.
*/
uint32_t unit:4;
/*
* Selects the uncore perfmon register to access
*/
uint32_t reg:8;
/*
* Counter number. Selects which counter to use for
* registers NV_PMEVCNTR and NV_PMEVTYPER.
*/
uint32_t counter:8;
} perfmon_command;
struct perfmon_status {
/*
* Resulting command status
*/
uint32_t val:8;
uint32_t unused:24;
} perfmon_status;
uint64_t data;
} uncore_perfmon_req_t;
#define UNCORE_PERFMON_CMD_READ 0U
#define UNCORE_PERFMON_CMD_WRITE 1U
#define UNCORE_PERFMON_CMD_READ U(0)
#define UNCORE_PERFMON_CMD_WRITE U(1)
#define UNCORE_PERFMON_CMD_MASK 0xFFU
#define UNCORE_PERFMON_UNIT_GRP_MASK 0xFU
#define UNCORE_PERFMON_SELECTOR_MASK 0xFU
#define UNCORE_PERFMON_REG_MASK 0xFFU
#define UNCORE_PERFMON_CTR_MASK 0xFFU
#define UNCORE_PERFMON_RESP_STATUS_MASK 0xFFU
#define UNCORE_PERFMON_CMD_MASK U(0xFF)
#define UNCORE_PERFMON_CMD_SHIFT U(24)
#define UNCORE_PERFMON_UNIT_GRP_MASK U(0xF)
#define UNCORE_PERFMON_SELECTOR_MASK U(0xF)
#define UNCORE_PERFMON_REG_MASK U(0xFF)
#define UNCORE_PERFMON_CTR_MASK U(0xFF)
#define UNCORE_PERFMON_RESP_STATUS_MASK U(0xFF)
#define UNCORE_PERFMON_RESP_STATUS_SHIFT U(24)
/*******************************************************************************
* Structure populated by arch specific code to export routines which perform
......@@ -146,13 +87,13 @@ typedef struct arch_mce_ops {
* of STANDBYWFI, update the core power state and expected wake time,
* then determine the proper power state to enter.
*/
int (*enter_cstate)(uint32_t ari_base, uint32_t state,
int32_t (*enter_cstate)(uint32_t ari_base, uint32_t state,
uint32_t wake_time);
/*
* This ARI request allows updating of the CLUSTER_CSTATE,
* CCPLEX_CSTATE, and SYSTEM_CSTATE register values.
*/
int (*update_cstate_info)(uint32_t ari_base,
int32_t (*update_cstate_info)(uint32_t ari_base,
uint32_t cluster,
uint32_t ccplex,
uint32_t system,
......@@ -164,7 +105,7 @@ typedef struct arch_mce_ops {
* threshold times. An index value specifies which crossover
* state is being updated.
*/
int (*update_crossover_time)(uint32_t ari_base,
int32_t (*update_crossover_time)(uint32_t ari_base,
uint32_t type,
uint32_t time);
/*
......@@ -177,7 +118,7 @@ typedef struct arch_mce_ops {
* This ARI request allows write access to statistical information
* related to power states.
*/
int (*write_cstate_stats)(uint32_t ari_base,
int32_t (*write_cstate_stats)(uint32_t ari_base,
uint32_t state,
uint32_t stats);
/*
......@@ -193,7 +134,7 @@ typedef struct arch_mce_ops {
* must be entered. If the CCx state is not allowed, the response
* indicates CC6/CC7 can't be entered
*/
int (*is_ccx_allowed)(uint32_t ari_base, uint32_t state,
int32_t (*is_ccx_allowed)(uint32_t ari_base, uint32_t state,
uint32_t wake_time);
/*
* This ARI request allows querying the CCPLEX to determine if
......@@ -203,19 +144,19 @@ typedef struct arch_mce_ops {
* indicates SC7 must be entered. If the SC7 state is not allowed,
* the response indicates SC7 can't be entered
*/
int (*is_sc7_allowed)(uint32_t ari_base, uint32_t state,
int32_t (*is_sc7_allowed)(uint32_t ari_base, uint32_t state,
uint32_t wake_time);
/*
* This ARI request allows a core to bring another offlined core
* back online to the C0 state. Note that a core is offlined by
* entering a C-state where the WAKE_MASK is all 0.
*/
int (*online_core)(uint32_t ari_base, uint32_t cpuid);
int32_t (*online_core)(uint32_t ari_base, uint32_t cpuid);
/*
* This ARI request allows the CPU to enable/disable Auto-CC3 idle
* state.
*/
int (*cc3_ctrl)(uint32_t ari_base,
int32_t (*cc3_ctrl)(uint32_t ari_base,
uint32_t freq,
uint32_t volt,
uint8_t enable);
......@@ -223,30 +164,30 @@ typedef struct arch_mce_ops {
* This ARI request allows updating the reset vector register for
* D15 and A57 CPUs.
*/
int (*update_reset_vector)(uint32_t ari_base);
int32_t (*update_reset_vector)(uint32_t ari_base);
/*
* This ARI request instructs the ROC to flush A57 data caches in
* order to maintain coherency with the Denver cluster.
*/
int (*roc_flush_cache)(uint32_t ari_base);
int32_t (*roc_flush_cache)(uint32_t ari_base);
/*
* This ARI request instructs the ROC to flush A57 data caches along
* with the caches covering ARM code in order to maintain coherency
* with the Denver cluster.
*/
int (*roc_flush_cache_trbits)(uint32_t ari_base);
int32_t (*roc_flush_cache_trbits)(uint32_t ari_base);
/*
* This ARI request instructs the ROC to clean A57 data caches along
* with the caches covering ARM code in order to maintain coherency
* with the Denver cluster.
*/
int (*roc_clean_cache)(uint32_t ari_base);
int32_t (*roc_clean_cache)(uint32_t ari_base);
/*
* This ARI request reads/writes the Machine Check Arch. (MCA)
* registers.
*/
uint64_t (*read_write_mca)(uint32_t ari_base,
mca_cmd_t cmd,
uint64_t cmd,
uint64_t *data);
/*
* Some MC GSC (General Security Carveout) register values are
......@@ -258,7 +199,7 @@ typedef struct arch_mce_ops {
* register value. This ARI request allows updating the GSC register
* value for a certain carveout in the CCPLEX.
*/
int (*update_ccplex_gsc)(uint32_t ari_base, uint32_t gsc_idx);
int32_t (*update_ccplex_gsc)(uint32_t ari_base, uint32_t gsc_idx);
/*
* This ARI request instructs the CCPLEX to either shutdown or
* reset the entire system
......@@ -268,8 +209,8 @@ typedef struct arch_mce_ops {
* This ARI request reads/writes data from/to Uncore PERFMON
* registers
*/
int (*read_write_uncore_perfmon)(uint32_t ari_base,
uncore_perfmon_req_t req, uint64_t *data);
int32_t (*read_write_uncore_perfmon)(uint32_t ari_base,
uint64_t req, uint64_t *data);
/*
* This ARI implements ARI_MISC_CCPLEX commands. This can be
* used to enable/disable coresight clock gating.
......@@ -279,39 +220,42 @@ typedef struct arch_mce_ops {
} arch_mce_ops_t;
/* declarations for ARI/NVG handler functions */
int ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
int ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
uint32_t system, uint8_t sys_state_force, uint32_t wake_mask,
uint8_t update_wake_mask);
int ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time);
int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time);
uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state);
int ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats);
int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats);
uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data);
int ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
int ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
int ari_online_core(uint32_t ari_base, uint32_t core);
int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
int ari_reset_vector_update(uint32_t ari_base);
int ari_roc_flush_cache_trbits(uint32_t ari_base);
int ari_roc_flush_cache(uint32_t ari_base);
int ari_roc_clean_cache(uint32_t ari_base);
uint64_t ari_read_write_mca(uint32_t ari_base, mca_cmd_t cmd, uint64_t *data);
int ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx);
int32_t ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
int32_t ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
int32_t ari_online_core(uint32_t ari_base, uint32_t core);
int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
int32_t ari_reset_vector_update(uint32_t ari_base);
int32_t ari_roc_flush_cache_trbits(uint32_t ari_base);
int32_t ari_roc_flush_cache(uint32_t ari_base);
int32_t ari_roc_clean_cache(uint32_t ari_base);
uint64_t ari_read_write_mca(uint32_t ari_base, uint64_t cmd, uint64_t *data);
int32_t ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx);
void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx);
int ari_read_write_uncore_perfmon(uint32_t ari_base,
uncore_perfmon_req_t req, uint64_t *data);
int32_t ari_read_write_uncore_perfmon(uint32_t ari_base,
uint64_t req, uint64_t *data);
void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value);
int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
uint32_t system, uint8_t sys_state_force, uint32_t wake_mask,
uint8_t update_wake_mask);
int nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time);
int32_t nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time);
uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state);
int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t val);
int nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
int nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
int nvg_online_core(uint32_t ari_base, uint32_t core);
int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
int32_t nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats);
int32_t nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
int32_t nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
int32_t nvg_online_core(uint32_t ari_base, uint32_t core);
int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
extern void nvg_set_request_data(uint64_t req, uint64_t data);
extern void nvg_set_request(uint64_t req);
extern uint64_t nvg_get_result(void);
#endif /* __MCE_PRIVATE_H__ */
plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
View file @ 6de8b24f
......@@ -19,13 +19,13 @@
/*******************************************************************************
* Register offsets for ARI request/results
******************************************************************************/
#define ARI_REQUEST 0x0
#define ARI_REQUEST_EVENT_MASK 0x4
#define ARI_STATUS 0x8
#define ARI_REQUEST_DATA_LO 0xC
#define ARI_REQUEST_DATA_HI 0x10
#define ARI_RESPONSE_DATA_LO 0x14
#define ARI_RESPONSE_DATA_HI 0x18
#define ARI_REQUEST 0x0U
#define ARI_REQUEST_EVENT_MASK 0x4U
#define ARI_STATUS 0x8U
#define ARI_REQUEST_DATA_LO 0xCU
#define ARI_REQUEST_DATA_HI 0x10U
#define ARI_RESPONSE_DATA_LO 0x14U
#define ARI_RESPONSE_DATA_HI 0x18U
/* Status values for the current request */
#define ARI_REQ_PENDING 1U
......@@ -41,12 +41,12 @@
******************************************************************************/
static inline uint32_t ari_read_32(uint32_t ari_base, uint32_t reg)
{
return mmio_read_32(ari_base + reg);
return mmio_read_32((uint64_t)ari_base + (uint64_t)reg);
}
static inline void ari_write_32(uint32_t ari_base, uint32_t val, uint32_t reg)
{
mmio_write_32(ari_base + reg, val);
mmio_write_32((uint64_t)ari_base + (uint64_t)reg, val);
}
static inline uint32_t ari_get_request_low(uint32_t ari_base)
......@@ -75,11 +75,12 @@ static inline void ari_clobber_response(uint32_t ari_base)
ari_write_32(ari_base, 0, ARI_RESPONSE_DATA_HI);
}
static int ari_request_wait(uint32_t ari_base, uint32_t evt_mask, uint32_t req,
static int32_t ari_request_wait(uint32_t ari_base, uint32_t evt_mask, uint32_t req,
uint32_t lo, uint32_t hi)
{
uint32_t retries = ARI_MAX_RETRY_COUNT;
uint32_t status;
int32_t ret = 0;
/* program the request, event_mask, hi and lo registers */
ari_write_32(ari_base, lo, ARI_REQUEST_DATA_LO);
......@@ -92,236 +93,270 @@ static int ari_request_wait(uint32_t ari_base, uint32_t evt_mask, uint32_t req,
* ARI_STATUS polling, since MCE is waiting for SW to trigger
* the event.
*/
if (evt_mask)
return 0;
/* For shutdown/reboot commands, we dont have to check for timeouts */
if ((req == (uint32_t)TEGRA_ARI_MISC_CCPLEX) &&
((lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) ||
(lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT))) {
return 0;
}
/*
* Wait for the command response for not more than the timeout
*/
while (retries != 0U) {
/* read the command status */
status = ari_read_32(ari_base, ARI_STATUS);
if ((status & (ARI_REQ_ONGOING | ARI_REQ_PENDING)) == 0U)
break;
/* delay 1 ms */
mdelay(1);
/* decrement the retry count */
retries--;
}
/* assert if the command timed out */
if (retries == 0U) {
ERROR("ARI request timed out: req %d on CPU %d\n",
req, plat_my_core_pos());
assert(retries != 0U);
if (evt_mask != 0U) {
ret = 0;
} else {
/* For shutdown/reboot commands, we dont have to check for timeouts */
if ((req == (uint32_t)TEGRA_ARI_MISC_CCPLEX) &&
((lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) ||
(lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT))) {
ret = 0;
} else {
/*
* Wait for the command response for not more than the timeout
*/
while (retries != 0U) {
/* read the command status */
status = ari_read_32(ari_base, ARI_STATUS);
if ((status & (ARI_REQ_ONGOING | ARI_REQ_PENDING)) == 0U) {
break;
}
/* delay 1 ms */
mdelay(1);
/* decrement the retry count */
retries--;
}
/* assert if the command timed out */
if (retries == 0U) {
ERROR("ARI request timed out: req %d on CPU %d\n",
req, plat_my_core_pos());
assert(retries != 0U);
}
}
}
return 0;
return ret;
}
int ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time)
int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time)
{
int32_t ret = 0;
/* check for allowed power state */
if (state != TEGRA_ARI_CORE_C0 && state != TEGRA_ARI_CORE_C1 &&
state != TEGRA_ARI_CORE_C6 && state != TEGRA_ARI_CORE_C7) {
if ((state != TEGRA_ARI_CORE_C0) &&
(state != TEGRA_ARI_CORE_C1) &&
(state != TEGRA_ARI_CORE_C6) &&
(state != TEGRA_ARI_CORE_C7)) {
ERROR("%s: unknown cstate (%d)\n", __func__, state);
return EINVAL;
}
/* clean the previous response state */
ari_clobber_response(ari_base);
ret = EINVAL;
} else {
/* clean the previous response state */
ari_clobber_response(ari_base);
/* Enter the cstate, to be woken up after wake_time (TSC ticks) */
return ari_request_wait(ari_base, ARI_EVT_MASK_STANDBYWFI_BIT,
/* Enter the cstate, to be woken up after wake_time (TSC ticks) */
ret = ari_request_wait(ari_base, ARI_EVT_MASK_STANDBYWFI_BIT,
TEGRA_ARI_ENTER_CSTATE, state, wake_time);
}
return ret;
}
int ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
uint32_t system, uint8_t sys_state_force, uint32_t wake_mask,
uint8_t update_wake_mask)
{
uint32_t val = 0;
uint32_t val = 0U;
/* clean the previous response state */
ari_clobber_response(ari_base);
/* update CLUSTER_CSTATE? */
if (cluster)
val |= (cluster & CLUSTER_CSTATE_MASK) |
CLUSTER_CSTATE_UPDATE_BIT;
if (cluster != 0U) {
val |= (cluster & (uint32_t)CLUSTER_CSTATE_MASK) |
(uint32_t)CLUSTER_CSTATE_UPDATE_BIT;
}
/* update CCPLEX_CSTATE? */
if (ccplex)
val |= (ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT |
CCPLEX_CSTATE_UPDATE_BIT;
if (ccplex != 0U) {
val |= ((ccplex & (uint32_t)CCPLEX_CSTATE_MASK) << (uint32_t)CCPLEX_CSTATE_SHIFT) |
(uint32_t)CCPLEX_CSTATE_UPDATE_BIT;
}
/* update SYSTEM_CSTATE? */
if (system)
val |= ((system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) |
((sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) |
SYSTEM_CSTATE_UPDATE_BIT);
if (system != 0U) {
val |= ((system & (uint32_t)SYSTEM_CSTATE_MASK) << (uint32_t)SYSTEM_CSTATE_SHIFT) |
(((uint32_t)sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) |
(uint32_t)SYSTEM_CSTATE_UPDATE_BIT);
}
/* update wake mask value? */
if (update_wake_mask)
val |= CSTATE_WAKE_MASK_UPDATE_BIT;
if (update_wake_mask != 0U) {
val |= (uint32_t)CSTATE_WAKE_MASK_UPDATE_BIT;
}
/* set the updated cstate info */
return ari_request_wait(ari_base, 0, TEGRA_ARI_UPDATE_CSTATE_INFO, val,
return ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CSTATE_INFO, val,
wake_mask);
}
int ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time)
int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time)
{
int32_t ret = 0;
/* sanity check crossover type */
if ((type == TEGRA_ARI_CROSSOVER_C1_C6) ||
(type > TEGRA_ARI_CROSSOVER_CCP3_SC1))
return EINVAL;
/* clean the previous response state */
ari_clobber_response(ari_base);
/* update crossover threshold time */
return ari_request_wait(ari_base, 0, TEGRA_ARI_UPDATE_CROSSOVER,
(type > TEGRA_ARI_CROSSOVER_CCP3_SC1)) {
ret = EINVAL;
} else {
/* clean the previous response state */
ari_clobber_response(ari_base);
/* update crossover threshold time */
ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CROSSOVER,
type, time);
}
return ret;
}
uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state)
{
int ret;
int32_t ret;
uint64_t result;
/* sanity check crossover type */
if (state == 0)
return EINVAL;
/* clean the previous response state */
ari_clobber_response(ari_base);
ret = ari_request_wait(ari_base, 0, TEGRA_ARI_CSTATE_STATS, state, 0);
if (ret != 0)
return EINVAL;
return (uint64_t)ari_get_response_low(ari_base);
if (state == 0U) {
result = EINVAL;
} else {
/* clean the previous response state */
ari_clobber_response(ari_base);
ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_CSTATE_STATS, state, 0U);
if (ret != 0) {
result = EINVAL;
} else {
result = (uint64_t)ari_get_response_low(ari_base);
}
}
return result;
}
int ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats)
int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats)
{
/* clean the previous response state */
ari_clobber_response(ari_base);
/* write the cstate stats */
return ari_request_wait(ari_base, 0, TEGRA_ARI_WRITE_CSTATE_STATS, state,
return ari_request_wait(ari_base, 0U, TEGRA_ARI_WRITE_CSTATE_STATS, state,
stats);
}
uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data)
{
uint64_t resp;
int ret;
int32_t ret;
uint32_t local_data = data;
/* clean the previous response state */
ari_clobber_response(ari_base);
/* ARI_REQUEST_DATA_HI is reserved for commands other than 'ECHO' */
if (cmd != TEGRA_ARI_MISC_ECHO)
data = 0;
ret = ari_request_wait(ari_base, 0, TEGRA_ARI_MISC, cmd, data);
if (ret)
return (uint64_t)ret;
if (cmd != TEGRA_ARI_MISC_ECHO) {
local_data = 0U;
}
/* get the command response */
resp = ari_get_response_low(ari_base);
resp |= ((uint64_t)ari_get_response_high(ari_base) << 32);
ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC, cmd, local_data);
if (ret != 0) {
resp = (uint64_t)ret;
} else {
/* get the command response */
resp = ari_get_response_low(ari_base);
resp |= ((uint64_t)ari_get_response_high(ari_base) << 32);
}
return resp;
}
int ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time)
int32_t ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time)
{
int ret;
int32_t ret;
uint32_t result;
/* clean the previous response state */
ari_clobber_response(ari_base);
ret = ari_request_wait(ari_base, 0, TEGRA_ARI_IS_CCX_ALLOWED, state & 0x7,
ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_IS_CCX_ALLOWED, state & 0x7U,
wake_time);
if (ret) {
if (ret != 0) {
ERROR("%s: failed (%d)\n", __func__, ret);
return 0;
result = 0U;
} else {
result = ari_get_response_low(ari_base) & 0x1U;
}
/* 1 = CCx allowed, 0 = CCx not allowed */
return (ari_get_response_low(ari_base) & 0x1);
return (int32_t)result;
}
int ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time)
int32_t ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time)
{
int ret;
int32_t ret, result;
/* check for allowed power state */
if (state != TEGRA_ARI_CORE_C0 && state != TEGRA_ARI_CORE_C1 &&
state != TEGRA_ARI_CORE_C6 && state != TEGRA_ARI_CORE_C7) {
if ((state != TEGRA_ARI_CORE_C0) &&
(state != TEGRA_ARI_CORE_C1) &&
(state != TEGRA_ARI_CORE_C6) &&
(state != TEGRA_ARI_CORE_C7)) {
ERROR("%s: unknown cstate (%d)\n", __func__, state);
return EINVAL;
}
/* clean the previous response state */
ari_clobber_response(ari_base);
ret = ari_request_wait(ari_base, 0, TEGRA_ARI_IS_SC7_ALLOWED, state,
wake_time);
if (ret) {
ERROR("%s: failed (%d)\n", __func__, ret);
return 0;
result = EINVAL;
} else {
/* clean the previous response state */
ari_clobber_response(ari_base);
ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_IS_SC7_ALLOWED, state,
wake_time);
if (ret != 0) {
ERROR("%s: failed (%d)\n", __func__, ret);
result = 0;
} else {
/* 1 = SC7 allowed, 0 = SC7 not allowed */
result = (ari_get_response_low(ari_base) != 0U) ? 1 : 0;
}
}
/* 1 = SC7 allowed, 0 = SC7 not allowed */
return !!ari_get_response_low(ari_base);
return result;
}
int ari_online_core(uint32_t ari_base, uint32_t core)
int32_t ari_online_core(uint32_t ari_base, uint32_t core)
{
int cpu = read_mpidr() & MPIDR_CPU_MASK;
int cluster = (read_mpidr() & MPIDR_CLUSTER_MASK) >>
MPIDR_AFFINITY_BITS;
int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
uint64_t cpu = read_mpidr() & (uint64_t)(MPIDR_CPU_MASK);
uint64_t cluster = (read_mpidr() & (uint64_t)(MPIDR_CLUSTER_MASK)) >>
(uint64_t)(MPIDR_AFFINITY_BITS);
uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK;
int32_t ret;
/* construct the current CPU # */
cpu |= (cluster << 2);
/* sanity check target core id */
if ((core >= MCE_CORE_ID_MAX) || (cpu == core)) {
if ((core >= MCE_CORE_ID_MAX) || (cpu == (uint64_t)core)) {
ERROR("%s: unsupported core id (%d)\n", __func__, core);
return EINVAL;
}
/*
* The Denver cluster has 2 CPUs only - 0, 1.
*/
if (impl == DENVER_IMPL && ((core == 2) || (core == 3))) {
ERROR("%s: unknown core id (%d)\n", __func__, core);
return EINVAL;
ret = EINVAL;
} else {
/*
* The Denver cluster has 2 CPUs only - 0, 1.
*/
if ((impl == (uint32_t)DENVER_IMPL) &&
((core == 2U) || (core == 3U))) {
ERROR("%s: unknown core id (%d)\n", __func__, core);
ret = EINVAL;
} else {
/* clean the previous response state */
ari_clobber_response(ari_base);
ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_ONLINE_CORE, core, 0U);
}
}
/* clean the previous response state */
ari_clobber_response(ari_base);
return ari_request_wait(ari_base, 0, TEGRA_ARI_ONLINE_CORE, core, 0);
return ret;
}
int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable)
int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable)
{
int val;
uint32_t val;
/* clean the previous response state */
ari_clobber_response(ari_base);
......@@ -338,12 +373,12 @@ int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable
*/
val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\
((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\
(enable ? MCE_AUTO_CC3_ENABLE_BIT : 0));
((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U));
return ari_request_wait(ari_base, 0, TEGRA_ARI_CC3_CTRL, val, 0);
return ari_request_wait(ari_base, 0U, TEGRA_ARI_CC3_CTRL, val, 0U);
}
int ari_reset_vector_update(uint32_t ari_base)
int32_t ari_reset_vector_update(uint32_t ari_base)
{
/* clean the previous response state */
ari_clobber_response(ari_base);
......@@ -352,85 +387,97 @@ int ari_reset_vector_update(uint32_t ari_base)
* Need to program the CPU reset vector one time during cold boot
* and SC7 exit
*/
ari_request_wait(ari_base, 0, TEGRA_ARI_COPY_MISCREG_AA64_RST, 0, 0);
(void)ari_request_wait(ari_base, 0U, TEGRA_ARI_COPY_MISCREG_AA64_RST, 0U, 0U);
return 0;
}
int ari_roc_flush_cache_trbits(uint32_t ari_base)
int32_t ari_roc_flush_cache_trbits(uint32_t ari_base)
{
/* clean the previous response state */
ari_clobber_response(ari_base);
return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS,
0, 0);
return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS,
0U, 0U);
}
int ari_roc_flush_cache(uint32_t ari_base)
int32_t ari_roc_flush_cache(uint32_t ari_base)
{
/* clean the previous response state */
ari_clobber_response(ari_base);
return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_FLUSH_CACHE_ONLY,
0, 0);
return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_FLUSH_CACHE_ONLY,
0U, 0U);
}
int ari_roc_clean_cache(uint32_t ari_base)
int32_t ari_roc_clean_cache(uint32_t ari_base)
{
/* clean the previous response state */
ari_clobber_response(ari_base);
return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_CLEAN_CACHE_ONLY,
0, 0);
return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_CLEAN_CACHE_ONLY,
0U, 0U);
}
uint64_t ari_read_write_mca(uint32_t ari_base, mca_cmd_t cmd, uint64_t *data)
uint64_t ari_read_write_mca(uint32_t ari_base, uint64_t cmd, uint64_t *data)
{
mca_arg_t mca_arg;
int ret;
uint64_t mca_arg_data, result = 0;
uint32_t resp_lo, resp_hi;
uint32_t mca_arg_err, mca_arg_finish;
int32_t ret;
/* Set data (write) */
mca_arg.data = data ? *data : 0ull;
mca_arg_data = (data != NULL) ? *data : 0ULL;
/* Set command */
ari_write_32(ari_base, cmd.input.low, ARI_RESPONSE_DATA_LO);
ari_write_32(ari_base, cmd.input.high, ARI_RESPONSE_DATA_HI);
ret = ari_request_wait(ari_base, 0, TEGRA_ARI_MCA, mca_arg.arg.low,
mca_arg.arg.high);
if (!ret) {
mca_arg.arg.low = ari_get_response_low(ari_base);
mca_arg.arg.high = ari_get_response_high(ari_base);
if (!mca_arg.err.finish)
return (uint64_t)mca_arg.err.error;
if (data) {
mca_arg.arg.low = ari_get_request_low(ari_base);
mca_arg.arg.high = ari_get_request_high(ari_base);
*data = mca_arg.data;
ari_write_32(ari_base, (uint32_t)cmd, ARI_RESPONSE_DATA_LO);
ari_write_32(ari_base, (uint32_t)(cmd >> 32U), ARI_RESPONSE_DATA_HI);
ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_MCA,
(uint32_t)mca_arg_data,
(uint32_t)(mca_arg_data >> 32UL));
if (ret == 0) {
resp_lo = ari_get_response_low(ari_base);
resp_hi = ari_get_response_high(ari_base);
mca_arg_err = resp_lo & MCA_ARG_ERROR_MASK;
mca_arg_finish = (resp_hi >> MCA_ARG_FINISH_SHIFT) &
MCA_ARG_FINISH_MASK;
if (mca_arg_finish == 0U) {
result = (uint64_t)mca_arg_err;
} else {
if (data != NULL) {
resp_lo = ari_get_request_low(ari_base);
resp_hi = ari_get_request_high(ari_base);
*data = ((uint64_t)resp_hi << 32UL) |
(uint64_t)resp_lo;
}
}
}
return 0;
return result;
}
int ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx)
int32_t ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx)
{
int32_t ret = 0;
/* sanity check GSC ID */
if (gsc_idx > TEGRA_ARI_GSC_VPR_IDX)
return EINVAL;
/* clean the previous response state */
ari_clobber_response(ari_base);
/*
* The MCE code will read the GSC carveout value, corrseponding to
* the ID, from the MC registers and update the internal GSC registers
* of the CCPLEX.
*/
ari_request_wait(ari_base, 0, TEGRA_ARI_UPDATE_CCPLEX_GSC, gsc_idx, 0);
if (gsc_idx > (uint32_t)TEGRA_ARI_GSC_VPR_IDX) {
ret = EINVAL;
} else {
/* clean the previous response state */
ari_clobber_response(ari_base);
/*
* The MCE code will read the GSC carveout value, corrseponding to
* the ID, from the MC registers and update the internal GSC registers
* of the CCPLEX.
*/
(void)ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CCPLEX_GSC, gsc_idx, 0U);
}
return 0;
return ret;
}
void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx)
......@@ -441,48 +488,55 @@ void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx)
/*
* The MCE will shutdown or restart the entire system
*/
(void)ari_request_wait(ari_base, 0, TEGRA_ARI_MISC_CCPLEX, state_idx, 0);
(void)ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC_CCPLEX, state_idx, 0U);
}
int ari_read_write_uncore_perfmon(uint32_t ari_base,
uncore_perfmon_req_t req, uint64_t *data)
int32_t ari_read_write_uncore_perfmon(uint32_t ari_base, uint64_t req,
uint64_t *data)
{
int ret;
int32_t ret, result;
uint32_t val;
uint8_t req_cmd, req_status;
req_cmd = (uint8_t)(req >> UNCORE_PERFMON_CMD_SHIFT);
/* clean the previous response state */
ari_clobber_response(ari_base);
/* sanity check input parameters */
if (req.perfmon_command.cmd == UNCORE_PERFMON_CMD_READ && !data) {
if ((req_cmd == UNCORE_PERFMON_CMD_READ) && (data == NULL)) {
ERROR("invalid parameters\n");
return EINVAL;
result = EINVAL;
} else {
/*
* For "write" commands get the value that has to be written
* to the uncore perfmon registers
*/
val = (req_cmd == UNCORE_PERFMON_CMD_WRITE) ?
(uint32_t)*data : 0UL;
ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_PERFMON, val,
(uint32_t)req);
if (ret != 0) {
result = ret;
} else {
/* read the command status value */
req_status = (uint8_t)ari_get_response_high(ari_base) &
UNCORE_PERFMON_RESP_STATUS_MASK;
/*
* For "read" commands get the data from the uncore
* perfmon registers
*/
req_status >>= UNCORE_PERFMON_RESP_STATUS_SHIFT;
if ((req_status == 0U) && (req_cmd == UNCORE_PERFMON_CMD_READ)) {
*data = ari_get_response_low(ari_base);
}
result = (int32_t)req_status;
}
}
/*
* For "write" commands get the value that has to be written
* to the uncore perfmon registers
*/
val = (req.perfmon_command.cmd == UNCORE_PERFMON_CMD_WRITE) ?
*data : 0;
ret = ari_request_wait(ari_base, 0, TEGRA_ARI_PERFMON, val, req.data);
if (ret)
return ret;
/* read the command status value */
req.perfmon_status.val = ari_get_response_high(ari_base) &
UNCORE_PERFMON_RESP_STATUS_MASK;
/*
* For "read" commands get the data from the uncore
* perfmon registers
*/
if ((req.perfmon_status.val == 0) && (req.perfmon_command.cmd ==
UNCORE_PERFMON_CMD_READ))
*data = ari_get_response_low(ari_base);
return (int)req.perfmon_status.val;
return result;
}
void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value)
......@@ -494,12 +548,11 @@ void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value)
if ((index > TEGRA_ARI_MISC_CCPLEX_EDBGREQ) ||
((index == TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL) &&
(value > 1))) {
(value > 1U))) {
ERROR("%s: invalid parameters \n", __func__);
return;
} else {
/* clean the previous response state */
ari_clobber_response(ari_base);
(void)ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC_CCPLEX, index, value);
}
/* clean the previous response state */
ari_clobber_response(ari_base);
(void)ari_request_wait(ari_base, 0, TEGRA_ARI_MISC_CCPLEX, index, value);
}
plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
View file @ 6de8b24f
/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -67,7 +67,7 @@ static arch_mce_ops_t ari_mce_ops = {
.misc_ccplex = ari_misc_ccplex
};
typedef struct mce_config {
typedef struct {
uint32_t ari_base;
arch_mce_ops_t *ops;
} mce_config_t;
......@@ -108,9 +108,9 @@ static mce_config_t mce_cfg_table[MCE_ARI_APERTURES_MAX] = {
static uint32_t mce_get_curr_cpu_ari_base(void)
{
uint32_t mpidr = read_mpidr();
int cpuid = mpidr & MPIDR_CPU_MASK;
int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
uint64_t mpidr = read_mpidr();
uint64_t cpuid = mpidr & (uint64_t)MPIDR_CPU_MASK;
uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK;
/*
* T186 has 2 CPU clusters, one with Denver CPUs and the other with
......@@ -119,17 +119,19 @@ static uint32_t mce_get_curr_cpu_ari_base(void)
* struct, we have to convert the Denver CPU ids to the corresponding
* indices in the mce_ops_table array.
*/
if (impl == DENVER_IMPL)
cpuid |= 0x4;
if (impl == DENVER_IMPL) {
cpuid |= 0x4U;
}
return mce_cfg_table[cpuid].ari_base;
}
static arch_mce_ops_t *mce_get_curr_cpu_ops(void)
{
uint32_t mpidr = read_mpidr();
int cpuid = mpidr & MPIDR_CPU_MASK;
int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
uint64_t mpidr = read_mpidr();
uint64_t cpuid = mpidr & (uint64_t)MPIDR_CPU_MASK;
uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) &
(uint64_t)MIDR_IMPL_MASK;
/*
* T186 has 2 CPU clusters, one with Denver CPUs and the other with
......@@ -138,8 +140,9 @@ static arch_mce_ops_t *mce_get_curr_cpu_ops(void)
* struct, we have to convert the Denver CPU ids to the corresponding
* indices in the mce_ops_table array.
*/
if (impl == DENVER_IMPL)
cpuid |= 0x4;
if (impl == DENVER_IMPL) {
cpuid |= 0x4U;
}
return mce_cfg_table[cpuid].ops;
}
......@@ -147,20 +150,16 @@ static arch_mce_ops_t *mce_get_curr_cpu_ops(void)
/*******************************************************************************
* Common handler for all MCE commands
******************************************************************************/
int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
uint64_t arg2)
{
arch_mce_ops_t *ops;
const arch_mce_ops_t *ops;
gp_regs_t *gp_regs = get_gpregs_ctx(cm_get_context(NON_SECURE));
uint32_t cpu_ari_base;
uint64_t ret64 = 0, arg3, arg4, arg5;
int ret = 0;
mca_cmd_t mca_cmd;
uncore_perfmon_req_t req;
cpu_context_t *ctx = cm_get_context(NON_SECURE);
gp_regs_t *gp_regs = get_gpregs_ctx(ctx);
int32_t ret = 0;
assert(ctx);
assert(gp_regs);
assert(gp_regs != NULL);
/* get a pointer to the CPU's arch_mce_ops_t struct */
ops = mce_get_curr_cpu_ops();
......@@ -171,8 +170,9 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
switch (cmd) {
case MCE_CMD_ENTER_CSTATE:
ret = ops->enter_cstate(cpu_ari_base, arg0, arg1);
if (ret < 0)
if (ret < 0) {
ERROR("%s: enter_cstate failed(%d)\n", __func__, ret);
}
break;
......@@ -181,28 +181,30 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
* get the parameters required for the update cstate info
* command
*/
arg3 = read_ctx_reg(gp_regs, CTX_GPREG_X4);
arg4 = read_ctx_reg(gp_regs, CTX_GPREG_X5);
arg5 = read_ctx_reg(gp_regs, CTX_GPREG_X6);
arg3 = read_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X4));
arg4 = read_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X5));
arg5 = read_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X6));
ret = ops->update_cstate_info(cpu_ari_base, (uint32_t)arg0,
(uint32_t)arg1, (uint32_t)arg2, (uint8_t)arg3,
(uint32_t)arg4, (uint8_t)arg5);
if (ret < 0)
if (ret < 0) {
ERROR("%s: update_cstate_info failed(%d)\n",
__func__, ret);
}
write_ctx_reg(gp_regs, CTX_GPREG_X4, 0);
write_ctx_reg(gp_regs, CTX_GPREG_X5, 0);
write_ctx_reg(gp_regs, CTX_GPREG_X6, 0);
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X4), (0));
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X5), (0));
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X6), (0));
break;
case MCE_CMD_UPDATE_CROSSOVER_TIME:
ret = ops->update_crossover_time(cpu_ari_base, arg0, arg1);
if (ret < 0)
if (ret < 0) {
ERROR("%s: update_crossover_time failed(%d)\n",
__func__, ret);
}
break;
......@@ -210,16 +212,17 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
ret64 = ops->read_cstate_stats(cpu_ari_base, arg0);
/* update context to return cstate stats value */
write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64);
write_ctx_reg(gp_regs, CTX_GPREG_X2, ret64);
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (ret64));
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X2), (ret64));
break;
case MCE_CMD_WRITE_CSTATE_STATS:
ret = ops->write_cstate_stats(cpu_ari_base, arg0, arg1);
if (ret < 0)
if (ret < 0) {
ERROR("%s: write_cstate_stats failed(%d)\n",
__func__, ret);
}
break;
......@@ -231,7 +234,8 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
}
/* update context to return CCx status value */
write_ctx_reg(gp_regs, CTX_GPREG_X1, ret);
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1),
(uint64_t)(ret));
break;
......@@ -243,22 +247,26 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
}
/* update context to return SC7 status value */
write_ctx_reg(gp_regs, CTX_GPREG_X1, ret);
write_ctx_reg(gp_regs, CTX_GPREG_X3, ret);
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1),
(uint64_t)(ret));
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X3),
(uint64_t)(ret));
break;
case MCE_CMD_ONLINE_CORE:
ret = ops->online_core(cpu_ari_base, arg0);
if (ret < 0)
if (ret < 0) {
ERROR("%s: online_core failed(%d)\n", __func__, ret);
}
break;
case MCE_CMD_CC3_CTRL:
ret = ops->cc3_ctrl(cpu_ari_base, arg0, arg1, arg2);
if (ret < 0)
if (ret < 0) {
ERROR("%s: cc3_ctrl failed(%d)\n", __func__, ret);
}
break;
......@@ -267,8 +275,10 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
arg0);
/* update context to return if echo'd data matched source */
write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64 == arg0);
write_ctx_reg(gp_regs, CTX_GPREG_X2, ret64 == arg0);
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1),
((ret64 == arg0) ? 1ULL : 0ULL));
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X2),
((ret64 == arg0) ? 1ULL : 0ULL));
break;
......@@ -280,8 +290,10 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
* version = minor(63:32) | major(31:0). Update context
* to return major and minor version number.
*/
write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint32_t)ret64);
write_ctx_reg(gp_regs, CTX_GPREG_X2, (uint32_t)(ret64 >> 32));
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1),
(ret64));
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X2),
(ret64 >> 32ULL));
break;
......@@ -290,50 +302,51 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
TEGRA_ARI_MISC_FEATURE_LEAF_0, arg0);
/* update context to return features value */
write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64);
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (ret64));
break;
case MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
ret = ops->roc_flush_cache_trbits(cpu_ari_base);
if (ret < 0)
if (ret < 0) {
ERROR("%s: flush cache_trbits failed(%d)\n", __func__,
ret);
}
break;
case MCE_CMD_ROC_FLUSH_CACHE:
ret = ops->roc_flush_cache(cpu_ari_base);
if (ret < 0)
if (ret < 0) {
ERROR("%s: flush cache failed(%d)\n", __func__, ret);
}
break;
case MCE_CMD_ROC_CLEAN_CACHE:
ret = ops->roc_clean_cache(cpu_ari_base);
if (ret < 0)
if (ret < 0) {
ERROR("%s: clean cache failed(%d)\n", __func__, ret);
}
break;
case MCE_CMD_ENUM_READ_MCA:
memcpy(&mca_cmd, &arg0, sizeof(arg0));
ret64 = ops->read_write_mca(cpu_ari_base, mca_cmd, &arg1);
ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1);
/* update context to return MCA data/error */
write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64);
write_ctx_reg(gp_regs, CTX_GPREG_X2, arg1);
write_ctx_reg(gp_regs, CTX_GPREG_X3, ret64);
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (ret64));
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X2), (arg1));
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X3), (ret64));
break;
case MCE_CMD_ENUM_WRITE_MCA:
memcpy(&mca_cmd, &arg0, sizeof(arg0));
ret64 = ops->read_write_mca(cpu_ari_base, mca_cmd, &arg1);
ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1);
/* update context to return MCA error */
write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64);
write_ctx_reg(gp_regs, CTX_GPREG_X3, ret64);
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (ret64));
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X3), (ret64));
break;
......@@ -357,11 +370,10 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
#endif
case MCE_CMD_UNCORE_PERFMON_REQ:
memcpy(&req, &arg0, sizeof(arg0));
ret = ops->read_write_uncore_perfmon(cpu_ari_base, req, &arg1);
ret = ops->read_write_uncore_perfmon(cpu_ari_base, arg0, &arg1);
/* update context to return data */
write_ctx_reg(gp_regs, CTX_GPREG_X1, arg1);
write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (arg1));
break;
case MCE_CMD_MISC_CCPLEX:
......@@ -370,8 +382,9 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
break;
default:
ERROR("unknown MCE command (%d)\n", cmd);
return EINVAL;
ERROR("unknown MCE command (%lu)\n", cmd);
ret = EINVAL;
break;
}
return ret;
......@@ -380,18 +393,18 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
/*******************************************************************************
* Handler to update the reset vector for CPUs
******************************************************************************/
int mce_update_reset_vector(void)
int32_t mce_update_reset_vector(void)
{
arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
const arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
ops->update_reset_vector(mce_get_curr_cpu_ari_base());
return 0;
}
static int mce_update_ccplex_gsc(tegra_ari_gsc_index_t gsc_idx)
static int32_t mce_update_ccplex_gsc(tegra_ari_gsc_index_t gsc_idx)
{
arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
const arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
ops->update_ccplex_gsc(mce_get_curr_cpu_ari_base(), gsc_idx);
......@@ -401,7 +414,7 @@ static int mce_update_ccplex_gsc(tegra_ari_gsc_index_t gsc_idx)
/*******************************************************************************
* Handler to update carveout values for Video Memory Carveout region
******************************************************************************/
int mce_update_gsc_videomem(void)
int32_t mce_update_gsc_videomem(void)
{
return mce_update_ccplex_gsc(TEGRA_ARI_GSC_VPR_IDX);
}
......@@ -409,7 +422,7 @@ int mce_update_gsc_videomem(void)
/*******************************************************************************
* Handler to update carveout values for TZDRAM aperture
******************************************************************************/
int mce_update_gsc_tzdram(void)
int32_t mce_update_gsc_tzdram(void)
{
return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZ_DRAM_IDX);
}
......@@ -417,7 +430,7 @@ int mce_update_gsc_tzdram(void)
/*******************************************************************************
* Handler to update carveout values for TZ SysRAM aperture
******************************************************************************/
int mce_update_gsc_tzram(void)
int32_t mce_update_gsc_tzram(void)
{
return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZRAM);
}
......@@ -427,28 +440,29 @@ int mce_update_gsc_tzram(void)
******************************************************************************/
__dead2 void mce_enter_ccplex_state(uint32_t state_idx)
{
arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
const arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
/* sanity check state value */
if (state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF &&
state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT)
if ((state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) &&
(state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT)) {
panic();
}
ops->enter_ccplex_state(mce_get_curr_cpu_ari_base(), state_idx);
/* wait till the CCPLEX powers down */
for (;;)
for (;;) {
;
}
panic();
}
/*******************************************************************************
* Handler to issue the UPDATE_CSTATE_INFO request
******************************************************************************/
void mce_update_cstate_info(mce_cstate_info_t *cstate)
void mce_update_cstate_info(const mce_cstate_info_t *cstate)
{
arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
const arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
/* issue the UPDATE_CSTATE_INFO request */
ops->update_cstate_info(mce_get_curr_cpu_ari_base(), cstate->cluster,
......@@ -462,7 +476,7 @@ void mce_update_cstate_info(mce_cstate_info_t *cstate)
******************************************************************************/
void mce_verify_firmware_version(void)
{
arch_mce_ops_t *ops;
const arch_mce_ops_t *ops;
uint32_t cpu_ari_base;
uint64_t version;
uint32_t major, minor;
......@@ -470,37 +484,40 @@ void mce_verify_firmware_version(void)
/*
* MCE firmware is not supported on simulation platforms.
*/
if (tegra_platform_is_emulation())
return;
if (tegra_platform_is_emulation()) {
/* get a pointer to the CPU's arch_mce_ops_t struct */
ops = mce_get_curr_cpu_ops();
INFO("MCE firmware is not supported\n");
/* get the CPU's ARI base address */
cpu_ari_base = mce_get_curr_cpu_ari_base();
} else {
/* get a pointer to the CPU's arch_mce_ops_t struct */
ops = mce_get_curr_cpu_ops();
/*
* Read the MCE firmware version and extract the major and minor
* version fields
*/
version = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_VERSION, 0);
major = (uint32_t)version;
minor = (uint32_t)(version >> 32);
/* get the CPU's ARI base address */
cpu_ari_base = mce_get_curr_cpu_ari_base();
INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor,
TEGRA_ARI_VERSION_MAJOR, TEGRA_ARI_VERSION_MINOR);
/*
* Read the MCE firmware version and extract the major and minor
* version fields
*/
version = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_VERSION, 0);
major = (uint32_t)version;
minor = (uint32_t)(version >> 32);
/*
* Verify that the MCE firmware version and the interface header
* match
*/
if (major != TEGRA_ARI_VERSION_MAJOR) {
ERROR("ARI major version mismatch\n");
panic();
}
INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor,
TEGRA_ARI_VERSION_MAJOR, TEGRA_ARI_VERSION_MINOR);
if (minor < TEGRA_ARI_VERSION_MINOR) {
ERROR("ARI minor version mismatch\n");
panic();
/*
* Verify that the MCE firmware version and the interface header
* match
*/
if (major != TEGRA_ARI_VERSION_MAJOR) {
ERROR("ARI major version mismatch\n");
panic();
}
if (minor < TEGRA_ARI_VERSION_MINOR) {
ERROR("ARI minor version mismatch\n");
panic();
}
}
}
plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
View file @ 6de8b24f
/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -13,57 +13,63 @@
#include <sys/errno.h>
#include <t18x_ari.h>
extern void nvg_set_request_data(uint64_t req, uint64_t data);
extern void nvg_set_request(uint64_t req);
extern uint64_t nvg_get_result(void);
int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time)
int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time)
{
int32_t ret = 0;
(void)ari_base;
/* check for allowed power state */
if (state != TEGRA_ARI_CORE_C0 && state != TEGRA_ARI_CORE_C1 &&
state != TEGRA_ARI_CORE_C6 && state != TEGRA_ARI_CORE_C7) {
if ((state != TEGRA_ARI_CORE_C0) && (state != TEGRA_ARI_CORE_C1) &&
(state != TEGRA_ARI_CORE_C6) && (state != TEGRA_ARI_CORE_C7)) {
ERROR("%s: unknown cstate (%d)\n", __func__, state);
return EINVAL;
}
/* time (TSC ticks) until the core is expected to get a wake event */
nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, wake_time);
ret = EINVAL;
} else {
/* time (TSC ticks) until the core is expected to get a wake event */
nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, wake_time);
/* set the core cstate */
write_actlr_el1(state);
/* set the core cstate */
write_actlr_el1(state);
}
return 0;
return ret;
}
/*
* This request allows updating of CLUSTER_CSTATE, CCPLEX_CSTATE and
* SYSTEM_CSTATE values.
*/
int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
uint32_t system, uint8_t sys_state_force, uint32_t wake_mask,
uint8_t update_wake_mask)
{
uint64_t val = 0;
uint64_t val = 0ULL;
(void)ari_base;
/* update CLUSTER_CSTATE? */
if (cluster)
val |= (cluster & CLUSTER_CSTATE_MASK) |
if (cluster != 0U) {
val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) |
CLUSTER_CSTATE_UPDATE_BIT;
}
/* update CCPLEX_CSTATE? */
if (ccplex)
val |= (ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT |
if (ccplex != 0U) {
val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) |
CCPLEX_CSTATE_UPDATE_BIT;
}
/* update SYSTEM_CSTATE? */
if (system)
val |= ((system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) |
((sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) |
if (system != 0U) {
val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) |
(((uint64_t)sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) |
SYSTEM_CSTATE_UPDATE_BIT);
}
/* update wake mask value? */
if (update_wake_mask)
if (update_wake_mask != 0U) {
val |= CSTATE_WAKE_MASK_UPDATE_BIT;
}
/* set the wake mask */
val &= CSTATE_WAKE_MASK_CLEAR;
......@@ -75,46 +81,60 @@ int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
return 0;
}
int nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time)
int32_t nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time)
{
/* sanity check crossover type */
if (type > TEGRA_ARI_CROSSOVER_CCP3_SC1)
return EINVAL;
int32_t ret = 0;
/*
* The crossover threshold limit types start from
* TEGRA_CROSSOVER_TYPE_C1_C6 to TEGRA_CROSSOVER_TYPE_CCP3_SC7. The
* command indices for updating the threshold can be generated
* by adding the type to the NVG_SET_THRESHOLD_CROSSOVER_C1_C6
* command index.
*/
nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 + type,
(uint64_t)time);
(void)ari_base;
return 0;
/* sanity check crossover type */
if (type > TEGRA_ARI_CROSSOVER_CCP3_SC1) {
ret = EINVAL;
} else {
/*
* The crossover threshold limit types start from
* TEGRA_CROSSOVER_TYPE_C1_C6 to TEGRA_CROSSOVER_TYPE_CCP3_SC7.
* The command indices for updating the threshold be generated
* by adding the type to the NVG_SET_THRESHOLD_CROSSOVER_C1_C6
* command index.
*/
nvg_set_request_data((TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 +
(uint64_t)type), (uint64_t)time);
}
return ret;
}
uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state)
{
/* sanity check state */
if (state == 0)
return EINVAL;
uint64_t ret;
/*
* The cstate types start from NVG_READ_CSTATE_STATS_SC7_ENTRIES
* to NVG_GET_LAST_CSTATE_ENTRY_A57_3. The command indices for
* reading the threshold can be generated by adding the type to
* the NVG_CLEAR_CSTATE_STATS command index.
*/
nvg_set_request(TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + state);
(void)ari_base;
return (int64_t)nvg_get_result();
/* sanity check state */
if (state == 0U) {
ret = EINVAL;
} else {
/*
* The cstate types start from NVG_READ_CSTATE_STATS_SC7_ENTRIES
* to NVG_GET_LAST_CSTATE_ENTRY_A57_3. The command indices for
* reading the threshold can be generated by adding the type to
* the NVG_CLEAR_CSTATE_STATS command index.
*/
nvg_set_request((TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR +
(uint64_t)state));
ret = nvg_get_result();
}
return ret;
}
int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats)
int32_t nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats)
{
uint64_t val;
(void)ari_base;
/*
* The only difference between a CSTATE_STATS_WRITE and
* CSTATE_STATS_READ is the usage of the 63:32 in the request.
......@@ -129,71 +149,88 @@ int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats)
* reading the threshold can be generated by adding the type to
* the NVG_CLEAR_CSTATE_STATS command index.
*/
nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + state, val);
nvg_set_request_data((TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR +
(uint64_t)state), val);
return 0;
}
int nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time)
int32_t nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time)
{
(void)ari_base;
(void)state;
(void)wake_time;
/* This does not apply to the Denver cluster */
return 0;
}
int nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time)
int32_t nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time)
{
uint64_t val;
int32_t ret;
(void)ari_base;
/* check for allowed power state */
if (state != TEGRA_ARI_CORE_C0 && state != TEGRA_ARI_CORE_C1 &&
state != TEGRA_ARI_CORE_C6 && state != TEGRA_ARI_CORE_C7) {
if ((state != TEGRA_ARI_CORE_C0) && (state != TEGRA_ARI_CORE_C1) &&
(state != TEGRA_ARI_CORE_C6) && (state != TEGRA_ARI_CORE_C7)) {
ERROR("%s: unknown cstate (%d)\n", __func__, state);
return EINVAL;
ret = EINVAL;
} else {
/*
* Request format -
* 63:32 = wake time
* 31:0 = C-state for this core
*/
val = ((uint64_t)wake_time << MCE_SC7_WAKE_TIME_SHIFT) |
((uint64_t)state & MCE_SC7_ALLOWED_MASK);
/* issue command to check if SC7 is allowed */
nvg_set_request_data(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED, val);
/* 1 = SC7 allowed, 0 = SC7 not allowed */
ret = (nvg_get_result() != 0ULL) ? 1 : 0;
}
/*
* Request format -
* 63:32 = wake time
* 31:0 = C-state for this core
*/
val = ((uint64_t)wake_time << MCE_SC7_WAKE_TIME_SHIFT) |
(state & MCE_SC7_ALLOWED_MASK);
/* issue command to check if SC7 is allowed */
nvg_set_request_data(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED, val);
/* 1 = SC7 allowed, 0 = SC7 not allowed */
return !!nvg_get_result();
return ret;
}
int nvg_online_core(uint32_t ari_base, uint32_t core)
int32_t nvg_online_core(uint32_t ari_base, uint32_t core)
{
int cpu = read_mpidr() & MPIDR_CPU_MASK;
int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
uint64_t cpu = read_mpidr() & (uint64_t)MPIDR_CPU_MASK;
uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) &
(uint64_t)MIDR_IMPL_MASK;
int32_t ret = 0;
(void)ari_base;
/* sanity check code id */
if ((core >= MCE_CORE_ID_MAX) || (cpu == core)) {
if ((core >= (uint32_t)MCE_CORE_ID_MAX) || (cpu == core)) {
ERROR("%s: unsupported core id (%d)\n", __func__, core);
return EINVAL;
ret = EINVAL;
} else {
/*
* The Denver cluster has 2 CPUs only - 0, 1.
*/
if ((impl == DENVER_IMPL) && ((core == 2U) || (core == 3U))) {
ERROR("%s: unknown core id (%d)\n", __func__, core);
ret = EINVAL;
} else {
/* get a core online */
nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE,
((uint64_t)core & MCE_CORE_ID_MASK));
}
}
/*
* The Denver cluster has 2 CPUs only - 0, 1.
*/
if (impl == DENVER_IMPL && ((core == 2) || (core == 3))) {
ERROR("%s: unknown core id (%d)\n", __func__, core);
return EINVAL;
}
/* get a core online */
nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE, core & MCE_CORE_ID_MASK);
return 0;
return ret;
}
int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable)
int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable)
{
int val;
uint32_t val;
(void)ari_base;
/*
* If the enable bit is cleared, Auto-CC3 will be disabled by setting
......@@ -207,9 +244,9 @@ int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable
*/
val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\
((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\
(enable ? MCE_AUTO_CC3_ENABLE_BIT : 0));
((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U));
nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, val);
nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, (uint64_t)val);
return 0;
}
plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
View file @ 6de8b24f
......@@ -256,8 +256,8 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
int tegra_soc_pwr_domain_on(u_register_t mpidr)
{
int target_cpu = mpidr & MPIDR_CPU_MASK;
int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >>
uint32_t target_cpu = mpidr & MPIDR_CPU_MASK;
uint32_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >>
MPIDR_AFFINITY_BITS;
if (target_cluster > MPIDR_AFFLVL1) {
......
plat/nvidia/tegra/soc/t186/plat_setup.c
View file @ 6de8b24f
......@@ -22,7 +22,7 @@
#include <tegra_private.h>
#include <xlat_tables.h>
DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1)
extern uint64_t tegra_enable_l2_ecc_parity_prot;
/*******************************************************************************
......@@ -172,7 +172,7 @@ void plat_early_platform_setup(void)
if (val >= TEGRA186_VER_A02P) {
val = read_l2ctlr_el1();
val |= L2_ECC_PARITY_PROTECTION_BIT;
val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
write_l2ctlr_el1(val);
/*
......
plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
View file @ 6de8b24f
......@@ -60,7 +60,7 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
/*
* System powerdown request only for afflvl 2
*/
for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] =
......
plat/rockchip/common/aarch64/plat_helpers.S
View file @ 6de8b24f
......@@ -43,9 +43,9 @@ handler_a72:
* Set the L2 Data RAM latency for Cortex-A72.
* Set the L2 Tag RAM latency to for Cortex-A72.
*/
mov x0, #((5 << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
mov x0, #((5 << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
(0x1 << 5))
msr L2CTLR_EL1, x0
msr CORTEX_A72_L2CTLR_EL1, x0
isb
handler_end:
ret
......
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