diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
index 3ac5333a042d327e690060d3540de61337c82ec2..415dc0f89a79f771e2f26f90c362455e7c021488 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
@@ -75,5 +75,8 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
 void nvg_set_request_data(uint64_t req, uint64_t data);
 void nvg_set_request(uint64_t req);
 uint64_t nvg_get_result(void);
+uint64_t nvg_cache_clean(void);
+uint64_t nvg_cache_clean_inval(void);
+uint64_t nvg_cache_inval_all(void);
 
 #endif /* __MCE_PRIVATE_H__ */
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S b/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S
index e6a6a998020cb5f55d9d19832273b59d6c4e165c..3c47208a10229104e74a7e5992a0fd13036fff95 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S
@@ -10,6 +10,9 @@
 	.globl	nvg_set_request_data
 	.globl	nvg_set_request
 	.globl	nvg_get_result
+	.globl	nvg_cache_clean
+	.globl	nvg_cache_clean_inval
+	.globl	nvg_cache_inval_all
 
 /* void nvg_set_request_data(uint64_t req, uint64_t data) */
 func nvg_set_request_data
@@ -29,3 +32,21 @@ func nvg_get_result
 	mrs	x0, s3_0_c15_c1_3
 	ret
 endfunc nvg_get_result
+
+/* uint64_t nvg_cache_clean(void) */
+func nvg_cache_clean
+	mrs	x0, s3_0_c15_c3_5
+	ret
+endfunc nvg_cache_clean
+
+/* uint64_t nvg_cache_clean_inval(void) */
+func nvg_cache_clean_inval
+	mrs	x0, s3_0_c15_c3_6
+	ret
+endfunc nvg_cache_clean_inval
+
+/* uint64_t nvg_cache_inval_all(void) */
+func nvg_cache_inval_all
+	mrs	x0, s3_0_c15_c3_7
+	ret
+endfunc nvg_cache_inval_all
\ No newline at end of file
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
index c7f6591866fbe5bf5dba5311ad88c9fc6daaecf9..2eba1d33e027346d4af6770383a733ce59684438 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
@@ -15,10 +15,8 @@
 #include <t194_nvg.h>
 #include <tegra_private.h>
 
-extern void nvg_set_request_data(uint64_t req, uint64_t data);
-extern void nvg_set_request(uint64_t req);
-extern uint64_t nvg_get_result(void);
-
+#define	ID_AFR0_EL1_CACHE_OPS_SHIFT	12
+#define	ID_AFR0_EL1_CACHE_OPS_MASK	0xFU
 /*
  * Reports the major and minor version of this interface.
  *
@@ -306,41 +304,62 @@ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx)
 
 /*
  * Cache clean operation for all CCPLEX caches.
- *
- * NVGDATA[0] cache_clean
  */
 int32_t nvg_roc_clean_cache(void)
 {
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
-							(uint64_t)CACHE_CLEAN_SET);
+	int32_t ret = 0;
 
-	return 0;
+	/* check if cache flush through mts is supported */
+	if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
+			ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
+		if (nvg_cache_clean() == 0U) {
+			ERROR("%s: failed\n", __func__);
+			ret = EINVAL;
+		}
+	} else {
+		ret = EINVAL;
+	}
+	return ret;
 }
 
 /*
  * Cache clean and invalidate operation for all CCPLEX caches.
- *
- * NVGDATA[1] cache_clean_inval
  */
 int32_t nvg_roc_flush_cache(void)
 {
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
-							(uint64_t)CACHE_CLEAN_INVAL_SET);
+	int32_t ret = 0;
 
-	return 0;
+	/* check if cache flush through mts is supported */
+	if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
+			ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
+		if (nvg_cache_clean_inval() == 0U) {
+			ERROR("%s: failed\n", __func__);
+			ret = EINVAL;
+		}
+	} else {
+		ret = EINVAL;
+	}
+	return ret;
 }
 
 /*
  * Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches.
- *
- * NVGDATA[2] cache_clean_inval_tr
  */
 int32_t nvg_roc_clean_cache_trbits(void)
 {
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
-							(uint64_t)CACHE_CLEAN_INVAL_TR_SET);
+	int32_t ret = 0;
 
-	return 0;
+	/* check if cache flush through mts is supported */
+	if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
+			ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
+		if (nvg_cache_inval_all() == 0U) {
+			ERROR("%s: failed\n", __func__);
+			ret = EINVAL;
+		}
+	} else {
+		ret = EINVAL;
+	}
+	return ret;
 }
 
 /*