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Commit 7479a33f authored by Marek Vasut's avatar Marek Vasut
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rcar_gen3: drivers: qos: H3: Drop MD pin check 



The DBSC_SCFCTST2 is always written with the same value, no matter
what the MD pin value is, drop the entire check and just write the
register with the one and only possible value.
Signed-off-by: default avatarMarek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I4d8926eb3c44c61ec777c05c581ce8247f13daa6
parent 1a9eb1ed
Show whitespace changes
Inline Side-by-side
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
View file @ 7479a33f
...@@ -20,8 +20,6 @@ ...@@ -20,8 +20,6 @@
static void dbsc_setting(void) static void dbsc_setting(void)
{ {
uint32_t md = 0;
/* BUFCAM settings */ /* BUFCAM settings */
/* DBSC_DBCAM0CNF0 not set */ /* DBSC_DBCAM0CNF0 not set */
io_write_32(DBSC_DBCAM0CNF1, 0x00044218); io_write_32(DBSC_DBCAM0CNF1, 0x00044218);
...@@ -32,26 +30,8 @@ static void dbsc_setting(void) ...@@ -32,26 +30,8 @@ static void dbsc_setting(void)
io_write_32(DBSC_DBSCHSZ0, 0x00000001); io_write_32(DBSC_DBSCHSZ0, 0x00000001);
io_write_32(DBSC_DBSCHRW0, 0x22421111); io_write_32(DBSC_DBSCHRW0, 0x22421111);
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17; /* DDR3 */
switch (md) {
case 0x0:
/* DDR3200 */
io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
/* DDR2800 */
io_write_32(DBSC_SCFCTST2, 0x012F1123); io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
/* DDR2400 */
io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
/* DDR1600 */
io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
}
/* QoS Settings */ /* QoS Settings */
io_write_32(DBSC_DBSCHQOS00, 0x0000F000); io_write_32(DBSC_DBSCHQOS00, 0x0000F000);
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
View file @ 7479a33f
...@@ -57,8 +57,6 @@ ...@@ -57,8 +57,6 @@
static void dbsc_setting(void) static void dbsc_setting(void)
{ {
uint32_t md = 0;
/* Register write enable */ /* Register write enable */
io_write_32(DBSC_DBSYSCNT0, 0x00001234U); io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
...@@ -70,26 +68,8 @@ static void dbsc_setting(void) ...@@ -70,26 +68,8 @@ static void dbsc_setting(void)
io_write_32(DBSC_DBSCHSZ0, 0x00000001U); io_write_32(DBSC_DBSCHSZ0, 0x00000001U);
io_write_32(DBSC_DBSCHRW0, 0x22421111U); io_write_32(DBSC_DBSCHRW0, 0x22421111U);
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17; /* DDR3 */
switch (md) {
case 0x0:
/* DDR3200 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
/* DDR2800 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U); io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
/* DDR2400 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
/* DDR1600 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
}
/* QoS Settings */ /* QoS Settings */
io_write_32(DBSC_DBSCHQOS00, 0x00000F00U); io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
View file @ 7479a33f
...@@ -57,8 +57,6 @@ ...@@ -57,8 +57,6 @@
static void dbsc_setting(void) static void dbsc_setting(void)
{ {
uint32_t md = 0;
/* Register write enable */ /* Register write enable */
io_write_32(DBSC_DBSYSCNT0, 0x00001234U); io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
...@@ -70,26 +68,8 @@ static void dbsc_setting(void) ...@@ -70,26 +68,8 @@ static void dbsc_setting(void)
io_write_32(DBSC_DBSCHSZ0, 0x00000001U); io_write_32(DBSC_DBSCHSZ0, 0x00000001U);
io_write_32(DBSC_DBSCHRW0, 0x22421111U); io_write_32(DBSC_DBSCHRW0, 0x22421111U);
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17; /* DDR3 */
switch (md) {
case 0x0:
/* DDR3200 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
/* DDR2800 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U); io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
/* DDR2400 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
/* DDR1600 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
}
/* QoS Settings */ /* QoS Settings */
io_write_32(DBSC_DBSCHQOS00, 0x00000F00U); io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
View file @ 7479a33f
...@@ -57,8 +57,6 @@ ...@@ -57,8 +57,6 @@
static void dbsc_setting(void) static void dbsc_setting(void)
{ {
uint32_t md = 0;
/* Register write enable */ /* Register write enable */
io_write_32(DBSC_DBSYSCNT0, 0x00001234U); io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
...@@ -70,26 +68,8 @@ static void dbsc_setting(void) ...@@ -70,26 +68,8 @@ static void dbsc_setting(void)
io_write_32(DBSC_DBSCHSZ0, 0x00000001U); io_write_32(DBSC_DBSCHSZ0, 0x00000001U);
io_write_32(DBSC_DBSCHRW0, 0x22421111U); io_write_32(DBSC_DBSCHRW0, 0x22421111U);
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17; /* DDR3 */
switch (md) {
case 0x0:
/* DDR3200 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
/* DDR2800 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U); io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
/* DDR2400 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
/* DDR1600 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
}
/* QoS Settings */ /* QoS Settings */
io_write_32(DBSC_DBSCHQOS00, 0x00000F00U); io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
......
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