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Commit 7704ff91 authored by Toshiyuki Ogasahara's avatar Toshiyuki Ogasahara Committed by Marek Vasut
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rcar_gen3: drivers: Change to restore timer counter value at resume 



Changed to save and restore cntpct_el0 using memory mapped
register for generic timer when System Suspend and Resume.

Reported by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Signed-off-by: default avatarToshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: default avatarYoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I40fd9f5434c4d52b320cd1d20322b9b8e4e67155
parent 4983f8b6
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drivers/renesas/rcar/console/rcar_printf.c
View file @ 7704ff91
/* /*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -94,9 +94,6 @@ int32_t rcar_log_init(void) ...@@ -94,9 +94,6 @@ int32_t rcar_log_init(void)
sizeof(t_log->header.head)); sizeof(t_log->header.head));
t_log->header.index = 0U; t_log->header.index = 0U;
t_log->header.size = 0U; t_log->header.size = 0U;
#ifndef IMAGE_BL2
rcar_stack_generic_timer[INDEX_TIMER_COUNT] = 0U;
#endif
} }
rcar_lock_init(); rcar_lock_init();
......
drivers/renesas/rcar/console/rcar_printf.h
View file @ 7704ff91
/* /*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -12,8 +12,4 @@ ...@@ -12,8 +12,4 @@
int32_t rcar_set_log_data(int32_t c); int32_t rcar_set_log_data(int32_t c);
int32_t rcar_log_init(void); int32_t rcar_log_init(void);
#if IMAGE_BL31
extern uint64_t rcar_stack_generic_timer[5];
#endif
#endif /* RCAR_PRINTF_H */ #endif /* RCAR_PRINTF_H */
drivers/renesas/rcar/pwrc/call_sram.S
View file @ 7704ff91
/* /*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <arch.h> #include <arch.h>
#include <asm_macros.S> #include <asm_macros.S>
#include "rcar_def.h"
.global rcar_pwrc_switch_stack .global rcar_pwrc_switch_stack
.global rcar_pwrc_save_generic_timer
.global rcar_pwrc_restore_generic_timer
#define OFFSET_SP_X9_X10 (0x00)
#define OFFSET_CNTFID0 (0x10)
#define OFFSET_CNTPCT_EL0 (0x18)
#define OFFSET_TIMER_COUNT (0x20)
/* /*
* x0 : jump address, * x0 : jump address,
...@@ -54,37 +46,3 @@ func rcar_pwrc_switch_stack ...@@ -54,37 +46,3 @@ func rcar_pwrc_switch_stack
ldp x29, x30, [sp,#-16] ldp x29, x30, [sp,#-16]
ret ret
endfunc rcar_pwrc_switch_stack endfunc rcar_pwrc_switch_stack
/* x0 : stack pointer base address */
func rcar_pwrc_save_generic_timer
stp x9, x10, [x0, #OFFSET_SP_X9_X10]
/* save CNTFID0 and cntpct_el0 */
mov_imm x10, (RCAR_CNTC_BASE + CNTFID_OFF)
ldr x9, [x10]
mrs x10, cntpct_el0
stp x9, x10, [x0, #OFFSET_CNTFID0]
ldp x9, x10, [x0, #OFFSET_SP_X9_X10]
ret
endfunc rcar_pwrc_save_generic_timer
/* x0 : Stack pointer base address */
func rcar_pwrc_restore_generic_timer
stp x9, x10, [x0, #OFFSET_SP_X9_X10]
/* restore CNTFID0 and cntpct_el0 */
ldr x10, [x0, #OFFSET_CNTFID0]
mov_imm x9, (RCAR_CNTC_BASE + CNTFID_OFF)
str x10, [x9]
ldp x9, x10, [x0, #OFFSET_CNTPCT_EL0]
add x9, x9, x10
str x9, [x0, #OFFSET_TIMER_COUNT]
ldp x9, x10, [x0, #OFFSET_SP_X9_X10]
ret
endfunc rcar_pwrc_restore_generic_timer
drivers/renesas/rcar/pwrc/pwrc.c
View file @ 7704ff91
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#include <lib/bakery_lock.h> #include <lib/bakery_lock.h>
#include <lib/mmio.h> #include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h> #include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include "iic_dvfs.h" #include "iic_dvfs.h"
#include "rcar_def.h" #include "rcar_def.h"
...@@ -126,6 +127,14 @@ RCAR_INSTANTIATE_LOCK ...@@ -126,6 +127,14 @@ RCAR_INSTANTIATE_LOCK
#define RST_MODEMR (RST_BASE + 0x0060U) #define RST_MODEMR (RST_BASE + 0x0060U)
#define RST_MODEMR_BIT0 (0x00000001U) #define RST_MODEMR_BIT0 (0x00000001U)
#define RCAR_CNTCR_OFF (0x00U)
#define RCAR_CNTCVL_OFF (0x08U)
#define RCAR_CNTCVU_OFF (0x0CU)
#define RCAR_CNTFID_OFF (0x20U)
#define RCAR_CNTCR_EN ((uint32_t)1U << 0U)
#define RCAR_CNTCR_FCREQ(x) ((uint32_t)(x) << 8U)
#if PMIC_ROHM_BD9571 #if PMIC_ROHM_BD9571
#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4)) #define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
#define PMIC_BKUP_MODE_CNT (0x20U) #define PMIC_BKUP_MODE_CNT (0x20U)
...@@ -323,6 +332,39 @@ done: ...@@ -323,6 +332,39 @@ done:
rcar_lock_release(); rcar_lock_release();
} }
static uint64_t rcar_pwrc_saved_cntpct_el0;
static uint32_t rcar_pwrc_saved_cntfid;
#if RCAR_SYSTEM_SUSPEND
static void rcar_pwrc_save_timer_state(void)
{
rcar_pwrc_saved_cntpct_el0 = read_cntpct_el0();
rcar_pwrc_saved_cntfid =
mmio_read_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF));
}
#endif
void rcar_pwrc_restore_timer_state(void)
{
/* Stop timer before restoring counter value */
mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCR_OFF), 0U);
mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCVL_OFF),
(uint32_t)(rcar_pwrc_saved_cntpct_el0 & 0xFFFFFFFFU));
mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCVU_OFF),
(uint32_t)(rcar_pwrc_saved_cntpct_el0 >> 32U));
mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF),
rcar_pwrc_saved_cntfid);
/* Start generic timer back */
write_cntfrq_el0((u_register_t)plat_get_syscnt_freq2());
mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCR_OFF),
(RCAR_CNTCR_FCREQ(0U) | RCAR_CNTCR_EN));
}
#if !PMIC_ROHM_BD9571 #if !PMIC_ROHM_BD9571
void rcar_pwrc_system_reset(void) void rcar_pwrc_system_reset(void)
{ {
...@@ -640,7 +682,7 @@ void rcar_pwrc_set_suspend_to_ram(void) ...@@ -640,7 +682,7 @@ void rcar_pwrc_set_suspend_to_ram(void)
DEVICE_SRAM_STACK_SIZE); DEVICE_SRAM_STACK_SIZE);
uint32_t sctlr; uint32_t sctlr;
rcar_pwrc_save_generic_timer(rcar_stack_generic_timer); rcar_pwrc_save_timer_state();
/* disable MMU */ /* disable MMU */
sctlr = (uint32_t) read_sctlr_el3(); sctlr = (uint32_t) read_sctlr_el3();
......
drivers/renesas/rcar/pwrc/pwrc.h
View file @ 7704ff91
/* /*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -52,6 +52,7 @@ uint32_t rcar_pwrc_status(uint64_t mpidr); ...@@ -52,6 +52,7 @@ uint32_t rcar_pwrc_status(uint64_t mpidr);
uint32_t rcar_pwrc_get_cluster(void); uint32_t rcar_pwrc_get_cluster(void);
uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr); uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr);
uint32_t rcar_pwrc_get_cpu_num(uint32_t cluster_type); uint32_t rcar_pwrc_get_cpu_num(uint32_t cluster_type);
void rcar_pwrc_restore_timer_state(void);
void plat_secondary_reset(void); void plat_secondary_reset(void);
void rcar_pwrc_code_copy_to_system_ram(void); void rcar_pwrc_code_copy_to_system_ram(void);
...@@ -67,12 +68,8 @@ void rcar_pwrc_init_suspend_to_ram(void); ...@@ -67,12 +68,8 @@ void rcar_pwrc_init_suspend_to_ram(void);
void rcar_pwrc_suspend_to_ram(void); void rcar_pwrc_suspend_to_ram(void);
#endif #endif
extern void rcar_pwrc_save_generic_timer(uint64_t *rcar_stack_generic_timer);
extern uint32_t rcar_pwrc_switch_stack(uintptr_t jump, uintptr_t stack, extern uint32_t rcar_pwrc_switch_stack(uintptr_t jump, uintptr_t stack,
void *arg); void *arg);
extern uint64_t rcar_stack_generic_timer[5];
#endif #endif
#endif /* PWRC_H */ #endif /* PWRC_H */
plat/renesas/rcar/plat_pm.c
View file @ 7704ff91
/* /*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -35,8 +35,6 @@ ...@@ -35,8 +35,6 @@
#define CLUSTER_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL1]) #define CLUSTER_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL1])
#define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0]) #define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0])
uint64_t rcar_stack_generic_timer[5] __attribute__ ((section("data")));
extern void rcar_pwrc_restore_generic_timer(uint64_t *stack); extern void rcar_pwrc_restore_generic_timer(uint64_t *stack);
extern void plat_rcar_gic_driver_init(void); extern void plat_rcar_gic_driver_init(void);
extern void plat_rcar_gic_init(void); extern void plat_rcar_gic_init(void);
...@@ -150,11 +148,7 @@ static void rcar_pwr_domain_suspend_finish(const psci_power_state_t ...@@ -150,11 +148,7 @@ static void rcar_pwr_domain_suspend_finish(const psci_power_state_t
if (cluster_type == RCAR_CLUSTER_A53A57) if (cluster_type == RCAR_CLUSTER_A53A57)
plat_cci_init(); plat_cci_init();
rcar_pwrc_restore_generic_timer(rcar_stack_generic_timer); rcar_pwrc_restore_timer_state();
/* start generic timer */
write_cntfrq_el0(plat_get_syscnt_freq2());
mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(U(0)) | CNTCR_EN);
rcar_pwrc_setup(); rcar_pwrc_setup();
rcar_pwrc_code_copy_to_system_ram(); rcar_pwrc_code_copy_to_system_ram();
......
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