Skip to content

GitLab

Unverified Commit 7825d719 authored by Antonio Niño Díaz's avatar Antonio Niño Díaz Committed by GitHub
Browse files

Merge pull request #1734 from marex/arm/master/update-rcar-2.0.0 

Arm/master/update rcar 2.0.0
parents c8719032 e68d2146
Hide whitespace changes
Inline Side-by-side
drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
View file @ 7825d719
......@@ -821,7 +821,8 @@ void pfc_init_m3n(void)
| MOD_SEL0_DRIF2_A
| MOD_SEL0_DRIF1_A
| MOD_SEL0_DRIF0_A
| MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A_A);
| MOD_SEL0_CANFD0_A
| MOD_SEL0_ADG_A_A);
pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
| MOD_SEL1_TSIF0_A
| MOD_SEL1_TIMER_TMU_A
......@@ -841,7 +842,9 @@ void pfc_init_m3n(void)
| MOD_SEL1_PWM6_A
| MOD_SEL1_PWM5_A
| MOD_SEL1_PWM4_A
| MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
| MOD_SEL1_PWM3_A
| MOD_SEL1_PWM2_A
| MOD_SEL1_PWM1_A);
pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
| MOD_SEL2_I2C_3_A
| MOD_SEL2_I2C_0_A
......@@ -852,7 +855,9 @@ void pfc_init_m3n(void)
| MOD_SEL2_SSI2_A
| MOD_SEL2_SSI9_A
| MOD_SEL2_TIMER_TMU2_A
| MOD_SEL2_ADG_B_A | MOD_SEL2_ADG_C_A | MOD_SEL2_VIN4_A);
| MOD_SEL2_ADG_B_A
| MOD_SEL2_ADG_C_A
| MOD_SEL2_VIN4_A);
/* initialize peripheral function select */
pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
......@@ -1007,7 +1012,10 @@ void pfc_init_m3n(void)
| GPSR0_D14
| GPSR0_D13
| GPSR0_D12
| GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
| GPSR0_D11
| GPSR0_D10
| GPSR0_D9
| GPSR0_D8);
pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
| GPSR1_EX_WAIT0_A
| GPSR1_A19
......@@ -1021,7 +1029,11 @@ void pfc_init_m3n(void)
| GPSR1_A7
| GPSR1_A6
| GPSR1_A5
| GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
| GPSR1_A4
| GPSR1_A3
| GPSR1_A2
| GPSR1_A1
| GPSR1_A0);
pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
| GPSR2_AVB_AVTP_MATCH_A
| GPSR2_AVB_LINK
......@@ -1031,7 +1043,10 @@ void pfc_init_m3n(void)
| GPSR2_PWM1_A
| GPSR2_IRQ5
| GPSR2_IRQ4
| GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
| GPSR2_IRQ3
| GPSR2_IRQ2
| GPSR2_IRQ1
| GPSR2_IRQ0);
pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
| GPSR3_SD0_CD
| GPSR3_SD1_DAT3
......@@ -1041,7 +1056,9 @@ void pfc_init_m3n(void)
| GPSR3_SD0_DAT3
| GPSR3_SD0_DAT2
| GPSR3_SD0_DAT1
| GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
| GPSR3_SD0_DAT0
| GPSR3_SD0_CMD
| GPSR3_SD0_CLK);
pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
| GPSR4_SD3_DAT6
| GPSR4_SD3_DAT3
......@@ -1054,7 +1071,9 @@ void pfc_init_m3n(void)
| GPSR4_SD2_DAT3
| GPSR4_SD2_DAT2
| GPSR4_SD2_DAT1
| GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
| GPSR4_SD2_DAT0
| GPSR4_SD2_CMD
| GPSR4_SD2_CLK);
pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
| GPSR5_MSIOF0_SS1
| GPSR5_MSIOF0_SYNC
......@@ -1069,7 +1088,9 @@ void pfc_init_m3n(void)
| GPSR5_RTS1_TANS
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
| GPSR5_RX1_A
| GPSR5_RTS0_TANS
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
| GPSR6_USB1_OVC
......@@ -1089,9 +1110,12 @@ void pfc_init_m3n(void)
| GPSR6_SSI_SCK4
| GPSR6_SSI_SDATA1_A
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
| GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
| GPSR7_HDMI0_CEC
| GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
......@@ -1108,7 +1132,9 @@ void pfc_init_m3n(void)
| POC_SD0_DAT3_33V
| POC_SD0_DAT2_33V
| POC_SD0_DAT1_33V
| POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
| POC_SD0_DAT0_33V
| POC_SD0_CMD_33V
| POC_SD0_CLK_33V);
/* initialize DRV control register */
reg = mmio_read_32(PFC_DRVCTRL0);
......
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
View file @ 7825d719
......@@ -12,7 +12,7 @@
#include "../qos_reg.h"
#include "qos_init_e3_v10.h"
#define RCAR_QOS_VERSION "rev.0.02"
#define RCAR_QOS_VERSION "rev.0.05"
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
......@@ -134,14 +134,6 @@ void qos_init_e3_v10(void)
}
}
/* 3DG bus Leaf setting */
io_write_32(GPU_ACT_GRD, 0x00001234U);
io_write_32(GPU_ACT0, 0x00000000U);
io_write_32(GPU_ACT1, 0x00000000U);
io_write_32(GPU_ACT2, 0x00000000U);
io_write_32(GPU_ACT3, 0x00000000U);
io_write_32(GPU_ACT_GRD, 0x00000000U);
/* RT bus Leaf setting */
io_write_32(RT_ACT0, 0x00000000U);
io_write_32(RT_ACT1, 0x00000000U);
......
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h
View file @ 7825d719
......@@ -27,20 +27,20 @@ static uint64_t mstat_fix[] = {
/* 0x0098, */ 0x0000000000000000UL,
/* 0x00a0, */ 0x000C08380000FFFFUL,
/* 0x00a8, */ 0x000C04110000FFFFUL,
/* 0x00b0, */ 0x000C04110000FFFFUL,
/* 0x00b0, */ 0x000C04150000FFFFUL,
/* 0x00b8, */ 0x0000000000000000UL,
/* 0x00c0, */ 0x000C08380000FFFFUL,
/* 0x00c8, */ 0x000C04110000FFFFUL,
/* 0x00d0, */ 0x000C04110000FFFFUL,
/* 0x00d0, */ 0x000C04150000FFFFUL,
/* 0x00d8, */ 0x0000000000000000UL,
/* 0x00e0, */ 0x0000000000000000UL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x001018580000FFFFUL,
/* 0x00f8, */ 0x000C04400000FFFFUL,
/* 0x00f8, */ 0x000C084F0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x001008580000FFFFUL,
/* 0x0118, */ 0x000C19660000FFFFUL,
/* 0x0118, */ 0x000C21E40000FFFFUL,
/* 0x0120, */ 0x0000000000000000UL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
......
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h
View file @ 7825d719
......@@ -27,20 +27,20 @@ static uint64_t mstat_fix[] = {
/* 0x0098, */ 0x0000000000000000UL,
/* 0x00a0, */ 0x000C10700000FFFFUL,
/* 0x00a8, */ 0x000C08210000FFFFUL,
/* 0x00b0, */ 0x000C08210000FFFFUL,
/* 0x00b0, */ 0x000C082A0000FFFFUL,
/* 0x00b8, */ 0x0000000000000000UL,
/* 0x00c0, */ 0x000C10700000FFFFUL,
/* 0x00c8, */ 0x000C08210000FFFFUL,
/* 0x00d0, */ 0x000C08210000FFFFUL,
/* 0x00d0, */ 0x000C082A0000FFFFUL,
/* 0x00d8, */ 0x0000000000000000UL,
/* 0x00e0, */ 0x0000000000000000UL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x00102CAF0000FFFFUL,
/* 0x00f8, */ 0x000C087F0000FFFFUL,
/* 0x00f8, */ 0x000C0C9D0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x00100CAF0000FFFFUL,
/* 0x0118, */ 0x000C32CC0000FFFFUL,
/* 0x0118, */ 0x000C43C80000FFFFUL,
/* 0x0120, */ 0x0000000000000000UL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
View file @ 7825d719
......@@ -12,7 +12,8 @@
#include "../qos_reg.h"
#include "qos_init_h3_v20.h"
#define RCAR_QOS_VERSION "rev.0.19"
#define RCAR_QOS_VERSION "rev.0.20"
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
View file @ 7825d719
......@@ -12,7 +12,8 @@
#include "../qos_reg.h"
#include "qos_init_h3_v30.h"
#define RCAR_QOS_VERSION "rev.0.07"
#define RCAR_QOS_VERSION "rev.0.10"
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
......@@ -226,8 +227,6 @@ void qos_init_h3_v30(void)
io_write_32(AXI_TR3CR, 0x00010000U);
io_write_32(AXI_TR4CR, 0x00010000U);
/* 3DG bus Leaf setting */
/* RT bus Leaf setting */
io_write_32(RT_ACT0, 0x00000000U);
io_write_32(RT_ACT1, 0x00000000U);
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat195.h
View file @ 7825d719
......@@ -36,12 +36,12 @@ static uint64_t mstat_fix[] = {
/* 0x00e0, */ 0x00100C090000FFFFUL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x001024090000FFFFUL,
/* 0x00f8, */ 0x000C08080000FFFFUL,
/* 0x00f8, */ 0x000C100D0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x00100C090000FFFFUL,
/* 0x0118, */ 0x000C18180000FFFFUL,
/* 0x0120, */ 0x000C18180000FFFFUL,
/* 0x0118, */ 0x000C1C1B0000FFFFUL,
/* 0x0120, */ 0x000C1C1B0000FFFFUL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
/* 0x0138, */ 0x00100C0B0000FFFFUL,
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat390.h
View file @ 7825d719
......@@ -36,12 +36,12 @@ static uint64_t mstat_fix[] = {
/* 0x00e0, */ 0x001014110000FFFFUL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x001044110000FFFFUL,
/* 0x00f8, */ 0x000C10100000FFFFUL,
/* 0x00f8, */ 0x000C1C1A0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x001014110000FFFFUL,
/* 0x0118, */ 0x000C302F0000FFFFUL,
/* 0x0120, */ 0x000C302F0000FFFFUL,
/* 0x0118, */ 0x000C38360000FFFFUL,
/* 0x0120, */ 0x000C38360000FFFFUL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
/* 0x0138, */ 0x001018150000FFFFUL,
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
View file @ 7825d719
......@@ -12,7 +12,8 @@
#include "../qos_reg.h"
#include "qos_init_h3n_v30.h"
#define RCAR_QOS_VERSION "rev.0.03"
#define RCAR_QOS_VERSION "rev.0.06"
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
......@@ -220,14 +221,6 @@ void qos_init_h3n_v30(void)
io_write_32(AXI_TR3CR, 0x00010000U);
io_write_32(AXI_TR4CR, 0x00010000U);
/* 3DG bus Leaf setting */
io_write_32(GPU_ACT_GRD, 0x00001234U);
io_write_32(GPU_ACT0, 0x00000000U);
io_write_32(GPU_ACT1, 0x00000000U);
io_write_32(GPU_ACT2, 0x00000000U);
io_write_32(GPU_ACT3, 0x00000000U);
io_write_32(GPU_ACT_GRD, 0x00000000U);
/* RT bus Leaf setting */
io_write_32(RT_ACT0, 0x00000000U);
io_write_32(RT_ACT1, 0x00000000U);
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat195.h
View file @ 7825d719
......@@ -36,12 +36,12 @@ static uint64_t mstat_fix[] = {
/* 0x00e0, */ 0x00100C090000FFFFUL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x001024090000FFFFUL,
/* 0x00f8, */ 0x000C08080000FFFFUL,
/* 0x00f8, */ 0x000C100D0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x00100C090000FFFFUL,
/* 0x0118, */ 0x000C18180000FFFFUL,
/* 0x0120, */ 0x000C18180000FFFFUL,
/* 0x0118, */ 0x000C1C1B0000FFFFUL,
/* 0x0120, */ 0x000C1C1B0000FFFFUL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
/* 0x0138, */ 0x00100C0B0000FFFFUL,
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat390.h
View file @ 7825d719
......@@ -36,12 +36,12 @@ static uint64_t mstat_fix[] = {
/* 0x00e0, */ 0x001014110000FFFFUL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x001044110000FFFFUL,
/* 0x00f8, */ 0x000C10100000FFFFUL,
/* 0x00f8, */ 0x000C1C1A0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x001014110000FFFFUL,
/* 0x0118, */ 0x000C302F0000FFFFUL,
/* 0x0120, */ 0x000C302F0000FFFFUL,
/* 0x0118, */ 0x000C38360000FFFFUL,
/* 0x0120, */ 0x000C38360000FFFFUL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
/* 0x0138, */ 0x001018150000FFFFUL,
......
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
View file @ 7825d719
......@@ -12,7 +12,8 @@
#include "../qos_reg.h"
#include "qos_init_m3_v11.h"
#define RCAR_QOS_VERSION "rev.0.17"
#define RCAR_QOS_VERSION "rev.0.18"
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
......
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
View file @ 7825d719
......@@ -12,7 +12,7 @@
#include "../qos_reg.h"
#include "qos_init_m3n_v10.h"
#define RCAR_QOS_VERSION "rev.0.06"
#define RCAR_QOS_VERSION "rev.0.08"
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
......@@ -198,14 +198,6 @@ void qos_init_m3n_v10(void)
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
}
/* 3DG bus Leaf setting */
io_write_32(GPU_ACT_GRD, 0x00001234U);
io_write_32(GPU_ACT0, 0x00000000U);
io_write_32(GPU_ACT1, 0x00000000U);
io_write_32(GPU_ACT2, 0x00000000U);
io_write_32(GPU_ACT3, 0x00000000U);
io_write_32(GPU_ACT_GRD, 0x00000000U);
/* RT bus Leaf setting */
io_write_32(RT_ACT0, 0x00000000U);
io_write_32(RT_ACT1, 0x00000000U);
......
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h
View file @ 7825d719
......@@ -27,11 +27,11 @@ static uint64_t mstat_fix[] = {
/* 0x0098, */ 0x0000000000000000UL,
/* 0x00a0, */ 0x000C041D0000FFFFUL,
/* 0x00a8, */ 0x000C04090000FFFFUL,
/* 0x00b0, */ 0x000C04090000FFFFUL,
/* 0x00b0, */ 0x000C040B0000FFFFUL,
/* 0x00b8, */ 0x0000000000000000UL,
/* 0x00c0, */ 0x000C041D0000FFFFUL,
/* 0x00c8, */ 0x000C04090000FFFFUL,
/* 0x00d0, */ 0x000C04090000FFFFUL,
/* 0x00d0, */ 0x000C040B0000FFFFUL,
/* 0x00d8, */ 0x0000000000000000UL,
/* 0x00e0, */ 0x0000000000000000UL,
/* 0x00e8, */ 0x0000000000000000UL,
......
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h
View file @ 7825d719
......@@ -27,11 +27,11 @@ static uint64_t mstat_fix[] = {
/* 0x0098, */ 0x0000000000000000UL,
/* 0x00a0, */ 0x000C08390000FFFFUL,
/* 0x00a8, */ 0x000C04110000FFFFUL,
/* 0x00b0, */ 0x000C04110000FFFFUL,
/* 0x00b0, */ 0x000C04150000FFFFUL,
/* 0x00b8, */ 0x0000000000000000UL,
/* 0x00c0, */ 0x000C08390000FFFFUL,
/* 0x00c8, */ 0x000C04110000FFFFUL,
/* 0x00d0, */ 0x000C04110000FFFFUL,
/* 0x00d0, */ 0x000C04150000FFFFUL,
/* 0x00d8, */ 0x0000000000000000UL,
/* 0x00e0, */ 0x0000000000000000UL,
/* 0x00e8, */ 0x0000000000000000UL,
......
drivers/staging/renesas/rcar/qos/qos_common.h
View file @ 7825d719
......@@ -9,6 +9,15 @@
#define RCAR_REF_DEFAULT (0U)
/* define used for get_refperiod. */
/* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */
/* refere to plat/renesas/rcar/ddr/ddr_a/ddr_init_e3.h for E3. */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF default */
#define REFPERIOD_CYCLE ((126 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */
#else /* REF option */
#define REFPERIOD_CYCLE ((252 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */
#endif
#if (RCAR_LSI == RCAR_E3)
/* define used for E3 */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 3.9usec */
......@@ -19,7 +28,7 @@
#define OPERATING_FREQ_E3 (266U) /* MHz */
#define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 -1U)
#define QOSWT_WTSET0_CYCLE_E3 ((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3) /* unit:ns */
/* #define QOSWT_WTSET0_CYCLE_E3 ((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3) */ /* unit:ns */
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
......
drivers/staging/renesas/rcar/qos/qos_init.c
View file @ 7825d719
......@@ -238,6 +238,7 @@ void rcar_qos_init(void)
#endif
}
#if !(RCAR_LSI == RCAR_E3)
uint32_t get_refperiod(void)
{
uint32_t refperiod = QOSWT_WTSET0_CYCLE;
......@@ -254,11 +255,9 @@ uint32_t get_refperiod(void)
case PRR_PRODUCT_11:
break;
case PRR_PRODUCT_20:
refperiod = QOSWT_WTSET0_CYCLE_H3_20;
break;
case PRR_PRODUCT_30:
default:
refperiod = QOSWT_WTSET0_CYCLE_H3_30;
refperiod = REFPERIOD_CYCLE;
break;
}
break;
......@@ -267,7 +266,7 @@ uint32_t get_refperiod(void)
switch (reg & PRR_CUT_MASK) {
case PRR_PRODUCT_30:
default:
refperiod = QOSWT_WTSET0_CYCLE_H3N;
refperiod = REFPERIOD_CYCLE;
break;
}
break;
......@@ -277,21 +276,16 @@ uint32_t get_refperiod(void)
switch (reg & PRR_CUT_MASK) {
case PRR_PRODUCT_10:
break;
case PRR_PRODUCT_20: /* M3 Cut 11 */
case PRR_PRODUCT_20: /* M3 Cut 11 */
default:
refperiod = QOSWT_WTSET0_CYCLE_M3_11;
refperiod = REFPERIOD_CYCLE;
break;
}
break;
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
case PRR_PRODUCT_M3N:
refperiod = QOSWT_WTSET0_CYCLE_M3N;
break;
#endif
#if (RCAR_LSI == RCAR_E3)
case PRR_PRODUCT_E3:
refperiod = QOSWT_WTSET0_CYCLE_E3;
refperiod = REFPERIOD_CYCLE;
break;
#endif
default:
......@@ -302,28 +296,25 @@ uint32_t get_refperiod(void)
/* H3 Cut 10 */
#elif RCAR_LSI_CUT == RCAR_CUT_11
/* H3 Cut 11 */
#elif RCAR_LSI_CUT == RCAR_CUT_20
/* H3 Cut 20 */
refperiod = QOSWT_WTSET0_CYCLE_H3_20;
#else
/* H3 Cut 20 */
/* H3 Cut 30 or later */
refperiod = QOSWT_WTSET0_CYCLE_H3_30;
refperiod = REFPERIOD_CYCLE;
#endif
#elif RCAR_LSI == RCAR_H3N
/* H3N Cut 30 or later */
refperiod = QOSWT_WTSET0_CYCLE_H3N;
refperiod = REFPERIOD_CYCLE;
#elif RCAR_LSI == RCAR_M3
#if RCAR_LSI_CUT == RCAR_CUT_10
/* M3 Cut 10 */
#else
/* M3 Cut 11 or later */
refperiod = QOSWT_WTSET0_CYCLE_M3_11;
refperiod = REFPERIOD_CYCLE;
#endif
#elif RCAR_LSI == RCAR_M3N /* for M3N */
refperiod = QOSWT_WTSET0_CYCLE_M3N;
#elif RCAR_LSI == RCAR_E3 /* for E3 */
refperiod = QOSWT_WTSET0_CYCLE_E3;
refperiod = REFPERIOD_CYCLE;
#endif
return refperiod;
}
#endif
plat/renesas/rcar/aarch64/plat_helpers.S
View file @ 7825d719
......@@ -217,6 +217,8 @@ endfunc platform_mem_init
* ---------------------------------------------
*/
func plat_report_exception
/* Switch to SP_EL0 */
msr spsel, #0
#if IMAGE_BL2
mov w1, #FIQ_SP_EL0
cmp w0, w1
......@@ -326,11 +328,11 @@ func plat_reset_handler
ubfx w0, w0, 8, 8
/* H3? */
cmp w0, #0x4F
b.eq H3
b.eq RCARH3
/* set R-Car M3/M3N */
mov x2, #1
b CHK_A5x
H3:
RCARH3:
/* set R-Car H3 */
mov x2, #0
/* --------------------------------------------------------------------
......
plat/renesas/rcar/aarch64/platform_common.c
View file @ 7825d719
......@@ -102,7 +102,7 @@ const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]
#endif
#if IMAGE_BL2
const mmap_region_t rcar_mmap[] = {
static const mmap_region_t rcar_mmap[] = {
MAP_FLASH0, /* 0x08000000 - 0x0BFFFFFF RPC area */
MAP_DRAM0, /* 0x40000000 - 0xBFFFFFFF DRAM area(Legacy) */
MAP_REG0, /* 0xE6000000 - 0xE62FFFFF SoC register area */
......@@ -116,7 +116,7 @@ const mmap_region_t rcar_mmap[] = {
#endif
#if IMAGE_BL31
const mmap_region_t rcar_mmap[] = {
static const mmap_region_t rcar_mmap[] = {
MAP_SHARED_RAM,
MAP_ATFW_CRASH,
MAP_ATFW_LOG,
......@@ -129,7 +129,7 @@ const mmap_region_t rcar_mmap[] = {
#endif
#if IMAGE_BL32
const mmap_region_t rcar_mmap[] = {
static const mmap_region_t rcar_mmap[] = {
MAP_DEVICE0,
MAP_DEVICE1,
{0}
......
plat/renesas/rcar/bl2_interrupt_error.c
View file @ 7825d719
......@@ -24,7 +24,7 @@ void bl2_interrupt_error_id(uint32_t int_id)
ERROR("\n");
if (int_id >= SWDT_ERROR_ID) {
ERROR("Unhandled exception occurred.\n");
ERROR(" Exception type = FIQ_SP_ELX\n");
ERROR(" Exception type = FIQ_SP_EL0\n");
panic();
}
......@@ -32,11 +32,11 @@ void bl2_interrupt_error_id(uint32_t int_id)
gicv2_end_of_interrupt((uint32_t) int_id);
rcar_swdt_release();
ERROR("Unhandled exception occurred.\n");
ERROR(" Exception type = FIQ_SP_ELX\n");
ERROR(" SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
ERROR(" ELR_EL1 = 0x%x\n", (uint32_t) read_elr_el1());
ERROR(" ESR_EL1 = 0x%x\n", (uint32_t) read_esr_el1());
ERROR(" FAR_EL1 = 0x%x\n", (uint32_t) read_far_el1());
ERROR(" Exception type = FIQ_SP_EL0\n");
ERROR(" SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
ERROR(" ELR_EL3 = 0x%x\n", (uint32_t) read_elr_el3());
ERROR(" ESR_EL3 = 0x%x\n", (uint32_t) read_esr_el3());
ERROR(" FAR_EL3 = 0x%x\n", (uint32_t) read_far_el3());
ERROR("\n");
panic();
}
......@@ -78,27 +78,27 @@ void bl2_interrupt_error_type(uint32_t ex_type)
&interrupt_ex[ex_type][0]);
ERROR("%s", msg);
switch (ex_type) {
case SYNC_EXCEPTION_SP_ELX:
ERROR(" SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
ERROR(" ELR_EL1 = 0x%x\n", (uint32_t) read_elr_el1());
ERROR(" ESR_EL1 = 0x%x\n", (uint32_t) read_esr_el1());
ERROR(" FAR_EL1 = 0x%x\n", (uint32_t) read_far_el1());
case SYNC_EXCEPTION_SP_EL0:
ERROR(" SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
ERROR(" ELR_EL3 = 0x%x\n", (uint32_t) read_elr_el3());
ERROR(" ESR_EL3 = 0x%x\n", (uint32_t) read_esr_el3());
ERROR(" FAR_EL3 = 0x%x\n", (uint32_t) read_far_el3());
break;
case IRQ_SP_ELX:
ERROR(" SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
ERROR(" ELR_EL1 = 0x%x\n", (uint32_t) read_elr_el1());
ERROR(" IAR_EL1 = 0x%x\n", gicv2_acknowledge_interrupt());
case IRQ_SP_EL0:
ERROR(" SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
ERROR(" ELR_EL3 = 0x%x\n", (uint32_t) read_elr_el3());
ERROR(" IAR_EL3 = 0x%x\n", gicv2_acknowledge_interrupt());
break;
case FIQ_SP_ELX:
ERROR(" SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
ERROR(" ELR_EL1 = 0x%x\n", (uint32_t) read_elr_el1());
ERROR(" IAR_EL1 = 0x%x\n", gicv2_acknowledge_interrupt());
case FIQ_SP_EL0:
ERROR(" SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
ERROR(" ELR_EL3 = 0x%x\n", (uint32_t) read_elr_el3());
ERROR(" IAR_EL3 = 0x%x\n", gicv2_acknowledge_interrupt());
break;
case SERROR_SP_ELX:
ERROR(" SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
ERROR(" ELR_EL1 = 0x%x\n", (uint32_t) read_elr_el1());
ERROR(" ESR_EL1 = 0x%x\n", (uint32_t) read_esr_el1());
ERROR(" FAR_EL1 = 0x%x\n", (uint32_t) read_far_el1());
case SERROR_SP_EL0:
ERROR(" SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
ERROR(" ELR_EL3 = 0x%x\n", (uint32_t) read_elr_el3());
ERROR(" ESR_EL3 = 0x%x\n", (uint32_t) read_esr_el3());
ERROR(" FAR_EL3 = 0x%x\n", (uint32_t) read_far_el3());
break;
default:
break;
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment