Merge pull request #1734 from marex/arm/master/update-rcar-2.0.0

Arm/master/update rcar 2.0.0

plat/renesas/rcar/bl2_plat_setup.c

@@ -61,6 +61,8 @@ extern void rcar_rpc_init(void);
 extern void rcar_pfc_init(void);
 extern void rcar_dma_init(void);
 
+static void bl2_init_generic_timer(void);
+
 /* R-Car Gen3 product check */
 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
 #define TARGET_PRODUCT			RCAR_PRODUCT_H3
@@ -74,6 +76,8 @@ extern void rcar_dma_init(void);
 #elif RCAR_LSI == RCAR_E3
 #define TARGET_PRODUCT			RCAR_PRODUCT_E3
 #define TARGET_NAME			"R-Car E3"
+#elif RCAR_LSI == RCAR_AUTO
+#define TARGET_NAME			"R-Car H3/M3/M3N"
 #endif
 
 #if (RCAR_LSI == RCAR_E3)
@@ -259,8 +263,10 @@ tlb:
 		   product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) {
 		mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
 		mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
-	} else if (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) {
+	} else if ((product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) ||
+		   (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER11))) {
 		mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
+		mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE);
 		mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
 	}
 
@@ -388,7 +394,7 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
 	return 0;
 }
 
-meminfo_t *bl2_plat_sec_mem_layout(void)
+struct meminfo *bl2_plat_sec_mem_layout(void)
 {
 	return &bl2_tzram_layout;
 }
@@ -624,6 +630,8 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
 	int fcnlnode;
 #endif
 
+	bl2_init_generic_timer();
+
 	reg = mmio_read_32(RCAR_MODEMR);
 	boot_dev = reg & MODEMR_BOOT_DEV_MASK;
 	boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
@@ -899,7 +907,7 @@ void bl2_el3_plat_arch_setup(void)
 #if RCAR_BL2_DCACHE == 1
 	NOTICE("BL2: D-Cache enable\n");
 	rcar_configure_mmu_el3(BL2_BASE,
-			       RCAR_SYSRAM_LIMIT - BL2_BASE,
+			       BL2_END - BL2_BASE,
 			       BL2_RO_BASE, BL2_RO_LIMIT
 #if USE_COHERENT_MEM
 			       , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT
@@ -912,3 +920,52 @@ void bl2_platform_setup(void)
 {
 
 }
+
+static void bl2_init_generic_timer(void)
+{
+#if RCAR_LSI == RCAR_E3
+	uint32_t reg_cntfid = EXTAL_EBISU;
+#else /* RCAR_LSI == RCAR_E3 */
+	uint32_t reg;
+	uint32_t reg_cntfid;
+	uint32_t modemr;
+	uint32_t modemr_pll;
+	uint32_t board_type;
+	uint32_t board_rev;
+	uint32_t pll_table[] = {
+		EXTAL_MD14_MD13_TYPE_0,	/* MD14/MD13 : 0b00 */
+		EXTAL_MD14_MD13_TYPE_1,	/* MD14/MD13 : 0b01 */
+		EXTAL_MD14_MD13_TYPE_2,	/* MD14/MD13 : 0b10 */
+		EXTAL_MD14_MD13_TYPE_3	/* MD14/MD13 : 0b11 */
+	};
+
+	modemr = mmio_read_32(RCAR_MODEMR);
+	modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK);
+
+	/* Set frequency data in CNTFID0 */
+	reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
+	reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+	switch (modemr_pll) {
+	case MD14_MD13_TYPE_0:
+		rcar_get_board_type(&board_type, &board_rev);
+		if (BOARD_SALVATOR_XS == board_type) {
+			reg_cntfid = EXTAL_SALVATOR_XS;
+		}
+		break;
+	case MD14_MD13_TYPE_3:
+		if (RCAR_PRODUCT_H3_CUT10 == reg) {
+			reg_cntfid = reg_cntfid >> 1U;
+		}
+		break;
+	default:
+		/* none */
+		break;
+	}
+#endif /* RCAR_LSI == RCAR_E3 */
+	/* Update memory mapped and register based freqency */
+	write_cntfrq_el0((u_register_t )reg_cntfid);
+	mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid);
+	/* Enable counter */
+	mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF,
+			(uint32_t)CNTCR_EN);
+}

plat/renesas/rcar/bl31_plat_setup.c

@@ -64,7 +64,7 @@ void plat_cci_disable(void)
 	cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
 }
 
-entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
+struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
 {
 	bl2_to_bl31_params_mem_t *from_bl2 = (bl2_to_bl31_params_mem_t *)
 					     PARAMS_BASE;
@@ -100,6 +100,7 @@ void bl31_plat_arch_setup(void)
 			       , BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT
 #endif
 	    );
+	rcar_pwrc_code_copy_to_system_ram();
 }
 
 void bl31_platform_setup(void)

plat/renesas/rcar/include/platform_def.h

@@ -79,7 +79,7 @@
  *          Cortex-A53
  * L1:I/32KB(16KBx2way) D/32KB(8KBx4way) L2:512KB(32KBx16way)
  */
-#define PLATFORM_CACHE_LINE_SIZE	128
+#define PLATFORM_CACHE_LINE_SIZE	64
 #define PLATFORM_CLUSTER_COUNT		U(2)
 #define PLATFORM_CLUSTER0_CORE_COUNT	U(4)
 #define PLATFORM_CLUSTER1_CORE_COUNT	U(4)
@@ -104,16 +104,16 @@
  * size plus a little space for growth. */
 #define RCAR_SYSRAM_BASE		U(0xE6300000)
 #if RCAR_LSI == RCAR_E3
-#define RCAR_SYSRAM_LIMIT		U(0xE6320000)
+#define BL2_LIMIT			U(0xE6320000)
 #else
-#define RCAR_SYSRAM_LIMIT		U(0xE6360000)
+#define BL2_LIMIT			U(0xE6360000)
 #endif
 
 #define BL2_BASE			U(0xE6304000)
 #if RCAR_LSI == RCAR_E3
-#define BL2_LIMIT			U(0xE6318000)
+#define BL2_IMAGE_LIMIT			U(0xE6318000)
 #else
-#define BL2_LIMIT			U(0xE632E800)
+#define BL2_IMAGE_LIMIT			U(0xE632E800)
 #endif
 #define RCAR_SYSRAM_SIZE		(BL2_BASE - RCAR_SYSRAM_BASE)
 

plat/renesas/rcar/include/rcar_def.h

@@ -24,7 +24,7 @@
 #define DEVICE_RCAR_SIZE		U(0x00300000)
 #define DEVICE_RCAR_BASE2		U(0xE6360000)
 #define DEVICE_RCAR_SIZE2		U(0x19CA0000)
-#define DEVICE_SRAM_BASE		U(0xE6310000)
+#define DEVICE_SRAM_BASE		U(0xE6300000)
 #define DEVICE_SRAM_SIZE		U(0x00002000)
 #define DEVICE_SRAM_STACK_BASE		(DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE)
 #define DEVICE_SRAM_STACK_SIZE		U(0x00001000)
@@ -231,6 +231,8 @@
 #define IPMMUMM_IMSCTLR_ENABLE		(0xC0000000U)
 #define IPMMUMM_IMAUXCTLR_NMERGE40_BIT	(0x01000000U)
 #define IMSCTLR_DISCACHE		(0xE0000000U)
+#define IPMMU_VP0_BASE			(0xFE990000U)
+#define IPMMUVP0_IMSCTLR		(IPMMU_VP0_BASE + 0x0500U)
 #define IPMMU_VI0_BASE			(0xFEBD0000U)
 #define IPMMUVI0_IMSCTLR		(IPMMU_VI0_BASE + 0x0500U)
 #define IPMMU_VI1_BASE			(0xFEBE0000U)

plat/renesas/rcar/include/rcar_version.h

@@ -9,7 +9,7 @@
 
 #include <arch_helpers.h>
 
-#define VERSION_OF_RENESAS		"1.0.22"
+#define VERSION_OF_RENESAS		"2.0.0"
 #define	VERSION_OF_RENESAS_MAXLEN	(128)
 
 extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN];

plat/renesas/rcar/plat_pm.c

@@ -22,6 +22,7 @@
 #include "pwrc.h"
 #include "rcar_def.h"
 #include "rcar_private.h"
+#include "ulcb_cpld.h"
 
 #define	DVFS_SET_VID_0V		(0x00)
 #define	P_ALL_OFF		(0x80)
@@ -41,10 +42,6 @@ extern void plat_rcar_gic_driver_init(void);
 extern void plat_rcar_gic_init(void);
 extern u_register_t rcar_boot_mpidr;
 
-#if (RCAR_GEN3_ULCB == 1)
-extern void rcar_cpld_reset_cpu(void);
-#endif
-
 static uintptr_t rcar_sec_entrypoint;
 
 static void rcar_program_mailbox(uint64_t mpidr, uint64_t address)
@@ -155,6 +152,7 @@ static void rcar_pwr_domain_suspend_finish(const psci_power_state_t
 	write_cntfrq_el0(plat_get_syscnt_freq2());
 	mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(U(0)) | CNTCR_EN);
 	rcar_pwrc_setup();
+	rcar_pwrc_code_copy_to_system_ram();
 
 #if RCAR_SYSTEM_SUSPEND
 	rcar_pwrc_init_suspend_to_ram();
@@ -167,11 +165,9 @@ static void __dead2 rcar_system_off(void)
 {
 #if PMIC_ROHM_BD9571
 #if PMIC_LEVEL_MODE
-	rcar_pwrc_code_copy_to_system_ram();
 	if (rcar_iic_dvfs_send(PMIC, DVFS_SET_VID, DVFS_SET_VID_0V))
 		ERROR("BL3-1:Failed the SYSTEM-OFF.\n");
 #else
-	rcar_pwrc_code_copy_to_system_ram();
 	if (rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, P_ALL_OFF))
 		ERROR("BL3-1:Failed the SYSTEM-RESET.\n");
 #endif
@@ -204,7 +200,6 @@ static void __dead2 rcar_system_reset(void)
 	uint8_t mode;
 	int32_t error;
 
-	rcar_pwrc_code_copy_to_system_ram();
 	error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, KEEP10_MAGIC);
 	if (error) {
 		ERROR("Failed send KEEP10 magic ret=%d \n", error);
@@ -227,7 +222,6 @@ static void __dead2 rcar_system_reset(void)
 	rcar_pwrc_set_suspend_to_ram();
 done:
 #else
-	rcar_pwrc_code_copy_to_system_ram();
 	if (rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, P_ALL_OFF))
 		ERROR("BL3-1:Failed the SYSTEM-RESET.\n");
 #endif

plat/renesas/rcar/platform.mk

@@ -4,13 +4,14 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
-PROGRAMMABLE_RESET_ADDRESS	:= 0
+PROGRAMMABLE_RESET_ADDRESS	:= 1
 COLD_BOOT_SINGLE_CPU		:= 1
 ARM_CCI_PRODUCT_ID		:= 500
 TRUSTED_BOARD_BOOT		:= 1
 RESET_TO_BL31			:= 1
 GENERATE_COT			:= 1
 BL2_AT_EL3			:= 1
+ENABLE_SVE_FOR_NS		:= 0
 
 $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
 
@@ -310,6 +311,7 @@ PLAT_INCLUDES	:=	-Iinclude/common/tbbr			\
 			-Idrivers/staging/renesas/rcar/qos	\
 			-Idrivers/renesas/rcar/iic_dvfs		\
 			-Idrivers/renesas/rcar/board		\
+			-Idrivers/renesas/rcar/cpld/		\
 			-Idrivers/renesas/rcar/avs		\
 			-Idrivers/renesas/rcar/delay		\
 			-Idrivers/renesas/rcar/rom		\
@@ -353,7 +355,7 @@ BL2_SOURCES	+=	${RCAR_GIC_SOURCES}				\
 			drivers/renesas/rcar/rpc/rpc_driver.c		\
 			drivers/renesas/rcar/dma/dma_driver.c		\
 			drivers/renesas/rcar/avs/avs_driver.c		\
-			drivers/renesas/rcar/delay/micro_delay.S	\
+			drivers/renesas/rcar/delay/micro_delay.c	\
 			drivers/renesas/rcar/emmc/emmc_interrupt.c	\
 			drivers/renesas/rcar/emmc/emmc_utility.c	\
 			drivers/renesas/rcar/emmc/emmc_mount.c		\
@@ -376,6 +378,7 @@ BL31_SOURCES	+=	${RCAR_GIC_SOURCES}				\
 			plat/renesas/rcar/plat_pm.c			\
 			drivers/renesas/rcar/console/rcar_console.S	\
 			drivers/renesas/rcar/console/rcar_printf.c	\
+			drivers/renesas/rcar/delay/micro_delay.c	\
 			drivers/renesas/rcar/pwrc/call_sram.S		\
 			drivers/renesas/rcar/pwrc/pwrc.c		\
 			drivers/renesas/rcar/common.c			\
@@ -415,7 +418,7 @@ clean_srecord:
 	rm -f ${SREC_PATH}/bl2.srec ${SREC_PATH}/bl31.srec
 
 .PHONY: rcar_srecord
-rcar_srecord:
+rcar_srecord: $(BL2_ELF_SRC) $(BL31_ELF_SRC)
 	@echo "generating srec: ${SREC_PATH}/bl2.srec"
 	$(Q)$(OC) -O srec --srec-forceS3 ${BL2_ELF_SRC}  ${SREC_PATH}/bl2.srec
 	@echo "generating srec: ${SREC_PATH}/bl31.srec"