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Unverified Commit 7825d719 authored by Antonio Niño Díaz's avatar Antonio Niño Díaz Committed by GitHub
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Merge pull request #1734 from marex/arm/master/update-rcar-2.0.0 

Arm/master/update rcar 2.0.0
parents c8719032 e68d2146
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drivers/renesas/rcar/auth/auth_mod.c
View file @ 7825d719
......@@ -113,7 +113,7 @@ verify_image:
}
#if RCAR_BL2_DCACHE == 1
/* clean and disable */
write_sctlr_el1(read_sctlr_el1() & ~SCTLR_C_BIT);
write_sctlr_el3(read_sctlr_el3() & ~SCTLR_C_BIT);
dcsw_op_all(DCCISW);
#endif
ret = (mmio_read_32(RCAR_BOOT_KEY_CERT_NEW) == RCAR_CERT_MAGIC_NUM) ?
......@@ -124,7 +124,7 @@ verify_image:
#if RCAR_BL2_DCACHE == 1
/* enable */
write_sctlr_el1(read_sctlr_el1() | SCTLR_C_BIT);
write_sctlr_el3(read_sctlr_el3() | SCTLR_C_BIT);
#endif
#endif
......
drivers/renesas/rcar/cpld/ulcb_cpld.c
View file @ 7825d719
......@@ -5,6 +5,7 @@
*/
#include <lib/mmio.h>
#include "ulcb_cpld.h"
#define SCLK 8 /* GP_6_8 */
#define SSTBZ 3 /* GP_2_3 */
......
drivers/renesas/rcar/cpld/ulcb_cpld.h 0 → 100644
View file @ 7825d719
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef RCAR_ULCB_CPLD_H__
#define RCAR_ULCB_CPLD_H__
extern void rcar_cpld_reset_cpu(void);
#endif /* RCAR_ULCB_CPLD_H__ */
drivers/renesas/rcar/delay/micro_delay.S deleted 100644 → 0
View file @ c8719032
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include "micro_delay.h"
#define CPG_BASE (0xE6150000)
#define CPG_SMSTPCR1 (0x0134)
#define CPG_CPGWPR (0x0900)
/* Module bit for TMU ch3-5 */
#define MSTPCR1_TMU1 (1 << 24)
#define TMU3_BASE (0xE6FC0000)
#define TMU_TSTR (0x0004)
#define TMU_TCOR (0x0008)
#define TMU_TCNT (0x000C)
#define TMU_TCR (0x0010)
/* Start bit for TMU ch3 */
#define TSTR1_TMU3 (1 << 0)
#define MIDR_CA57 (0x0D07 << MIDR_PN_SHIFT)
#define MIDR_CA53 (0x0D03 << MIDR_PN_SHIFT)
.globl rcar_micro_delay
#if (TMU3_MEASUREMENT == 1)
.globl tmu3_init
.globl tmu3_start
.globl tmu3_stop
.globl tcnt3_snapshot
#endif
/* Aligned with the cache line */
.align 6
func rcar_micro_delay
cbz x0, micro_delay_e
mrs x1, midr_el1
and x1, x1, #MIDR_PN_MASK << MIDR_PN_SHIFT
mov w2, #MIDR_CA53
cmp w1, w2
b.eq micro_delay_ca53
b micro_delay_ca57
micro_delay_e:
ret
endfunc rcar_micro_delay
func micro_delay_ca57
ca57_loop_1:
mov x1, #185
ca57_loop_2:
subs x1, x1, #1
b.ne ca57_loop_2
subs x0, x0, #1
b.ne ca57_loop_1
ret
endfunc micro_delay_ca57
func micro_delay_ca53
ca53_loop_1:
mov x1, #134
ca53_loop_2:
subs x1, x1, #1
b.ne ca53_loop_2
subs x0, x0, #1
b.ne ca53_loop_1
ret
endfunc micro_delay_ca53
#if (TMU3_MEASUREMENT == 1)
func tmu3_init
ldr x2, =CPG_BASE
ldr w0, [x2, #CPG_SMSTPCR1]
ldr w1, [x2, #CPG_MSTPSR1]
ldr w2, #MSTPCR1_TMU1
bl mstpcr_write
ret
endfunc tmu3_init
func tmu3_start
ldr x0, =TMU3_BASE
mov w1, #0xFFFFFFFF
str w1, [x0, TMU_TCNT]
ldr x0, =TMU3_BASE
ldrb w1, [x0, TMU_TSTR]
orr w1, w1, #TSTR1_TMU3
strb w1, [x0, TMU_TSTR]
ret
endfunc tmu3_start
func tcnt3_snapshot
ldr x0, =TMU3_BASE
ldr w0, [x0, TMU_TCNT]
ret
endfunc tcnt3_snapshot
func tmu3_stop
ldr x0, =TMU3_BASE
ldrb w1, [x0, TMU_TSTR]
and w1, w1, #~TSTR1_TMU3
strb w1, [x0, TMU_TSTR]
ret
endfunc tmu3_stop
#endif
drivers/renesas/rcar/delay/micro_delay.c 0 → 100644
View file @ 7825d719
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <arch_helpers.h>
#include "micro_delay.h"
#define RCAR_CONV_MICROSEC 1000000U
void
#if IMAGE_BL31
__attribute__ ((section (".system_ram")))
#endif
rcar_micro_delay(uint64_t micro_sec)
{
uint64_t freq;
uint64_t base_count;
uint64_t get_count;
uint64_t wait_time = 0U;
freq = read_cntfrq_el0();
base_count = read_cntpct_el0();
while (micro_sec > wait_time) {
get_count = read_cntpct_el0();
wait_time = ((get_count - base_count) * RCAR_CONV_MICROSEC) / freq;
}
}
drivers/renesas/rcar/delay/micro_delay.h
View file @ 7825d719
......@@ -7,20 +7,9 @@
#ifndef MICRO_DELAY_H
#define MICRO_DELAY_H
#define TMU3_MEASUREMENT (0)
#ifndef __ASSEMBLY__
#include <stdint.h>
void rcar_micro_delay(uint32_t count_us);
#if (TMU3_MEASUREMENT == 1)
void tmu3_start(void);
void tmu3_init(void);
void tmu3_stop(void);
uint32_t tcnt3_snapshot(void);
#endif
void rcar_micro_delay(uint64_t micro_sec);
#endif
#endif /* MICRO_DELAY_H */
drivers/renesas/rcar/pwrc/pwrc.c
View file @ 7825d719
......@@ -17,6 +17,7 @@
#include "iic_dvfs.h"
#include "rcar_def.h"
#include "rcar_private.h"
#include "micro_delay.h"
#include "pwrc.h"
/*
......@@ -122,7 +123,6 @@ RCAR_INSTANTIATE_LOCK
#define RST_BASE (0xE6160000U)
#define RST_MODEMR (RST_BASE + 0x0060U)
#define RST_MODEMR_BIT0 (0x00000001U)
#define RCAR_CONV_MICROSEC (1000000U)
#if PMIC_ROHM_BD9571
#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
......@@ -143,23 +143,6 @@ IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END);
IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START);
#endif
#if RCAR_SYSTEM_SUSPEND
static void __attribute__ ((section (".system_ram")))
rcar_pwrc_micro_delay(uint64_t micro_sec)
{
uint64_t freq, base, val;
uint64_t wait_time = 0;
freq = read_cntfrq_el0();
base = read_cntpct_el0();
while (micro_sec > wait_time) {
val = read_cntpct_el0() - base;
wait_time = val * RCAR_CONV_MICROSEC / freq;
}
}
#endif
uint32_t rcar_pwrc_status(uint64_t mpidr)
{
uint32_t ret = 0;
......@@ -414,7 +397,7 @@ self_refresh:
mmio_write_32(DBSC4_REG_DBACEN, 0);
if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
rcar_pwrc_micro_delay(100);
rcar_micro_delay(100);
else if (product == RCAR_PRODUCT_H3) {
mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
DBCAM_FLUSH(0);
......@@ -465,7 +448,7 @@ self_refresh:
/* Set the auto-refresh enable register */
mmio_write_32(DBSC4_REG_DBRFEN, 0U);
rcar_pwrc_micro_delay(1U);
rcar_micro_delay(1U);
if (product == RCAR_PRODUCT_M3)
return;
......@@ -650,7 +633,6 @@ void rcar_pwrc_set_suspend_to_ram(void)
DEVICE_SRAM_STACK_SIZE);
uint32_t sctlr;
rcar_pwrc_code_copy_to_system_ram();
rcar_pwrc_save_generic_timer(rcar_stack_generic_timer);
/* disable MMU */
......@@ -665,10 +647,7 @@ void rcar_pwrc_init_suspend_to_ram(void)
{
#if PMIC_ROHM_BD9571
uint8_t mode;
#endif
rcar_pwrc_code_copy_to_system_ram();
#if PMIC_ROHM_BD9571
if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode))
panic();
......@@ -683,7 +662,6 @@ void rcar_pwrc_suspend_to_ram(void)
#if RCAR_SYSTEM_RESET_KEEPON_DDR
int32_t error;
rcar_pwrc_code_copy_to_system_ram();
error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, 0);
if (error) {
ERROR("Failed send KEEP10 init ret=%d \n", error);
......
drivers/renesas/rcar/scif/scif.S
View file @ 7825d719
......@@ -75,6 +75,8 @@
#if SCIF_CLK == SCIF_EXTARNAL_CLK
#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG)
#else
#define SCFSR_TEND_MASK (1 << 6)
#define SCFSR_TEND_TRANS_END (0x0040)
#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT)
#endif
#define SCFSR_INIT_DATA (0x0000)
......@@ -281,6 +283,11 @@ func console_core_putc
bcs 2b
strb w0, [x1, #SCIF_SCFTDR]
/* Clear TEND flag */
ldrh w2, [x1, #SCIF_SCFSR]
and w2, w2, #~SCFSR_TEND_MASK
strh w2, [x1, #SCIF_SCFSR]
ret
endfunc console_core_putc
......@@ -309,16 +316,12 @@ endfunc console_getc
func console_flush
ldr x0, =SCIF2_BASE
1:
ldrh w1, [x0, #SCIF_SCFDR]
ubfx w1, w1, #8, #5
cmp w1, #0
/* Check TEND flag */
ldrh w1, [x0, #SCIF_SCFSR]
and w1, w1, #SCFSR_TEND_MASK
cmp w1, #SCFSR_TEND_TRANS_END
bne 1b
mov x0, #100
mov x3, x30
bl rcar_micro_delay
mov x30, x3
ldr x0, =SCIF2_BASE
ldrh w1, [x0, #SCIF_SCSCR]
and w1, w1, #~(SCSCR_TE_EN + SCSCR_RE_EN)
......
drivers/renesas/rcar/watchdog/swdt.c
View file @ 7825d719
......@@ -133,7 +133,11 @@ void rcar_swdt_release(void)
(ARM_IRQ_SEC_WDT & ~ITARGET_MASK);
uint32_t i;
/* Disable FIQ interrupt */
write_daifset(DAIF_FIQ_BIT);
/* FIQ interrupts are not taken to EL3 */
write_scr_el3(read_scr_el3() & ~SCR_FIQ_BIT);
swdt_disable();
gicv2_cpuif_disable();
......
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
View file @ 7825d719
......@@ -48,564 +48,637 @@ static uint32_t ReadReg_32(uint32_t a)
******************************************************************************/
uint32_t init_ddr(void)
{
uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i;
uint32_t ddr_md;
/* rev.0.08 */
uint32_t RegVal,j;
uint32_t RegVal, j;
uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
uint32_t pdqsr_ctl,lcdl_ctl,lcdl_judge1,lcdl_judge2;
uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2;
/* rev.0.10 */
uint32_t pdr_ctl;
/* rev.0.11 */
uint32_t byp_ctl;
/* rev.0.08 */
if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
pdqsr_ctl = 1;
lcdl_ctl = 1;
}else {
pdr_ctl = 1; /* rev.0.10 */
byp_ctl = 1; /* rev.0.11 */
} else {
pdqsr_ctl = 0;
lcdl_ctl = 0;
pdr_ctl = 0; /* rev.0.10 */
byp_ctl = 0; /* rev.0.11 */
}
/* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
ddr_md = (ReadReg_32(RST_MODEMR)>>19)&BIT0;
ddr_md = (ReadReg_32(RST_MODEMR) >> 19) & BIT0;
/* 1584Mbps setting */
if (ddr_md==0){
if (ddr_md == 0) {
/* CPG setting ===============================================*/
WriteReg_32(CPG_CPGWPR,0x5A5AFFFF);
WriteReg_32(CPG_CPGWPCR,0xA5A50000);
WriteReg_32(CPG_CPGWPR, 0x5A5AFFFF);
WriteReg_32(CPG_CPGWPCR, 0xA5A50000);
WriteReg_32(CPG_SRCR4,0x20000000);
WriteReg_32(CPG_SRCR4, 0x20000000);
WriteReg_32(0xE61500DC,0xe2200000); /* Change to 1584Mbps */
while ( (BIT11 & ReadReg_32(CPG_PLLECR)) == 0 );
WriteReg_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */
while ((BIT11 & ReadReg_32(CPG_PLLECR)) == 0);
WriteReg_32(CPG_SRSTCLR4,0x20000000);
WriteReg_32(CPG_SRSTCLR4, 0x20000000);
WriteReg_32(CPG_CPGWPCR,0xA5A50001);
WriteReg_32(CPG_CPGWPCR, 0xA5A50001);
/* CPG setting ===============================================*/
} /* ddr_md */
WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
WriteReg_32(DBSC_E3_DBKIND,0x00000007);
WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234);
WriteReg_32(DBSC_E3_DBKIND, 0x00000007);
#if RCAR_DRAM_DDR3L_MEMCONF == 0
WriteReg_32(DBSC_E3_DBMEMCONF00,0x0f030a02); /* 1GB */
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02); /* 1GB */
#elif RCAR_DRAM_DDR3L_MEMCONF == 1
WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02); /* 2GB(default) */
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /* 2GB(default) */
#elif RCAR_DRAM_DDR3L_MEMCONF == 2
WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030b02); /* 4GB */
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030b02); /* 4GB */
#else
WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02); /* 2GB */
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /* 2GB */
#endif
#if RCAR_DRAM_DDR3L_MEMDUAL == 1
RegVal_R2 = (ReadReg_32(0xE6790614));
WriteReg_32(0xE6790614,RegVal_R2 | 0x00000003); /* MCS1_N/MODT1 are activated. */
WriteReg_32(0xE6790614, RegVal_R2 | 0x00000003); /* MCS1_N/MODT1 are activated. */
#endif
WriteReg_32(DBSC_E3_DBPHYCONF0,0x00000001);
WriteReg_32(DBSC_E3_DBPHYCONF0, 0x00000001);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBTR0,0x0000000B);
WriteReg_32(DBSC_E3_DBTR1,0x00000008);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBTR0, 0x0000000B);
WriteReg_32(DBSC_E3_DBTR1, 0x00000008);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBTR0,0x0000000D);
WriteReg_32(DBSC_E3_DBTR1,0x00000009);
WriteReg_32(DBSC_E3_DBTR0, 0x0000000D);
WriteReg_32(DBSC_E3_DBTR1, 0x00000009);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBTR2,0x00000000);
WriteReg_32(DBSC_E3_DBTR2, 0x00000000);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBTR3,0x0000000B);
WriteReg_32(DBSC_E3_DBTR4,0x000B000B);
WriteReg_32(DBSC_E3_DBTR5,0x00000027);
WriteReg_32(DBSC_E3_DBTR6,0x0000001C);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBTR3, 0x0000000B);
WriteReg_32(DBSC_E3_DBTR4, 0x000B000B);
WriteReg_32(DBSC_E3_DBTR5, 0x00000027);
WriteReg_32(DBSC_E3_DBTR6, 0x0000001C);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBTR3,0x0000000D);
WriteReg_32(DBSC_E3_DBTR4,0x000D000D);
WriteReg_32(DBSC_E3_DBTR5,0x0000002D);
WriteReg_32(DBSC_E3_DBTR6,0x00000020);
WriteReg_32(DBSC_E3_DBTR3, 0x0000000D);
WriteReg_32(DBSC_E3_DBTR4, 0x000D000D);
WriteReg_32(DBSC_E3_DBTR5, 0x0000002D);
WriteReg_32(DBSC_E3_DBTR6, 0x00000020);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBTR7,0x00060006);
WriteReg_32(DBSC_E3_DBTR7, 0x00060006);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBTR8,0x00000020);
WriteReg_32(DBSC_E3_DBTR9,0x00000006);
WriteReg_32(DBSC_E3_DBTR10,0x0000000C);
WriteReg_32(DBSC_E3_DBTR11,0x0000000A);
WriteReg_32(DBSC_E3_DBTR12,0x00120012);
WriteReg_32(DBSC_E3_DBTR13,0x000000CE);
WriteReg_32(DBSC_E3_DBTR14,0x00140005);
WriteReg_32(DBSC_E3_DBTR15,0x00050004);
WriteReg_32(DBSC_E3_DBTR16,0x071F0305);
WriteReg_32(DBSC_E3_DBTR17,0x040C0000);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBTR8, 0x00000020);
WriteReg_32(DBSC_E3_DBTR9, 0x00000006);
WriteReg_32(DBSC_E3_DBTR10, 0x0000000C);
WriteReg_32(DBSC_E3_DBTR11, 0x0000000A);
WriteReg_32(DBSC_E3_DBTR12, 0x00120012);
WriteReg_32(DBSC_E3_DBTR13, 0x000000CE);
WriteReg_32(DBSC_E3_DBTR14, 0x00140005);
WriteReg_32(DBSC_E3_DBTR15, 0x00050004);
WriteReg_32(DBSC_E3_DBTR16, 0x071F0305);
WriteReg_32(DBSC_E3_DBTR17, 0x040C0000);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBTR8,0x00000021);
WriteReg_32(DBSC_E3_DBTR9,0x00000007);
WriteReg_32(DBSC_E3_DBTR10,0x0000000E);
WriteReg_32(DBSC_E3_DBTR11,0x0000000C);
WriteReg_32(DBSC_E3_DBTR12,0x00140014);
WriteReg_32(DBSC_E3_DBTR13,0x000000F2);
WriteReg_32(DBSC_E3_DBTR14,0x00170006);
WriteReg_32(DBSC_E3_DBTR15,0x00060005);
WriteReg_32(DBSC_E3_DBTR16,0x09210507);
WriteReg_32(DBSC_E3_DBTR17,0x040E0000);
WriteReg_32(DBSC_E3_DBTR8, 0x00000021);
WriteReg_32(DBSC_E3_DBTR9, 0x00000007);
WriteReg_32(DBSC_E3_DBTR10, 0x0000000E);
WriteReg_32(DBSC_E3_DBTR11, 0x0000000C);
WriteReg_32(DBSC_E3_DBTR12, 0x00140014);
WriteReg_32(DBSC_E3_DBTR13, 0x000000F2);
WriteReg_32(DBSC_E3_DBTR14, 0x00170006);
WriteReg_32(DBSC_E3_DBTR15, 0x00060005);
WriteReg_32(DBSC_E3_DBTR16, 0x09210507);
WriteReg_32(DBSC_E3_DBTR17, 0x040E0000);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBTR18,0x00000200);
WriteReg_32(DBSC_E3_DBTR18, 0x00000200);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBTR19,0x01000040);
WriteReg_32(DBSC_E3_DBTR20,0x020000D6);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBTR19, 0x01000040);
WriteReg_32(DBSC_E3_DBTR20, 0x020000D6);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBTR19,0x0129004B);
WriteReg_32(DBSC_E3_DBTR20,0x020000FB);
WriteReg_32(DBSC_E3_DBTR19, 0x0129004B);
WriteReg_32(DBSC_E3_DBTR20, 0x020000FB);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBTR21,0x00040004);
WriteReg_32(DBSC_E3_DBBL,0x00000000);
WriteReg_32(DBSC_E3_DBODT0,0x00000001);
WriteReg_32(DBSC_E3_DBADJ0,0x00000001);
WriteReg_32(DBSC_E3_DBSYSCONF1,0x00000002);
WriteReg_32(DBSC_E3_DBDFICNT0,0x00000010);
WriteReg_32(DBSC_E3_DBBCAMDIS,0x00000001);
WriteReg_32(DBSC_E3_DBSCHRW1,0x00000046);
WriteReg_32(DBSC_E3_DBTR21, 0x00040004);
WriteReg_32(DBSC_E3_DBBL, 0x00000000);
WriteReg_32(DBSC_E3_DBODT0, 0x00000001);
WriteReg_32(DBSC_E3_DBADJ0, 0x00000001);
WriteReg_32(DBSC_E3_DBSYSCONF1, 0x00000002);
WriteReg_32(DBSC_E3_DBDFICNT0, 0x00000010);
WriteReg_32(DBSC_E3_DBBCAMDIS, 0x00000001);
WriteReg_32(DBSC_E3_DBSCHRW1, 0x00000046);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_SCFCTST0,0x0D050B03);
WriteReg_32(DBSC_E3_SCFCTST1,0x0306030C);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_SCFCTST0, 0x0D050B03);
WriteReg_32(DBSC_E3_SCFCTST1, 0x0306030C);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_SCFCTST0,0x0C050B03);
WriteReg_32(DBSC_E3_SCFCTST1,0x0305030C);
WriteReg_32(DBSC_E3_SCFCTST0, 0x0C050B03);
WriteReg_32(DBSC_E3_SCFCTST1, 0x0305030C);
} /* ddr_md */
/* rev.0.03 add Comment */
/****************************************************************************
* Initial_Step0( INITBYP )
***************************************************************************/
WriteReg_32(DBSC_E3_DBPDLK0,0x0000A55A);
WriteReg_32(DBSC_E3_DBCMD,0x01840001);
WriteReg_32(DBSC_E3_DBCMD,0x08840000);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x80010000);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDLK0, 0x0000A55A);
WriteReg_32(DBSC_E3_DBCMD, 0x01840001);
WriteReg_32(DBSC_E3_DBCMD, 0x08840000);
NOTICE("BL2: [COLD_BOOT]\n"); /* rev.0.11 */
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x80010000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
/* rev.0.03 add Comment */
/****************************************************************************
* Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training )
***************************************************************************/
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000008);
WriteReg_32(DBSC_E3_DBPDRGD0,0x000B8000);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x000B8000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x04058904);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058904);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A04);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A04);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000091);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000095);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BBAD);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000099);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000091);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000095);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BBAD);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000099);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0024641E);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00010073);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024641E);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010073);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
/* rev.0.03 add Comment */
/****************************************************************************
* Initial_Step2( DRAMRST/DRAMINT training )
***************************************************************************/
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058900);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058A00);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003);
if (byp_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C720);
} else {
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C700);
}
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007);
while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000004);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000004);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*792/125)-400 + 0x08B00000);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 792 / 125) - 400 + 0x08B00000);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*928/125)-400 + 0x0A300000);
WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 928 / 125) - 400 + 0x0A300000);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000022);
WriteReg_32(DBSC_E3_DBPDRGD0,0x1000040B);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000023);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000022);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x1000040B);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000023);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x2D9C0B66);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x2D9C0B66);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x35A00D77);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x35A00D77);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000024);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000024);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x2A88B400);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A88B400);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x2A8A2C28);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A8A2C28);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000025);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000025);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x30005200);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005200);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x30005E00);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005E00);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000026);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000026);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x0014A9C9);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014A9C9);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x0014CB49);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014CB49);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000027);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000027);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000D70);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000D70);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000F14);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000F14);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000028);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000046);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000029);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000028);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000046);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000029);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
if (ddr_md == 0) { /* 1584Mbps */
if (REFRESH_RATE > 3900) {
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000018); /* [7]SRT=0 */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000018); /* [7]SRT=0 */
} else {
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000098); /* [7]SRT=1 */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000098); /* [7]SRT=1 */
}
} else { /* 1856Mbps */
if (REFRESH_RATE > 3900) {
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000020); /* [7]SRT=0 */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000020); /* [7]SRT=0 */
} else {
WriteReg_32(DBSC_E3_DBPDRGD0,0x000000A0); /* [7]SRT=1 */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x000000A0); /* [7]SRT=1 */
} /* REFRESH_RATE */
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
WriteReg_32(DBSC_E3_DBPDRGD0,0x81003047);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000020);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00181884);
WriteReg_32(DBSC_E3_DBPDRGA0,0x0000001A);
WriteReg_32(DBSC_E3_DBPDRGD0,0x33C03C10);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A7);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A8);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A9);
WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C7);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C8);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C9);
WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E7);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E8);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E9);
WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000107);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000108);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000109);
WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00010181);
WriteReg_32(DBSC_E3_DBCMD,0x08840001);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003047);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000020);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00181884);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000001A);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x33C03C10);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A7);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A8);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A9);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C7);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C8);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C9);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E7);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E8);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E9);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000107);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000108);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000109);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010181);
WriteReg_32(DBSC_E3_DBCMD, 0x08840001);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
/* rev.0.03 add Comment */
/****************************************************************************
* Initial_Step3( WL/QSG training )
***************************************************************************/
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00010601);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010601);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
/* rev.0.03 add Comment */
/****************************************************************************
* Initial_Step4( WLADJ training )
***************************************************************************/
for ( i = 0; i<4; i++){
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
for (i = 0; i < 4; i++) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8;
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20);
RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20);
RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
if ( RegVal_R6 > 0 ){
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
if (RegVal_R6 > 0) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R6);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R6);
} else {
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R7);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R7);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
} /* RegVal_R6 */
} /* for i */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00C0);
/* rev.0.10 move Comment */
/****************************************************************************
* Initial_Step4( WLADJ training )
***************************************************************************/
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005);
WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00C0);
/* rev.0.08 */
if (pdqsr_ctl == 1){}else{
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
if (pdqsr_ctl == 1){} else {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
}
/* PDR always off */ /* rev.0.10 */
if (pdr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
}
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00010801);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010801);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
/* rev.0.03 add Comment */
/****************************************************************************
* Initial_Step5678( RdWrbitRdWreye )
* Initial_Step5(Read Data Bit Deskew)
***************************************************************************/
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00D8);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005);
WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00D8);
/* rev.0.08 */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00011001);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
if (pdqsr_ctl == 1){
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00011001);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
if (pdqsr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
}
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00012001);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
if (pdqsr_ctl == 1){
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
/* PDR dynamic */ /* rev.0.10 */
if (pdr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
}
/****************************************************************************
* Initial_Step6(Write Data Bit Deskew)
***************************************************************************/
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00012001);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
/****************************************************************************
* Initial_Step7(Read Data Eye Training)
***************************************************************************/
if (pdqsr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
}
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00014001);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
if (pdqsr_ctl == 1){
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
/* PDR always off */ /* rev.0.10 */
if (pdr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
}
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00014001);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
if (pdqsr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
}
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00018001);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
/* PDR dynamic */ /* rev.0.10 */
if (pdr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
}
/* rev.0.03 add Comment */
/****************************************************************************
* Initial_Step3_2( DQS Gate Training )
* Initial_Step8(Write Data Eye Training)
***************************************************************************/
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
WriteReg_32(DBSC_E3_DBPDRGD0,0x81003087);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00010401);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00018001);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
/* rev.0.03 add Comment */
/****************************************************************************
* Initial_Step5-2_7-2( Rd bit Rd eye )
* Initial_Step3_2( DQS Gate Training )
***************************************************************************/
for ( i = 0; i < 4; i++){
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003087);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010401);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
for (i = 0; i < 4; i++) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20);
RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20);
RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
RegVal_R12 = (RegVal_R5 >> 0x2);
if ( RegVal_R12 < RegVal_R6 ){
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
if (RegVal_R12 < RegVal_R6) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
} else {
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007));
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
} /* RegVal_R12 < RegVal_R6 */
} /* for i */
/* rev.0.10 move Comment */
/****************************************************************************
* Initial_Step5-2_7-2( Rd bit Rd eye )
***************************************************************************/
/* rev.0.08 */
if (pdqsr_ctl == 1){}else{
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
if (pdqsr_ctl == 1){} else {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
}
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00015001);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
/* PDR always off */ /* rev.0.10 */
if (pdr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
}
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00015001);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
/* rev.0.08 */
if (lcdl_ctl == 1){
for (i=0; i< 4; i++) {
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
if (lcdl_ctl == 1) {
for (i = 0; i < 4; i++) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8);
bdlcount_0c_div2 = (bdlcount_0c >> 1);
bdlcount_0c_div4 = (bdlcount_0c >> 2);
bdlcount_0c_div8 = (bdlcount_0c >> 3);
bdlcount_0c_div16 = (bdlcount_0c >> 4);
if (ddr_md==0){ /* 1584Mbps */
lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8 ;
lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16 ;
if (ddr_md == 0) { /* 1584Mbps */
lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8;
lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16;
} else { /* 1856Mbps */
lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 ;
lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 ;
lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4;
lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4;
} /* ddr_md */
if (dqsgd_0c > lcdl_judge1) {
if (dqsgd_0c <= lcdl_judge2) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
WriteReg_32(DBSC_E3_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal));
WriteReg_32(DBSC_E3_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal));
} else {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
......@@ -614,135 +687,148 @@ if (pdqsr_ctl == 1){
gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal|(gatesl_0c + 1)));
WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal | (gatesl_0c + 1)));
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16)));
WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16)));
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
rbd_0c[0] = (RegVal ) & 0x0000001f;
rbd_0c[0] = (RegVal) &0x0000001f;
rbd_0c[1] = (RegVal >> 8) & 0x0000001f;
rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
for (j=0; j< 4; j++) {
for (j = 0; j < 4; j++) {
rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
RegVal = RegVal | (rbd_0c[j] <<8*j);
RegVal = RegVal | (rbd_0c[j] << 8 * j);
}
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
rbd_0c[0] = (RegVal ) & 0x0000001f;
rbd_0c[0] = (RegVal) &0x0000001f;
rbd_0c[1] = (RegVal >> 8) & 0x0000001f;
rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
for (j=0; j< 4; j++) {
for (j = 0; j < 4; j++) {
rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
RegVal = RegVal | (rbd_0c[j] <<8*j);
RegVal = RegVal | (rbd_0c[j] << 8 * j);
}
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
}
}
}
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000002);
WriteReg_32(DBSC_E3_DBPDRGD0,0x07D81E37);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000002);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x07D81E37);
}
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003);
if (byp_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C720);
} else {
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C700);
}
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007);
while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0 );
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0024643E);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024643E);
WriteReg_32(DBSC_E3_DBBUS0CNF1,0x00000010);
WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000/REFRESH_RATE) + 0x01000000);
WriteReg_32(DBSC_E3_DBBUS0CNF1, 0x00000010);
WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000 / REFRESH_RATE) + 0x01000000);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*99/125) + 0x00080000);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 99 / 125) + 0x00080000);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*116/125) + 0x00080000);
WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 116 / 125) + 0x00080000);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBRFCNF2,0x00010000);
WriteReg_32(DBSC_E3_DBDFICUPDCNF,0x40100001);
WriteReg_32(DBSC_E3_DBRFEN,0x00000001);
WriteReg_32(DBSC_E3_DBACEN,0x00000001);
WriteReg_32(DBSC_E3_DBRFCNF2, 0x00010000);
WriteReg_32(DBSC_E3_DBDFICUPDCNF, 0x40100001);
WriteReg_32(DBSC_E3_DBRFEN, 0x00000001);
WriteReg_32(DBSC_E3_DBACEN, 0x00000001);
/* rev.0.08 */
if (pdqsr_ctl == 1){
WriteReg_32(0xE67F0018,0x00000001);
if (pdqsr_ctl == 1) {
WriteReg_32(0xE67F0018, 0x00000001);
RegVal = ReadReg_32(0x40000000);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000000);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
}
/* PDR dynamic */ /* rev.0.10 */
if (pdr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
}
/* rev.0.03 add Comment */
/****************************************************************************
* Initial_Step9( Initial End )
***************************************************************************/
WriteReg_32(DBSC_E3_DBPDLK0,0x00000000);
WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
WriteReg_32(DBSC_E3_DBPDLK0, 0x00000000);
WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000);
#ifdef ddr_qos_init_setting /* only for non qos_init */
WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
WriteReg_32(DBSC_E3_DBCAM0CNF1,0x00043218);
WriteReg_32(DBSC_E3_DBCAM0CNF2,0x000000F4);
WriteReg_32(DBSC_E3_DBSCHCNT0,0x000f0037);
WriteReg_32(DBSC_E3_DBSCHSZ0,0x00000001);
WriteReg_32(DBSC_E3_DBSCHRW0,0x22421111);
WriteReg_32(DBSC_E3_SCFCTST2,0x012F1123);
WriteReg_32(DBSC_E3_DBSCHQOS00,0x00000F00);
WriteReg_32(DBSC_E3_DBSCHQOS01,0x00000B00);
WriteReg_32(DBSC_E3_DBSCHQOS02,0x00000000);
WriteReg_32(DBSC_E3_DBSCHQOS03,0x00000000);
WriteReg_32(DBSC_E3_DBSCHQOS40,0x00000300);
WriteReg_32(DBSC_E3_DBSCHQOS41,0x000002F0);
WriteReg_32(DBSC_E3_DBSCHQOS42,0x00000200);
WriteReg_32(DBSC_E3_DBSCHQOS43,0x00000100);
WriteReg_32(DBSC_E3_DBSCHQOS90,0x00000100);
WriteReg_32(DBSC_E3_DBSCHQOS91,0x000000F0);
WriteReg_32(DBSC_E3_DBSCHQOS92,0x000000A0);
WriteReg_32(DBSC_E3_DBSCHQOS93,0x00000040);
WriteReg_32(DBSC_E3_DBSCHQOS130,0x00000100);
WriteReg_32(DBSC_E3_DBSCHQOS131,0x000000F0);
WriteReg_32(DBSC_E3_DBSCHQOS132,0x000000A0);
WriteReg_32(DBSC_E3_DBSCHQOS133,0x00000040);
WriteReg_32(DBSC_E3_DBSCHQOS140,0x000000C0);
WriteReg_32(DBSC_E3_DBSCHQOS141,0x000000B0);
WriteReg_32(DBSC_E3_DBSCHQOS142,0x00000080);
WriteReg_32(DBSC_E3_DBSCHQOS143,0x00000040);
WriteReg_32(DBSC_E3_DBSCHQOS150,0x00000040);
WriteReg_32(DBSC_E3_DBSCHQOS151,0x00000030);
WriteReg_32(DBSC_E3_DBSCHQOS152,0x00000020);
WriteReg_32(DBSC_E3_DBSCHQOS153,0x00000010);
WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234);
WriteReg_32(DBSC_E3_DBCAM0CNF1, 0x00043218);
WriteReg_32(DBSC_E3_DBCAM0CNF2, 0x000000F4);
WriteReg_32(DBSC_E3_DBSCHCNT0, 0x000f0037);
WriteReg_32(DBSC_E3_DBSCHSZ0, 0x00000001);
WriteReg_32(DBSC_E3_DBSCHRW0, 0x22421111);
WriteReg_32(DBSC_E3_SCFCTST2, 0x012F1123);
WriteReg_32(DBSC_E3_DBSCHQOS00, 0x00000F00);
WriteReg_32(DBSC_E3_DBSCHQOS01, 0x00000B00);
WriteReg_32(DBSC_E3_DBSCHQOS02, 0x00000000);
WriteReg_32(DBSC_E3_DBSCHQOS03, 0x00000000);
WriteReg_32(DBSC_E3_DBSCHQOS40, 0x00000300);
WriteReg_32(DBSC_E3_DBSCHQOS41, 0x000002F0);
WriteReg_32(DBSC_E3_DBSCHQOS42, 0x00000200);
WriteReg_32(DBSC_E3_DBSCHQOS43, 0x00000100);
WriteReg_32(DBSC_E3_DBSCHQOS90, 0x00000100);
WriteReg_32(DBSC_E3_DBSCHQOS91, 0x000000F0);
WriteReg_32(DBSC_E3_DBSCHQOS92, 0x000000A0);
WriteReg_32(DBSC_E3_DBSCHQOS93, 0x00000040);
WriteReg_32(DBSC_E3_DBSCHQOS130, 0x00000100);
WriteReg_32(DBSC_E3_DBSCHQOS131, 0x000000F0);
WriteReg_32(DBSC_E3_DBSCHQOS132, 0x000000A0);
WriteReg_32(DBSC_E3_DBSCHQOS133, 0x00000040);
WriteReg_32(DBSC_E3_DBSCHQOS140, 0x000000C0);
WriteReg_32(DBSC_E3_DBSCHQOS141, 0x000000B0);
WriteReg_32(DBSC_E3_DBSCHQOS142, 0x00000080);
WriteReg_32(DBSC_E3_DBSCHQOS143, 0x00000040);
WriteReg_32(DBSC_E3_DBSCHQOS150, 0x00000040);
WriteReg_32(DBSC_E3_DBSCHQOS151, 0x00000030);
WriteReg_32(DBSC_E3_DBSCHQOS152, 0x00000020);
WriteReg_32(DBSC_E3_DBSCHQOS153, 0x00000010);
/* rev.0.08 */
if (pdqsr_ctl == 1){}else{
WriteReg_32(0xE67F0018,0x00000001);
if (pdqsr_ctl == 1){} else {
WriteReg_32(0xE67F0018, 0x00000001);
}
WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000);
#endif
return 1; /* rev.0.04 Restore the return code */
......@@ -752,7 +838,6 @@ if (pdqsr_ctl == 1){
/* rev.0.04 add function */
uint32_t recovery_from_backup_mode(void)
{
/****************************************************************************
* recovery_Step0(DBSC Setting 1) / same "init_ddr"
***************************************************************************/
......@@ -760,608 +845,672 @@ uint32_t recovery_from_backup_mode(void)
uint32_t ddr_md;
uint32_t err;
/* rev.0.08 */
uint32_t RegVal,j;
uint32_t RegVal, j;
uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
uint32_t pdqsr_ctl,lcdl_ctl,lcdl_judge1,lcdl_judge2;
uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2;
/* rev.0.10 */
uint32_t pdr_ctl;
/* rev.0.11 */
uint32_t byp_ctl;
/* rev.0.08 */
if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
pdqsr_ctl = 1;
lcdl_ctl = 1;
}else {
pdr_ctl = 1; /* rev.0.10 */
byp_ctl = 1; /* rev.0.11 */
} else {
pdqsr_ctl = 0;
lcdl_ctl = 0;
pdr_ctl = 0; /* rev.0.10 */
byp_ctl = 0; /* rev.0.11 */
}
/* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
ddr_md = (ReadReg_32(RST_MODEMR)>>19)&BIT0;
ddr_md = (ReadReg_32(RST_MODEMR) >> 19) & BIT0;
/* 1584Mbps setting */
if (ddr_md==0){
if (ddr_md == 0) {
/* CPG setting ===============================================*/
WriteReg_32(CPG_CPGWPR,0x5A5AFFFF);
WriteReg_32(CPG_CPGWPCR,0xA5A50000);
WriteReg_32(CPG_CPGWPR, 0x5A5AFFFF);
WriteReg_32(CPG_CPGWPCR, 0xA5A50000);
WriteReg_32(CPG_SRCR4,0x20000000);
WriteReg_32(CPG_SRCR4, 0x20000000);
WriteReg_32(0xE61500DC,0xe2200000); /* Change to 1584Mbps */
while ( (BIT11 & ReadReg_32(CPG_PLLECR)) == 0 );
WriteReg_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */
while ((BIT11 & ReadReg_32(CPG_PLLECR)) == 0);
WriteReg_32(CPG_SRSTCLR4,0x20000000);
WriteReg_32(CPG_SRSTCLR4, 0x20000000);
WriteReg_32(CPG_CPGWPCR,0xA5A50001);
WriteReg_32(CPG_CPGWPCR, 0xA5A50001);
/* CPG setting ===============================================*/
} /* ddr_md */
WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
WriteReg_32(DBSC_E3_DBKIND,0x00000007);
WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234);
WriteReg_32(DBSC_E3_DBKIND, 0x00000007);
#if RCAR_DRAM_DDR3L_MEMCONF == 0
WriteReg_32(DBSC_E3_DBMEMCONF00,0x0f030a02);
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02);
#elif RCAR_DRAM_DDR3L_MEMCONF == 1
WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02);
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02);
#elif RCAR_DRAM_DDR3L_MEMCONF == 2
WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030b02);
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030b02);
#else
WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02);
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02);
#endif
/* rev.0.08 */
#if RCAR_DRAM_DDR3L_MEMDUAL == 1
RegVal_R2 = (ReadReg_32(0xE6790614));
WriteReg_32(0xE6790614,RegVal_R2 | 0x00000003); /* MCS1_N/MODT1 are activated. */
WriteReg_32(0xE6790614, RegVal_R2 | 0x00000003); /* MCS1_N/MODT1 are activated. */
#endif
WriteReg_32(DBSC_E3_DBPHYCONF0,0x00000001);
WriteReg_32(DBSC_E3_DBPHYCONF0, 0x00000001);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBTR0,0x0000000B);
WriteReg_32(DBSC_E3_DBTR1,0x00000008);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBTR0, 0x0000000B);
WriteReg_32(DBSC_E3_DBTR1, 0x00000008);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBTR0,0x0000000D);
WriteReg_32(DBSC_E3_DBTR1,0x00000009);
WriteReg_32(DBSC_E3_DBTR0, 0x0000000D);
WriteReg_32(DBSC_E3_DBTR1, 0x00000009);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBTR2,0x00000000);
WriteReg_32(DBSC_E3_DBTR2, 0x00000000);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBTR3,0x0000000B);
WriteReg_32(DBSC_E3_DBTR4,0x000B000B);
WriteReg_32(DBSC_E3_DBTR5,0x00000027);
WriteReg_32(DBSC_E3_DBTR6,0x0000001C);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBTR3, 0x0000000B);
WriteReg_32(DBSC_E3_DBTR4, 0x000B000B);
WriteReg_32(DBSC_E3_DBTR5, 0x00000027);
WriteReg_32(DBSC_E3_DBTR6, 0x0000001C);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBTR3,0x0000000D);
WriteReg_32(DBSC_E3_DBTR4,0x000D000D);
WriteReg_32(DBSC_E3_DBTR5,0x0000002D);
WriteReg_32(DBSC_E3_DBTR6,0x00000020);
WriteReg_32(DBSC_E3_DBTR3, 0x0000000D);
WriteReg_32(DBSC_E3_DBTR4, 0x000D000D);
WriteReg_32(DBSC_E3_DBTR5, 0x0000002D);
WriteReg_32(DBSC_E3_DBTR6, 0x00000020);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBTR7,0x00060006);
WriteReg_32(DBSC_E3_DBTR7, 0x00060006);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBTR8,0x00000020);
WriteReg_32(DBSC_E3_DBTR9,0x00000006);
WriteReg_32(DBSC_E3_DBTR10,0x0000000C);
WriteReg_32(DBSC_E3_DBTR11,0x0000000A);
WriteReg_32(DBSC_E3_DBTR12,0x00120012);
WriteReg_32(DBSC_E3_DBTR13,0x000000CE);
WriteReg_32(DBSC_E3_DBTR14,0x00140005);
WriteReg_32(DBSC_E3_DBTR15,0x00050004);
WriteReg_32(DBSC_E3_DBTR16,0x071F0305);
WriteReg_32(DBSC_E3_DBTR17,0x040C0000);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBTR8, 0x00000020);
WriteReg_32(DBSC_E3_DBTR9, 0x00000006);
WriteReg_32(DBSC_E3_DBTR10, 0x0000000C);
WriteReg_32(DBSC_E3_DBTR11, 0x0000000A);
WriteReg_32(DBSC_E3_DBTR12, 0x00120012);
WriteReg_32(DBSC_E3_DBTR13, 0x000000CE);
WriteReg_32(DBSC_E3_DBTR14, 0x00140005);
WriteReg_32(DBSC_E3_DBTR15, 0x00050004);
WriteReg_32(DBSC_E3_DBTR16, 0x071F0305);
WriteReg_32(DBSC_E3_DBTR17, 0x040C0000);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBTR8,0x00000021);
WriteReg_32(DBSC_E3_DBTR9,0x00000007);
WriteReg_32(DBSC_E3_DBTR10,0x0000000E);
WriteReg_32(DBSC_E3_DBTR11,0x0000000C);
WriteReg_32(DBSC_E3_DBTR12,0x00140014);
WriteReg_32(DBSC_E3_DBTR13,0x000000F2);
WriteReg_32(DBSC_E3_DBTR14,0x00170006);
WriteReg_32(DBSC_E3_DBTR15,0x00060005);
WriteReg_32(DBSC_E3_DBTR16,0x09210507);
WriteReg_32(DBSC_E3_DBTR17,0x040E0000);
WriteReg_32(DBSC_E3_DBTR8, 0x00000021);
WriteReg_32(DBSC_E3_DBTR9, 0x00000007);
WriteReg_32(DBSC_E3_DBTR10, 0x0000000E);
WriteReg_32(DBSC_E3_DBTR11, 0x0000000C);
WriteReg_32(DBSC_E3_DBTR12, 0x00140014);
WriteReg_32(DBSC_E3_DBTR13, 0x000000F2);
WriteReg_32(DBSC_E3_DBTR14, 0x00170006);
WriteReg_32(DBSC_E3_DBTR15, 0x00060005);
WriteReg_32(DBSC_E3_DBTR16, 0x09210507);
WriteReg_32(DBSC_E3_DBTR17, 0x040E0000);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBTR18,0x00000200);
WriteReg_32(DBSC_E3_DBTR18, 0x00000200);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBTR19,0x01000040);
WriteReg_32(DBSC_E3_DBTR20,0x020000D6);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBTR19, 0x01000040);
WriteReg_32(DBSC_E3_DBTR20, 0x020000D6);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBTR19,0x0129004B);
WriteReg_32(DBSC_E3_DBTR20,0x020000FB);
WriteReg_32(DBSC_E3_DBTR19, 0x0129004B);
WriteReg_32(DBSC_E3_DBTR20, 0x020000FB);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBTR21,0x00040004);
WriteReg_32(DBSC_E3_DBBL,0x00000000);
WriteReg_32(DBSC_E3_DBODT0,0x00000001);
WriteReg_32(DBSC_E3_DBADJ0,0x00000001);
WriteReg_32(DBSC_E3_DBSYSCONF1,0x00000002);
WriteReg_32(DBSC_E3_DBDFICNT0,0x00000010);
WriteReg_32(DBSC_E3_DBBCAMDIS,0x00000001);
WriteReg_32(DBSC_E3_DBSCHRW1,0x00000046);
WriteReg_32(DBSC_E3_DBTR21, 0x00040004);
WriteReg_32(DBSC_E3_DBBL, 0x00000000);
WriteReg_32(DBSC_E3_DBODT0, 0x00000001);
WriteReg_32(DBSC_E3_DBADJ0, 0x00000001);
WriteReg_32(DBSC_E3_DBSYSCONF1, 0x00000002);
WriteReg_32(DBSC_E3_DBDFICNT0, 0x00000010);
WriteReg_32(DBSC_E3_DBBCAMDIS, 0x00000001);
WriteReg_32(DBSC_E3_DBSCHRW1, 0x00000046);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_SCFCTST0,0x0D050B03);
WriteReg_32(DBSC_E3_SCFCTST1,0x0306030C);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_SCFCTST0, 0x0D050B03);
WriteReg_32(DBSC_E3_SCFCTST1, 0x0306030C);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_SCFCTST0,0x0C050B03);
WriteReg_32(DBSC_E3_SCFCTST1,0x0305030C);
WriteReg_32(DBSC_E3_SCFCTST0, 0x0C050B03);
WriteReg_32(DBSC_E3_SCFCTST1, 0x0305030C);
} /* ddr_md */
/****************************************************************************
* recovery_Step1(PHY setting 1)
***************************************************************************/
WriteReg_32(DBSC_E3_DBPDLK0,0x0000A55A);
WriteReg_32(DBSC_E3_DBCMD,0x01840001);
WriteReg_32(DBSC_E3_DBCMD,0x0A840000);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000008); /* DDR_PLLCR */
WriteReg_32(DBSC_E3_DBPDRGD0,0x000B8000);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003); /* DDR_PGCR1 */
WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000020); /* DDR_DXCCR */
WriteReg_32(DBSC_E3_DBPDRGD0,0x00181884);
WriteReg_32(DBSC_E3_DBPDRGA0,0x0000001A); /* DDR_ACIOCR0 */
WriteReg_32(DBSC_E3_DBPDRGD0,0x33C03C10);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000004);
WriteReg_32(DBSC_E3_DBPDLK0, 0x0000A55A);
WriteReg_32(DBSC_E3_DBCMD, 0x01840001);
WriteReg_32(DBSC_E3_DBCMD, 0x0A840000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000008); /* DDR_PLLCR */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x000B8000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003); /* DDR_PGCR1 */
if (byp_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C720);
} else {
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C700);
}
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000020); /* DDR_DXCCR */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00181884);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000001A); /* DDR_ACIOCR0 */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x33C03C10);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007);
while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000004);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*792/125)-400 + 0x08B00000);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 792 / 125) - 400 + 0x08B00000);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*928/125)-400 + 0x0A300000);
WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 928 / 125) - 400 + 0x0A300000);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000022);
WriteReg_32(DBSC_E3_DBPDRGD0,0x1000040B);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000023);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000022);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x1000040B);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000023);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x2D9C0B66);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x2D9C0B66);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x35A00D77);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x35A00D77);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000024);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000024);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x2A88B400);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A88B400);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x2A8A2C28);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A8A2C28);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000025);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000025);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x30005200);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005200);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x30005E00);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005E00);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000026);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000026);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x0014A9C9);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014A9C9);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x0014CB49);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014CB49);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000027);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000027);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000D70);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000D70);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000F14);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000F14);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000028);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000046);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000029);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000028);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000046);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000029);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
if (ddr_md == 0) { /* 1584Mbps */
if (REFRESH_RATE > 3900) {
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000018); /* [7]SRT=0 */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000018); /* [7]SRT=0 */
} else {
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000098); /* [7]SRT=1 */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000098); /* [7]SRT=1 */
}
} else { /* 1856Mbps */
if (REFRESH_RATE > 3900) {
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000020); /* [7]SRT=0 */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000020); /* [7]SRT=0 */
} else {
WriteReg_32(DBSC_E3_DBPDRGD0,0x000000A0); /* [7]SRT=1 */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x000000A0); /* [7]SRT=1 */
} /* REFRESH_RATE */
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
WriteReg_32(DBSC_E3_DBPDRGD0,0x81003047);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000091);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000095);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BBAD);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000099);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021); /* DDR_DSGCR */
WriteReg_32(DBSC_E3_DBPDRGD0,0x0024641E);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
WriteReg_32(DBSC_E3_DBPDRGD0,0x40010000);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000092); /* DDR_ZQ0DR */
WriteReg_32(DBSC_E3_DBPDRGD0,0xC2C59AB5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000096); /* DDR_ZQ1DR */
WriteReg_32(DBSC_E3_DBPDRGD0,0xC4285FBF);
WriteReg_32(DBSC_E3_DBPDRGA0,0x0000009A); /* DDR_ZQ2DR */
WriteReg_32(DBSC_E3_DBPDRGD0,0xC2C59AB5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /* DDR_ZQCR */
WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003047);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000091);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000095);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BBAD);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000099);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021); /* DDR_DSGCR */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024641E);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x40010000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */
WriteReg_32(DBSC_E3_DBPDRGD0, 0xC2C59AB5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */
WriteReg_32(DBSC_E3_DBPDRGD0, 0xC4285FBF);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */
WriteReg_32(DBSC_E3_DBPDRGD0, 0xC2C59AB5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058900);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058A00);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /* DDR_ZQCR */
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
WriteReg_32(DBSC_E3_DBPDRGD0,0x00050001);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00050001);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
/* ddr backupmode end */
if(ddrBackup) {
if (ddrBackup) {
NOTICE("[WARM_BOOT]");
} else {
NOTICE("[COLD_BOOT]");
} /* ddrBackup */
err=rcar_dram_update_boot_status(ddrBackup);
if(err){
err = rcar_dram_update_boot_status(ddrBackup);
if (err) {
NOTICE("[BOOT_STATUS_UPDATE_ERROR]");
return INITDRAM_ERR_I;
} /* err */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000092); /* DDR_ZQ0DR */
WriteReg_32(DBSC_E3_DBPDRGD0,0x02C59AB5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000096); /* DDR_ZQ1DR */
WriteReg_32(DBSC_E3_DBPDRGD0,0x04285FBF);
WriteReg_32(DBSC_E3_DBPDRGA0,0x0000009A); /* DDR_ZQ2DR */
WriteReg_32(DBSC_E3_DBPDRGD0,0x02C59AB5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x02C59AB5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x04285FBF);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x02C59AB5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
WriteReg_32(DBSC_E3_DBPDRGD0,0x08000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x08000000);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000003);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000003);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
WriteReg_32(DBSC_E3_DBPDRGD0,0x80010000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x80010000);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
WriteReg_32(DBSC_E3_DBPDRGD0,0x00010073);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010073);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /* DDR_ZQCR */
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058900);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058A00);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /* DDR_ZQCR */
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00);
} /* ddr_md */
/* rev0.08 */
WriteReg_32(DBSC_E3_DBPDRGA0,0x0000000C);
WriteReg_32(DBSC_E3_DBPDRGD0,0x18000040);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000000C);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x18000040);
/****************************************************************************
* recovery_Step2(PHY setting 2)
***************************************************************************/
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A7);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A8);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A9);
WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C7);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C8);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C9);
WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E7);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E8);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E9);
WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000107);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000108);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000109);
WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000/REFRESH_RATE) + 0x01000000);
WriteReg_32(DBSC_E3_DBBUS0CNF1,0x00000010);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A7);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A8);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A9);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C7);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C8);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C9);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E7);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E8);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E9);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000107);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000108);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000109);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000 / REFRESH_RATE) + 0x01000000);
WriteReg_32(DBSC_E3_DBBUS0CNF1, 0x00000010);
/* Select setting value in bps */
if (ddr_md==0){ /* 1584Mbps */
WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*99/125) + 0x00080000);
if (ddr_md == 0) { /* 1584Mbps */
WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 99 / 125) + 0x00080000);
} else { /* 1856Mbps */
WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*116/125) + 0x00080000);
WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 116 / 125) + 0x00080000);
} /* ddr_md */
WriteReg_32(DBSC_E3_DBRFCNF2,0x00010000);
WriteReg_32(DBSC_E3_DBRFEN,0x00000001);
WriteReg_32(DBSC_E3_DBCMD,0x0A840001);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0 );
WriteReg_32(DBSC_E3_DBRFCNF2, 0x00010000);
WriteReg_32(DBSC_E3_DBRFEN, 0x00000001);
WriteReg_32(DBSC_E3_DBCMD, 0x0A840001);
while ((BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0);
WriteReg_32(DBSC_E3_DBCMD,0x00000000);
WriteReg_32(DBSC_E3_DBCMD, 0x00000000);
WriteReg_32(DBSC_E3_DBCMD,0x04840010);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0 );
WriteReg_32(DBSC_E3_DBCMD, 0x04840010);
while ((BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
WriteReg_32(DBSC_E3_DBPDRGD0,0x00010701);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010701);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
for ( i = 0; i<4; i++)
for (i = 0; i < 4; i++)
{
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8;
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20);
RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20);
RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
if ( RegVal_R6 > 0 ){
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
if (RegVal_R6 > 0) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R6);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R6);
} else {
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R7);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R7);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
} /* RegVal_R6 */
} /* for i */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00C0);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005);
WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00C0);
/* rev.0.08 */
if (pdqsr_ctl == 1){}else{
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
if (pdqsr_ctl == 1){} else {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
}
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00010801);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
/* PDR always off */ /* rev.0.10 */
if (pdr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
}
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00D8);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010801);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005);
WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00D8);
/* rev.0.08 */
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00011001);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
if (pdqsr_ctl == 1){
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00011001);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
if (pdqsr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
}
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00012001);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
if (pdqsr_ctl == 1){
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
/* PDR dynamic */ /* rev.0.10 */
if (pdr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
}
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00012001);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
if (pdqsr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
}
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00014001);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
if (pdqsr_ctl == 1){
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
/* PDR always off */ /* rev.0.10 */
if (pdr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
}
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00014001);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
if (pdqsr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
}
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00018001);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
WriteReg_32(DBSC_E3_DBPDRGD0,0x81003087);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00010401);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
for ( i = 0; i < 4; i++){
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
/* PDR dynamic */ /* rev.0.10 */
if (pdr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
}
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00018001);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003087);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010401);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
for (i = 0; i < 4; i++) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20);
RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20);
RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
RegVal_R12 = (RegVal_R5 >> 0x2);
if ( RegVal_R12 < RegVal_R6 ){
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
if (RegVal_R12 < RegVal_R6) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
} else {
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007));
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
} /* RegVal_R12 < RegVal_R6 */
} /* for i */
/* rev.0.08 */
if (pdqsr_ctl == 1){}else{
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
if (pdqsr_ctl == 1){} else {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
}
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0,0x00015001);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
/* PDR always off */ /* rev.0.10 */
if (pdr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
}
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00015001);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
/* rev.0.08 */
if (lcdl_ctl == 1){
for (i=0; i< 4; i++) {
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
if (lcdl_ctl == 1) {
for (i = 0; i < 4; i++) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8);
bdlcount_0c_div2 = (bdlcount_0c >> 1);
bdlcount_0c_div4 = (bdlcount_0c >> 2);
bdlcount_0c_div8 = (bdlcount_0c >> 3);
bdlcount_0c_div16 = (bdlcount_0c >> 4);
if (ddr_md==0){ /* 1584Mbps */
lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8 ;
lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16 ;
if (ddr_md == 0) { /* 1584Mbps */
lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8;
lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16;
} else { /* 1856Mbps */
lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 ;
lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 ;
lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4;
lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4;
} /* ddr_md */
if (dqsgd_0c > lcdl_judge1) {
if (dqsgd_0c <= lcdl_judge2) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
WriteReg_32(DBSC_E3_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal));
WriteReg_32(DBSC_E3_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal));
} else {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
......@@ -1370,123 +1519,136 @@ if (pdqsr_ctl == 1){
gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal|(gatesl_0c + 1)));
WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal | (gatesl_0c + 1)));
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16)));
WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16)));
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
rbd_0c[0] = (RegVal ) & 0x0000001f;
rbd_0c[0] = (RegVal) &0x0000001f;
rbd_0c[1] = (RegVal >> 8) & 0x0000001f;
rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
for (j=0; j< 4; j++) {
for (j = 0; j < 4; j++) {
rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
RegVal = RegVal | (rbd_0c[j] <<8*j);
RegVal = RegVal | (rbd_0c[j] << 8 * j);
}
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
rbd_0c[0] = (RegVal ) & 0x0000001f;
rbd_0c[0] = (RegVal) &0x0000001f;
rbd_0c[1] = (RegVal >> 8) & 0x0000001f;
rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
for (j=0; j< 4; j++) {
for (j = 0; j < 4; j++) {
rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
RegVal = RegVal | (rbd_0c[j] <<8*j);
RegVal = RegVal | (rbd_0c[j] << 8 * j);
}
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
}
}
}
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000002);
WriteReg_32(DBSC_E3_DBPDRGD0,0x07D81E37);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000002);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x07D81E37);
}
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0 );
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021);
WriteReg_32(DBSC_E3_DBPDRGD0,0x0024643E);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003);
if (byp_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C720);
} else {
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C700);
}
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007);
while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024643E);
/****************************************************************************
* recovery_Step3(DBSC Setting 2)
***************************************************************************/
WriteReg_32(DBSC_E3_DBDFICUPDCNF,0x40100001);
WriteReg_32(DBSC_E3_DBACEN,0x00000001);
WriteReg_32(DBSC_E3_DBDFICUPDCNF, 0x40100001);
WriteReg_32(DBSC_E3_DBACEN, 0x00000001);
/* rev.0.08 */
if (pdqsr_ctl == 1){
WriteReg_32(0xE67F0018,0x00000001);
if (pdqsr_ctl == 1) {
WriteReg_32(0xE67F0018, 0x00000001);
RegVal = ReadReg_32(0x40000000);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000000);
WriteReg_32(DBSC_E3_DBPDRGD0,RegVal);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
}
/* PDR dynamic */ /* rev.0.10 */
if (pdr_ctl == 1) {
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
}
WriteReg_32(DBSC_E3_DBPDLK0,0x00000000);
WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
WriteReg_32(DBSC_E3_DBPDLK0, 0x00000000);
WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000);
#ifdef ddr_qos_init_setting /* only for non qos_init */
WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
WriteReg_32(DBSC_E3_DBCAM0CNF1,0x00043218);
WriteReg_32(DBSC_E3_DBCAM0CNF2,0x000000F4);
WriteReg_32(DBSC_E3_DBSCHCNT0,0x000f0037);
WriteReg_32(DBSC_E3_DBSCHSZ0,0x00000001);
WriteReg_32(DBSC_E3_DBSCHRW0,0x22421111);
WriteReg_32(DBSC_E3_SCFCTST2,0x012F1123);
WriteReg_32(DBSC_E3_DBSCHQOS00,0x00000F00);
WriteReg_32(DBSC_E3_DBSCHQOS01,0x00000B00);
WriteReg_32(DBSC_E3_DBSCHQOS02,0x00000000);
WriteReg_32(DBSC_E3_DBSCHQOS03,0x00000000);
WriteReg_32(DBSC_E3_DBSCHQOS40,0x00000300);
WriteReg_32(DBSC_E3_DBSCHQOS41,0x000002F0);
WriteReg_32(DBSC_E3_DBSCHQOS42,0x00000200);
WriteReg_32(DBSC_E3_DBSCHQOS43,0x00000100);
WriteReg_32(DBSC_E3_DBSCHQOS90,0x00000100);
WriteReg_32(DBSC_E3_DBSCHQOS91,0x000000F0);
WriteReg_32(DBSC_E3_DBSCHQOS92,0x000000A0);
WriteReg_32(DBSC_E3_DBSCHQOS93,0x00000040);
WriteReg_32(DBSC_E3_DBSCHQOS130,0x00000100);
WriteReg_32(DBSC_E3_DBSCHQOS131,0x000000F0);
WriteReg_32(DBSC_E3_DBSCHQOS132,0x000000A0);
WriteReg_32(DBSC_E3_DBSCHQOS133,0x00000040);
WriteReg_32(DBSC_E3_DBSCHQOS140,0x000000C0);
WriteReg_32(DBSC_E3_DBSCHQOS141,0x000000B0);
WriteReg_32(DBSC_E3_DBSCHQOS142,0x00000080);
WriteReg_32(DBSC_E3_DBSCHQOS143,0x00000040);
WriteReg_32(DBSC_E3_DBSCHQOS150,0x00000040);
WriteReg_32(DBSC_E3_DBSCHQOS151,0x00000030);
WriteReg_32(DBSC_E3_DBSCHQOS152,0x00000020);
WriteReg_32(DBSC_E3_DBSCHQOS153,0x00000010);
WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234);
WriteReg_32(DBSC_E3_DBCAM0CNF1, 0x00043218);
WriteReg_32(DBSC_E3_DBCAM0CNF2, 0x000000F4);
WriteReg_32(DBSC_E3_DBSCHCNT0, 0x000f0037);
WriteReg_32(DBSC_E3_DBSCHSZ0, 0x00000001);
WriteReg_32(DBSC_E3_DBSCHRW0, 0x22421111);
WriteReg_32(DBSC_E3_SCFCTST2, 0x012F1123);
WriteReg_32(DBSC_E3_DBSCHQOS00, 0x00000F00);
WriteReg_32(DBSC_E3_DBSCHQOS01, 0x00000B00);
WriteReg_32(DBSC_E3_DBSCHQOS02, 0x00000000);
WriteReg_32(DBSC_E3_DBSCHQOS03, 0x00000000);
WriteReg_32(DBSC_E3_DBSCHQOS40, 0x00000300);
WriteReg_32(DBSC_E3_DBSCHQOS41, 0x000002F0);
WriteReg_32(DBSC_E3_DBSCHQOS42, 0x00000200);
WriteReg_32(DBSC_E3_DBSCHQOS43, 0x00000100);
WriteReg_32(DBSC_E3_DBSCHQOS90, 0x00000100);
WriteReg_32(DBSC_E3_DBSCHQOS91, 0x000000F0);
WriteReg_32(DBSC_E3_DBSCHQOS92, 0x000000A0);
WriteReg_32(DBSC_E3_DBSCHQOS93, 0x00000040);
WriteReg_32(DBSC_E3_DBSCHQOS130, 0x00000100);
WriteReg_32(DBSC_E3_DBSCHQOS131, 0x000000F0);
WriteReg_32(DBSC_E3_DBSCHQOS132, 0x000000A0);
WriteReg_32(DBSC_E3_DBSCHQOS133, 0x00000040);
WriteReg_32(DBSC_E3_DBSCHQOS140, 0x000000C0);
WriteReg_32(DBSC_E3_DBSCHQOS141, 0x000000B0);
WriteReg_32(DBSC_E3_DBSCHQOS142, 0x00000080);
WriteReg_32(DBSC_E3_DBSCHQOS143, 0x00000040);
WriteReg_32(DBSC_E3_DBSCHQOS150, 0x00000040);
WriteReg_32(DBSC_E3_DBSCHQOS151, 0x00000030);
WriteReg_32(DBSC_E3_DBSCHQOS152, 0x00000020);
WriteReg_32(DBSC_E3_DBSCHQOS153, 0x00000010);
/* rev.0.08 */
if (pdqsr_ctl == 1){}else{
WriteReg_32(0xE67F0018,0x00000001);
if (pdqsr_ctl == 1){} else {
WriteReg_32(0xE67F0018, 0x00000001);
}
WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000);
#endif
return 1;
......@@ -1504,35 +1666,34 @@ int32_t rcar_dram_init(void)
{
uint32_t dataL;
uint32_t failcount;
uint32_t md=0;
uint32_t ddr=0;
uint32_t md = 0;
uint32_t ddr = 0;
md = *((volatile uint32_t*)RST_MODEMR);
ddr = (md & 0x00080000) >> 19;
if(ddr == 0x0){
if (ddr == 0x0) {
NOTICE("BL2: DDR1584(%s)", RCAR_E3_DDR_VERSION);
}
else if(ddr == 0x1){
} else if(ddr == 0x1){
NOTICE("BL2: DDR1856(%s)", RCAR_E3_DDR_VERSION);
} /* ddr */
rcar_dram_get_boot_status(&ddrBackup);
if(ddrBackup==DRAM_BOOT_STATUS_WARM){
dataL=recovery_from_backup_mode(); /* WARM boot */
if (ddrBackup == DRAM_BOOT_STATUS_WARM) {
dataL = recovery_from_backup_mode(); /* WARM boot */
} else {
dataL=init_ddr(); /* COLD boot */
dataL = init_ddr(); /* COLD boot */
} /* ddrBackup */
if(dataL==1){
failcount =0;
if (dataL == 1) {
failcount = 0;
} else {
failcount =1;
failcount = 1;
} /* dataL */
NOTICE("..%d\n",failcount); /* rev.0.05 */
NOTICE("..%d\n", failcount); /* rev.0.05 */
if(failcount==0){
if (failcount == 0) {
return INITDRAM_OK;
} else {
return INITDRAM_NG;
......
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
View file @ 7825d719
......@@ -9,7 +9,7 @@
#include <stdint.h>
#define RCAR_E3_DDR_VERSION "rev.0.09"
#define RCAR_E3_DDR_VERSION "rev.0.11"
#ifdef ddr_qos_init_setting
#define REFRESH_RATE 3900 /* Average periodic refresh interval[ns]. Support 3900,7800 */
......
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
View file @ 7825d719
......@@ -87,21 +87,11 @@ static uint32_t ddr_mbps;
static uint32_t ddr_mbpsdiv;
static uint32_t ddr_tccd;
static struct _boardcnf *Boardcnf;
uint32_t ddr_phyvalid;
uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
static uint32_t ddr_phyvalid;
static uint32_t ddr_phycaslice;
static volatile uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
static uint32_t ch_have_this_cs[CS_CNT];
static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2];
static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
static uint32_t max_density;
static uint32_t ddr0800_mul;
static uint32_t ddr_mul;
......@@ -260,9 +250,6 @@ static void ddr_setval_ach(uint32_t regdef, uint32_t val);
static void ddr_setval_ach_as(uint32_t regdef, uint32_t val);
static uint32_t ddr_getval(uint32_t ch, uint32_t regdef);
static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p);
/* NOT USED
static uint32_t ddr_getval_ach_s(uint32_t slice, uint32_t regdef, uint32_t *p);
*/
static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p);
static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size);
static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val);
......@@ -284,7 +271,7 @@ static void dbsc_regset_post(void);
static uint32_t dfi_init_start(void);
static void change_lpddr4_en(uint32_t mode);
static uint32_t set_term_code(void);
static void ddr_register_set(uint32_t ch);
static void ddr_register_set(void);
static inline uint32_t wait_freqchgreq(uint32_t assert);
static inline void set_freqchgack(uint32_t assert);
static inline void set_dfifrequency(uint32_t freq);
......@@ -293,12 +280,8 @@ static void update_dly(void);
static uint32_t pi_training_go(void);
static uint32_t init_ddr(void);
static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick);
static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
static uint32_t wdqdm_man1(void);
static uint32_t wdqdm_man(void);
static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
static uint32_t rdqdm_man1(void);
static uint32_t rdqdm_man(void);
......@@ -325,6 +308,24 @@ static void ddr_padcal_tcompensate_getinit(uint32_t override);
******************************************************************************/
#include "boot_init_dram_config.c"
#ifndef DDR_FAST_INIT
static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2];
static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
#endif/* DDR_FAST_INIT */
/*******************************************************************************
* macro for channel selection loop
******************************************************************************/
......@@ -363,71 +364,69 @@ static void pll3_control(uint32_t high)
{
uint32_t dataL, dataDIV, dataMUL, tmpDIV;
/* PLL3 disable */
dataL = mmio_read_32(CPG_PLLECR);
dataL &= ~CPG_PLLECR_PLL3E_BIT;
cpg_write_32(CPG_PLLECR, dataL);
dsb_sev();
cpg_write_32(CPG_FRQCRD, 0x00030003); /* PLL3 DIV resetting */
dsb_sev();
/* PLL3 enable */
dataL = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR);
cpg_write_32(CPG_ZB3CKCR, dataL); /* zb3 clk stop */
dsb_sev();
/* PLL3 Restart */
dataL = mmio_read_32(CPG_PLLECR);
dataL |= CPG_PLLECR_PLL3E_BIT;
cpg_write_32(CPG_PLLECR, dataL);
dsb_sev();
do {
dataL = mmio_read_32(CPG_PLLECR);
} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
dsb_sev();
if (high) {
/* High frequency */
tmpDIV =
(1000 * ddr_mbpsdiv * brd_clkdiv * (brd_clkdiva + 1)) /
(ddr_mul * brd_clk * ddr_mbpsdiv + 1);
dataMUL =
((ddr_mul * (tmpDIV + 1) - 1) << 24) | (brd_clkdiva << 7);
if (tmpDIV) {
dataDIV = tmpDIV + 1;
} else {
dataDIV = 0;
}
(ddr_mul * (tmpDIV + 1) - 1) << 24;
Pll3Mode = 1;
loop_max = 2;
} else {
/* Low frequency */
tmpDIV =
(1000 * ddr_mbpsdiv * brd_clkdiv * (brd_clkdiva + 1)) /
(ddr0800_mul * brd_clk * ddr_mbpsdiv + 1);
dataMUL =
((ddr0800_mul * (tmpDIV + 1) -
1) << 24) | (brd_clkdiva << 7);
(ddr0800_mul * (tmpDIV + 1) - 1) << 24;
Pll3Mode = 0;
loop_max = 8;
}
if (tmpDIV) {
dataDIV = tmpDIV + 1;
} else {
dataDIV = 0;
}
Pll3Mode = 0;
loop_max = 8;
}
dataMUL = dataMUL | (brd_clkdiva << 7);
/* PLL3 disable */
dataL = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT;
cpg_write_32(CPG_PLLECR, dataL);
dsb_sev();
if ((Prr_Product == PRR_PRODUCT_M3) ||
((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_20))) {
/* PLL3 DIV resetting(Lowest value:3) */
dataL = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
cpg_write_32(CPG_FRQCRD, dataL);
dsb_sev();
/* zb3 clk stop */
dataL = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR);
cpg_write_32(CPG_ZB3CKCR, dataL);
dsb_sev();
/* PLL3 enable */
dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
cpg_write_32(CPG_PLLECR, dataL);
dsb_sev();
do {
dataL = mmio_read_32(CPG_PLLECR);
} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
dsb_sev();
/* PLL3 DIV resetting (Highest value:0) */
dataL = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
cpg_write_32(CPG_FRQCRD, dataL); /* PLL3 DIV resetting */
cpg_write_32(CPG_FRQCRD, dataL);
dsb_sev();
/* DIV SET KICK */
dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
cpg_write_32(CPG_FRQCRB, dataL); /* DIV SET KICK */
cpg_write_32(CPG_FRQCRB, dataL);
dsb_sev();
/* PLL3 FREQ */
cpg_write_32(CPG_PLL3CR, dataMUL); /* Set PLL3 freq */
/* PLL3 multiplie set */
cpg_write_32(CPG_PLL3CR, dataMUL);
dsb_sev();
do {
......@@ -435,13 +434,14 @@ static void pll3_control(uint32_t high)
} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
dsb_sev();
dataL =
(dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
cpg_write_32(CPG_FRQCRD, dataL); /* PLL3 DIV resetting */
/* PLL3 DIV resetting(Target value) */
dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
cpg_write_32(CPG_FRQCRD, dataL);
dsb_sev();
/* DIV SET KICK */
dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
cpg_write_32(CPG_FRQCRB, dataL); /* DIV SET KICK */
cpg_write_32(CPG_FRQCRB, dataL);
dsb_sev();
do {
......@@ -449,10 +449,37 @@ static void pll3_control(uint32_t high)
} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
dsb_sev();
/* zb3 clk start */
dataL = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR);
cpg_write_32(CPG_ZB3CKCR, dataL); /* zb3 clk start */
cpg_write_32(CPG_ZB3CKCR, dataL);
dsb_sev();
} else { /* H3Ver.3.0/M3N/V3H */
/* PLL3 multiplie set */
cpg_write_32(CPG_PLL3CR, dataMUL);
dsb_sev();
/* PLL3 DIV set(Target value) */
dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
cpg_write_32(CPG_FRQCRD, dataL);
/* DIV SET KICK */
dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
cpg_write_32(CPG_FRQCRB, dataL);
dsb_sev();
/* PLL3 enable */
dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
cpg_write_32(CPG_PLLECR, dataL);
dsb_sev();
do {
dataL = mmio_read_32(CPG_PLLECR);
} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
dsb_sev();
}
return;
}
......@@ -647,11 +674,6 @@ static inline uint32_t ddr_regdef_lsb(uint32_t _regdef)
return DDR_REGDEF_LSB(pDDR_REGDEF_TBL[_regdef]);
}
static inline uint32_t ddr_regdef_len(uint32_t _regdef)
{
return DDR_REGDEF_LEN(pDDR_REGDEF_TBL[_regdef]);
}
static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
uint32_t val)
{
......@@ -740,17 +762,6 @@ static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p)
return p[0];
}
/* NOT_USED
static uint32_t ddr_getval_ach_s(uint32_t slice, uint32_t regdef, uint32_t *p)
{
uint32_t ch;
foreach_vch(ch)
p[ch] = ddr_getval_s(ch, slice, regdef);
return p[0];
}
*/
static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p)
{
uint32_t ch, slice;
......@@ -925,9 +936,8 @@ struct _jedec_spec2 {
#define JS2_tRCpb (JS2_TBLCNT)
#define JS2_tRCab (JS2_TBLCNT+1)
#define JS2_tRFCpb (JS2_TBLCNT+2)
#define JS2_tRFCab (JS2_TBLCNT+3)
#define JS2_CNT (JS2_TBLCNT+4)
#define JS2_tRFCab (JS2_TBLCNT+2)
#define JS2_CNT (JS2_TBLCNT+3)
#ifndef JS2_DERATE
#define JS2_DERATE 0
......@@ -982,13 +992,9 @@ const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = {
}
};
/* pb, ab */
const uint16_t jedec_spec2_tRFC_pb_ab[2][7] = {
const uint16_t jedec_spec2_tRFC_ab[7] = {
/* 4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non) */
{
60, 90, 90, 140, 140, 280, 280},
{
130, 180, 180, 280, 280, 560, 560}
130, 180, 180, 280, 280, 560, 560
};
static uint32_t js1_ind;
......@@ -1409,46 +1415,26 @@ static void ddrtbl_load(void)
}
/***********************************************************************
Adjust PI paramters
Adjust PI parameters
***********************************************************************/
#ifdef _def_LPDDR4_ODT
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F0_0,
_def_LPDDR4_ODT);
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F0_1,
_def_LPDDR4_ODT);
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F0_2,
_def_LPDDR4_ODT);
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F0_3,
_def_LPDDR4_ODT);
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F1_0,
_def_LPDDR4_ODT);
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F1_1,
_def_LPDDR4_ODT);
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F1_2,
_def_LPDDR4_ODT);
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F1_3,
for (i = 0; i < 2; i++) {
for (csab = 0; csab < CSAB_CNT; csab++) {
ddrtbl_setval(_cnf_DDR_PI_REGSET,
_reg_PI_MR11_DATA_Fx_CSx[i][csab],
_def_LPDDR4_ODT);
}
}
#endif /* _def_LPDDR4_ODT */
#ifdef _def_LPDDR4_VREFCA
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_0,
_def_LPDDR4_VREFCA);
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_1,
_def_LPDDR4_VREFCA);
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_2,
_def_LPDDR4_VREFCA);
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_3,
_def_LPDDR4_VREFCA);
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_0,
_def_LPDDR4_VREFCA);
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_1,
_def_LPDDR4_VREFCA);
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_2,
_def_LPDDR4_VREFCA);
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_3,
for (i = 0; i < 2; i++) {
for (csab = 0; csab < CSAB_CNT; csab++) {
ddrtbl_setval(_cnf_DDR_PI_REGSET,
_reg_PI_MR12_DATA_Fx_CSx[i][csab],
_def_LPDDR4_VREFCA);
}
}
#endif /* _def_LPDDR4_VREFCA */
if ((Prr_Product == PRR_PRODUCT_M3N)
|| (Prr_Product == PRR_PRODUCT_V3H)) {
......@@ -1563,6 +1549,32 @@ static void ddrtbl_load(void)
reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]);
}
if (((Prr_Product == PRR_PRODUCT_M3)
|| (Prr_Product == PRR_PRODUCT_M3N)) &&
((0x00ffffff & (uint32_t)((Boardcnf->ch[0].ca_swap) >> 40))
!= 0x00)) {
adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE;
for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
reg_ddrphy_write_a(adr + i,
_cnf_DDR_PHY_ADR_V_REGSET[i]);
}
ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_ADR_DISABLE, 0x02);
DDR_PHY_ADR_I_NUM -= 1;
ddr_phycaslice = 1;
#ifndef _def_LPDDR4_ODT
for (i = 0; i < 2; i++) {
for (csab = 0; csab < CSAB_CNT; csab++) {
ddrtbl_setval(_cnf_DDR_PI_REGSET,
_reg_PI_MR11_DATA_Fx_CSx[i][csab],
0x66);
}
}
#endif/* _def_LPDDR4_ODT */
} else {
ddr_phycaslice = 0;
}
if (DDR_PHY_ADR_I_NUM > 0) {
for (slice = 0; slice < DDR_PHY_ADR_I_NUM; slice++) {
adr =
......@@ -1631,7 +1643,9 @@ static void ddr_config_sub(void)
BOARD SETTINGS (CA,ADDR_SEL)
***********************************************************************/
const uint32_t _par_CALVL_DEVICE_MAP = 1;
dataL = Boardcnf->ch[ch].ca_swap | 0x00888888;
dataL = (0x00ffffff & (uint32_t)(Boardcnf->ch[ch].ca_swap)) |
0x00888888;
/* --- ADR_CALVL_SWIZZLE --- */
if (Prr_Product == PRR_PRODUCT_M3) {
......@@ -1663,6 +1677,38 @@ static void ddr_config_sub(void)
}
}
ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, dataL);
if (ddr_phycaslice == 1) {
/* ----------- adr slice2 swap ----------- */
tmp = (uint32_t)((Boardcnf->ch[ch].ca_swap) >> 40);
dataL = (tmp & 0x00ffffff) | 0x00888888;
/* --- ADR_CALVL_SWIZZLE --- */
if (Prr_Product == PRR_PRODUCT_M3) {
ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL);
ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_0,
0x00000000);
ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL);
ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_1,
0x00000000);
ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_DEVICE_MAP,
_par_CALVL_DEVICE_MAP);
} else {
ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL);
ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1,
0x00000000);
ddr_setval_s(ch, 2, _reg_PHY_CALVL_DEVICE_MAP,
_par_CALVL_DEVICE_MAP);
}
/* --- ADR_ADDR_SEL --- */
dataL = 0;
for (i = 0; i < 6; i++) {
dataL |= ((tmp & 0x0f) << (i * 5));
tmp = tmp >> 4;
}
ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, dataL);
}
/***********************************************************************
BOARD SETTINGS (BYTE_ORDER_SEL)
......@@ -1710,7 +1756,7 @@ static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz)
if (tgt == tmp)
break;
}
tmp = Boardcnf->ch[ch].ca_swap;
tmp = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap;
if (slice % 2)
tmp |= 0x00888888;
*p_swz = tmp;
......@@ -1755,7 +1801,7 @@ static void ddr_config_sub_h3v1x(void)
/***********************************************************************
BOARD SETTINGS (CA,ADDR_SEL)
***********************************************************************/
ca = Boardcnf->ch[ch].ca_swap;
ca = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap;
ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca);
ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap);
......@@ -1864,6 +1910,16 @@ static void ddr_config(void)
ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
dataL + adj);
}
if (ddr_phycaslice == 1) {
for (i = 0; i < 6; i++) {
adj =
_f_scale_adj(Boardcnf->ch[ch].cacs_adj[i +
_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
ddr_setval_s(ch, 2,
_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
dataL + adj);
}
}
}
set_dfifrequency(0x00);
......@@ -1974,20 +2030,13 @@ static void dbsc_regset(void)
/* RFC */
if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_20)
&& (max_density == 0)) {
js2[JS2_tRFCpb] =
_f_scale(ddr_mbps, ddr_mbpsdiv,
1UL * jedec_spec2_tRFC_pb_ab[0][1] * 1000, 0);
js2[JS2_tRFCab] =
_f_scale(ddr_mbps, ddr_mbpsdiv,
1UL * jedec_spec2_tRFC_pb_ab[1][1] * 1000, 0);
1UL * jedec_spec2_tRFC_ab[1] * 1000, 0);
} else {
js2[JS2_tRFCpb] = _f_scale(ddr_mbps, ddr_mbpsdiv,
1UL *
jedec_spec2_tRFC_pb_ab[0]
[max_density] * 1000, 0);
js2[JS2_tRFCab] =
_f_scale(ddr_mbps, ddr_mbpsdiv,
1UL * jedec_spec2_tRFC_pb_ab[1][max_density] *
1UL * jedec_spec2_tRFC_ab[max_density] *
1000, 0);
}
......@@ -2032,7 +2081,7 @@ static void dbsc_regset(void)
dataL = WL + 1 + (16 / 2) + js2[JS2_tWTR];
mmio_write_32(DBSC_DBTR(12), (dataL << 16) | dataL);
/* DBTR13.TRFCPB,TRFCAB : tRFCpb, tRFCab */
/* DBTR13.TRFCAB : tRFCab */
mmio_write_32(DBSC_DBTR(13), (js2[JS2_tRFCab]));
/* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */
......@@ -2061,7 +2110,11 @@ static void dbsc_regset(void)
/* WRCSGAP = 5 */
tmp[1] = 5;
/* RDCSLAT = RDLAT_ADJ +2 */
if (Prr_Product == PRR_PRODUCT_M3) {
tmp[2] = tmp[3];
} else {
tmp[2] = tmp[3] + 2;
}
/* RDCSGAP = 6 */
if (Prr_Product == PRR_PRODUCT_M3) {
tmp[3] = 4;
......@@ -2428,20 +2481,7 @@ static uint32_t dfi_init_start(void)
uint32_t dataL;
const uint32_t RETRY_MAX = 0x10000;
/***********************************************************************
set IE=1 when init_start_disable==0
***********************************************************************/
if (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_CAL_MODE_0) &
0x01) {
ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00);
} else {
ddr_setval_ach_as(_reg_PHY_IE_MODE,
ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
_reg_PHY_IE_MODE));
}
if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
/***********************************************************************
PLL3 Disable
***********************************************************************/
......@@ -2535,8 +2575,8 @@ static void change_lpddr4_en(uint32_t mode)
_reg_PHY_PAD_CS_DRIVE
};
for (i = 0; i < 3; i++) {
foreach_vch(ch) {
for (i = 0; i < 3; i++) {
dataL = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]);
if (mode) {
dataL |= (1U << 14);
......@@ -2591,9 +2631,6 @@ static uint32_t set_term_code(void)
&& (Prr_Cut == PRR_PRODUCT_10)) {
/* non */
} else {
ddr_setval_ach_as(_reg_PHY_IE_MODE,
ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
_reg_PHY_IE_MODE));
ddr_setval_ach(_reg_PHY_PAD_TERM_X[0],
(ddrtbl_getval
(_cnf_DDR_PHY_ADR_G_REGSET,
......@@ -2664,48 +2701,46 @@ static uint32_t set_term_code(void)
/*******************************************************************************
* DDR mode register setting
******************************************************************************/
static void ddr_register_set(uint32_t ch)
static void ddr_register_set(void)
{
int32_t fspwp;
uint32_t chind;
uint32_t tmp;
chind = ch << 20;
for (fspwp = 1; fspwp >= 0; fspwp--) {
/*MR13,fspwp */
send_dbcmd(0x0e040d08 | chind | (fspwp << 6));
send_dbcmd(0x0e840d08 | (fspwp << 6));
tmp =
ddrtbl_getval(_cnf_DDR_PI_REGSET,
_reg_PI_MR1_DATA_Fx_CSx[fspwp][0]);
send_dbcmd(0x0e040100 | chind | tmp);
send_dbcmd(0x0e840100 | tmp);
tmp =
ddrtbl_getval(_cnf_DDR_PI_REGSET,
_reg_PI_MR2_DATA_Fx_CSx[fspwp][0]);
send_dbcmd(0x0e040200 | chind | tmp);
send_dbcmd(0x0e840200 | tmp);
tmp =
ddrtbl_getval(_cnf_DDR_PI_REGSET,
_reg_PI_MR3_DATA_Fx_CSx[fspwp][0]);
send_dbcmd(0x0e040300 | chind | tmp);
send_dbcmd(0x0e840300 | tmp);
tmp =
ddrtbl_getval(_cnf_DDR_PI_REGSET,
_reg_PI_MR11_DATA_Fx_CSx[fspwp][0]);
send_dbcmd(0x0e040b00 | chind | tmp);
send_dbcmd(0x0e840b00 | tmp);
tmp =
ddrtbl_getval(_cnf_DDR_PI_REGSET,
_reg_PI_MR12_DATA_Fx_CSx[fspwp][0]);
send_dbcmd(0x0e040c00 | chind | tmp);
send_dbcmd(0x0e840c00 | tmp);
tmp =
ddrtbl_getval(_cnf_DDR_PI_REGSET,
_reg_PI_MR14_DATA_Fx_CSx[fspwp][0]);
send_dbcmd(0x0e040e00 | chind | tmp);
send_dbcmd(0x0e840e00 | tmp);
/* MR22 */
send_dbcmd(0x0e041600 | chind | 0x16);
send_dbcmd(0x0e841616);
}
}
......@@ -2904,7 +2939,7 @@ static uint32_t init_ddr(void)
int32_t i;
uint32_t dataL;
uint32_t phytrainingok;
uint32_t ch;
uint32_t ch, slice;
uint32_t err;
MSG_LF("init_ddr:0\n");
......@@ -3011,12 +3046,8 @@ static uint32_t init_ddr(void)
return (INITDRAM_ERR_O);
MSG_LF("init_ddr:5\n");
/***********************************************************************
set ie_mode=1
***********************************************************************/
ddr_setval_ach_as(_reg_PHY_IE_MODE,
ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
_reg_PHY_IE_MODE));
/* PDX */
send_dbcmd(0x08840001);
/***********************************************************************
check register i/f is alive
......@@ -3037,38 +3068,22 @@ static uint32_t init_ddr(void)
/* CMOS MODE */
change_lpddr4_en(0);
ch = 0x08;
/* PDE */
send_dbcmd(0x08040000 | (0x00100000 * ch));
/* PDX */
send_dbcmd(0x08040001 | (0x00100000 * ch));
/* MR22 (ODTCS & RQZ */
send_dbcmd(0x0e041600 | (0x00100000 * ch) | 0x16);
/* MRS */
ddr_register_set();
/* ZQCAL start */
send_dbcmd(0x0d04004F | (0x00100000 * ch));
rcar_micro_delay(100);
send_dbcmd(0x0d84004F);
/* ZQLAT */
send_dbcmd(0x0d040051 | (0x00100000 * ch));
send_dbcmd(0x0d840051);
/***********************************************************************
Thermal sensor setting
***********************************************************************/
/* THCTR Bit6: PONM=0 , Bit0: THSST=1 */
dataL =
((*((volatile uint32_t *)THS1_THCTR)) & 0xFFFFFFBF) | 0x00000001;
*((volatile uint32_t *)THS1_THCTR) = dataL;
dataL = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001;
mmio_write_32(THS1_THCTR, dataL);
/***********************************************************************
setup DDR mode registers
***********************************************************************/
foreach_vch(ch) {
ddr_register_set(ch);
}
/* LPDDR4 MODE */
change_lpddr4_en(1);
......@@ -3079,8 +3094,6 @@ static uint32_t init_ddr(void)
***********************************************************************/
foreach_vch(ch) {
dataL = ddr_getval(ch, _reg_PI_CS_MAP);
if (!(ch_have_this_cs[0] & (1U << ch)))
dataL = dataL & 0x0a;
if (!(ch_have_this_cs[1] & (1U << ch)))
dataL = dataL & 0x05;
ddr_setval(ch, _reg_PI_CS_MAP, dataL);
......@@ -3090,7 +3103,19 @@ static uint32_t init_ddr(void)
exec pi_training
***********************************************************************/
ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00);
if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01);
} else {
foreach_vch(ch) {
for (slice = 0; slice < SLICE_CNT; slice++) {
ddr_setval_s(ch, slice,
_reg_PHY_PER_CS_TRAINING_EN,
((ch_have_this_cs[1]) >> ch)
& 0x01);
}
}
}
phytrainingok = pi_training_go();
......@@ -3111,7 +3136,17 @@ static uint32_t init_ddr(void)
ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
dataL + adj);
}
if (ddr_phycaslice == 1) {
for (i = 0; i < 6; i++) {
adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
ddr_setval_s(ch, 2, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
dataL + adj
);
}
}
}
update_dly();
MSG_LF("init_ddr:9\n");
......@@ -3132,15 +3167,16 @@ static uint32_t init_ddr(void)
/***********************************************************************
RDQLVL Training
***********************************************************************/
if ((Prr_Product == PRR_PRODUCT_H3) || (Prr_Product == PRR_PRODUCT_M3)) {
if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) {
ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01);
} else {
ddr_setval_ach_as(_reg_PHY_IE_MODE,
ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
_reg_PHY_IE_MODE));
}
err = rdqdm_man();
if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) {
ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00);
}
if (err) {
return (INITDRAM_ERR_T);
}
......@@ -3229,6 +3265,7 @@ static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick)
/*******************************************************************************
* WDQ TRAINING
******************************************************************************/
#ifndef DDR_FAST_INIT
static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
{
int32_t i, k;
......@@ -3284,7 +3321,6 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
cs = ddr_csn % 2;
ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX);
for (i = 0; i < 9; i++) {
dq = slice * 8 + i;
if (i == 8)
......@@ -3325,10 +3361,16 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
err = 2;
}
wdqdm_win[ch][cs][slice] = min_win;
if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x01);
} else {
ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
((ch_have_this_cs[1]) >> ch) & 0x01);
}
}
return err;
}
#endif/* DDR_FAST_INIT */
static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore)
{
......@@ -3375,14 +3417,16 @@ static uint32_t wdqdm_man1(void)
uint32_t ddr_csn;
uint32_t dataL;
uint32_t err;
uint32_t high_dq[DRAM_CH_CNT];
uint32_t mr14_csab0_bak[DRAM_CH_CNT];
#ifndef DDR_FAST_INIT
uint32_t err_flg;
#endif/* DDR_FAST_INIT */
/***********************************************************************
manual execution of training
***********************************************************************/
uint32_t high_dq[DRAM_CH_CNT];
uint32_t mr14_csab0_bak[DRAM_CH_CNT];
if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
foreach_vch(ch) {
high_dq[ch] = 0;
for (slice = 0; slice < SLICE_CNT; slice++) {
......@@ -3390,11 +3434,9 @@ static uint32_t wdqdm_man1(void)
if (k >= 2)
high_dq[ch] |= (1U << slice);
}
ddr_setval(ch, _reg_PI_16BIT_DRAM_CONNECT, 0x00);
}
}
if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x00);
err = 0;
/* CLEAR PREV RESULT */
for (cs = 0; cs < CS_CNT; cs++) {
......@@ -3412,8 +3454,9 @@ static uint32_t wdqdm_man1(void)
}
ddrphy_regif_idle();
#ifndef DDR_FAST_INIT
err_flg = 0;
#endif/* DDR_FAST_INIT */
for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
if ((Prr_Product == PRR_PRODUCT_H3)
&& (Prr_Cut <= PRR_PRODUCT_11)) {
......@@ -3458,6 +3501,7 @@ static uint32_t wdqdm_man1(void)
ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0],
mr14_csab0_bak[ch]);
}
#ifndef DDR_FAST_INIT
foreach_vch(ch) {
if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) {
wdqdm_clr1(ch, ddr_csn);
......@@ -3468,8 +3512,13 @@ static uint32_t wdqdm_man1(void)
err_flg |= (1U << (ddr_csn * 4 + ch));
ddrphy_regif_idle();
}
#endif/* DDR_FAST_INIT */
}
err_exit:
#ifndef DDR_FAST_INIT
err |= err_flg;
#endif/* DDR_FAST_INIT */
if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01);
foreach_vch(ch) {
dataL = mmio_read_32(DBSC_DBDFICNT(ch));
......@@ -3477,7 +3526,8 @@ err_exit:
mmio_write_32(DBSC_DBDFICNT(ch), dataL);
ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00);
}
return (err_flg | err);
}
return (err);
}
static uint32_t wdqdm_man(void)
......@@ -3591,6 +3641,7 @@ static uint32_t wdqdm_man(void)
/*******************************************************************************
* RDQ TRAINING
******************************************************************************/
#ifndef DDR_FAST_INIT
static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
{
int32_t i, k;
......@@ -3740,11 +3791,15 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
}
return (err);
}
#endif/* DDR_FAST_INIT */
static uint32_t rdqdm_man1(void)
{
uint32_t ch;
uint32_t ddr_csn;
#ifdef DDR_FAST_INIT
uint32_t slice;
#endif/* DDR_FAST_INIT */
uint32_t err;
/***********************************************************************
......@@ -3752,12 +3807,12 @@ static uint32_t rdqdm_man1(void)
***********************************************************************/
err = 0;
for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
for (ddr_csn = 0; ddr_csn < CS_CNT; ddr_csn++) {
/* KICK RDQLVL */
err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ);
if (err)
goto err_exit;
#ifndef DDR_FAST_INIT
foreach_vch(ch) {
if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) {
rdqdm_clr1(ch, ddr_csn);
......@@ -3769,7 +3824,50 @@ static uint32_t rdqdm_man1(void)
if (err)
goto err_exit;
}
#else/* DDR_FAST_INIT */
foreach_vch(ch) {
if (ch_have_this_cs[ddr_csn] & (1U << ch)) {
for (slice = 0; slice < SLICE_CNT; slice++) {
if (ddr_getval_s(ch, slice,
_reg_PHY_RDLVL_STATUS_OBS) !=
0x0D00FFFF) {
err = (1U << ch) |
(0x10U << slice);
goto err_exit;
}
}
}
if (((Prr_Product == PRR_PRODUCT_H3)
&& (Prr_Cut <= PRR_PRODUCT_11))
|| ((Prr_Product == PRR_PRODUCT_M3)
&& (Prr_Cut <= PRR_PRODUCT_10))) {
uint32_t i, adj, dataL;
for (slice = 0; slice < SLICE_CNT; slice++) {
for (i = 0; i <= 8; i++) {
if (i == 8)
adj = _f_scale_adj(Boardcnf->ch[ch].dm_adj_r[slice]);
else
adj = _f_scale_adj(Boardcnf->ch[ch].dq_adj_r[slice * 8 + i]);
ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn);
dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], dataL);
rdqdm_dly[ch][ddr_csn][slice][i] = dataL;
rdqdm_dly[ch][ddr_csn | 1][slice][i] = dataL;
dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], dataL);
rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = dataL;
rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = dataL;
}
}
}
}
ddrphy_regif_idle();
#endif/* DDR_FAST_INIT */
}
err_exit:
return (err);
}
......@@ -3867,7 +3965,6 @@ static uint32_t _rx_offset_cal_updn(uint32_t code)
return tmp;
}
/* #define RX_OFFSET_FAST */
static uint32_t rx_offset_cal(void)
{
uint32_t index;
......@@ -3878,11 +3975,7 @@ static uint32_t rx_offset_cal(void)
uint32_t tmp;
uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM];
#ifdef RX_OFFSET_FAST
uint32_t adr_st;
adr_st = ddr_regdef_adr(_reg_PHY_RX_CAL_X[0]);
#endif
ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01);
ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01);
foreach_vch(ch) {
for (slice = 0; slice < SLICE_CNT; slice++) {
......@@ -3894,19 +3987,9 @@ static uint32_t rx_offset_cal(void)
for (code = 0; code < CODE_MAX / CODE_STEP; code++) {
tmp = _rx_offset_cal_updn(code * CODE_STEP);
#ifdef RX_OFFSET_FAST
tmp = tmp | (tmp << 16);
for (index = 0; index < (_reg_PHY_RX_CAL_X_NUM + 1) / 2;
index++) {
for (slice = 0; slice < 4; slice++)
reg_ddrphy_write_a(adr_st + 0x80 * slice +
index, tmp);
}
#else
for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) {
ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp);
}
#endif
dsb_sev();
ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *) tmp_ach_as);
......@@ -3945,9 +4028,6 @@ static uint32_t rx_offset_cal(void)
}
}
ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
ddr_setval_ach_as(_reg_PHY_IE_MODE,
ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
_reg_PHY_IE_MODE));
return 0;
}
......@@ -3960,7 +4040,6 @@ static uint32_t rx_offset_cal_hw(void)
uint32_t tmp;
uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01);
ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x00);
ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
ddr_setval_ach_as(_reg_PHY_RX_CAL_SAMPLE_WAIT, 0x0f);
......@@ -3997,9 +4076,6 @@ static uint32_t rx_offset_cal_hw(void)
retry++;
}
ddr_setval_ach_as(_reg_PHY_IE_MODE,
ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
_reg_PHY_IE_MODE));
return (complete == 0);
}
......@@ -4095,17 +4171,16 @@ int32_t rcar_dram_init(void)
/***********************************************************************
Thermal sensor setting
***********************************************************************/
dataL = *((volatile uint32_t *)CPG_MSTPSR5);
dataL = mmio_read_32(CPG_MSTPSR5);
if (dataL & BIT22) { /* case THS/TSC Standby */
dataL &= ~(BIT22);
*((volatile uint32_t *)CPG_CPGWPR) = ~dataL;
*((volatile uint32_t *)CPG_SMSTPCR5) = dataL;
while ((BIT22) & *((volatile uint32_t *)CPG_MSTPSR5)) ; /* wait bit=0 */
cpg_write_32(CPG_SMSTPCR5, dataL);
while ((BIT22) & mmio_read_32(CPG_MSTPSR5)); /* wait bit=0 */
}
/* THCTR Bit6: PONM=0 , Bit0: THSST=0 */
dataL = (*((volatile uint32_t *)THS1_THCTR)) & 0xFFFFFFBE;
*((volatile uint32_t *)THS1_THCTR) = dataL;
dataL = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE;
mmio_write_32(THS1_THCTR, dataL);
/***********************************************************************
Judge product and cut
......@@ -4136,7 +4211,7 @@ int32_t rcar_dram_init(void)
|| (Prr_Product == PRR_PRODUCT_V3H)) {
pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[3][0];
} else {
FATAL_MSG("DDR:Unknown Product");
FATAL_MSG("BL2: DDR:Unknown Product\n");
return 0xff;
}
......@@ -4152,7 +4227,7 @@ int32_t rcar_dram_init(void)
***********************************************************************/
_cnf_BOARDTYPE = boardcnf_get_brd_type();
if (_cnf_BOARDTYPE >= BOARDNUM) {
FATAL_MSG("DDR:Unknown Board");
FATAL_MSG("BL2: DDR:Unknown Board\n");
return 0xff;
}
Boardcnf = (struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE];
......@@ -4254,7 +4329,7 @@ int32_t rcar_dram_init(void)
else
ddr_tccd = tmp_tccd;
NOTICE("BL2: DDR%d(%s)", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION);
NOTICE("BL2: DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION);
MSG_LF("Start\n");
......@@ -4273,8 +4348,6 @@ int32_t rcar_dram_init(void)
failcount = 1;
}
NOTICE("..%d\n", failcount);
foreach_vch(ch)
mmio_write_32(DBSC_DBPDLK(ch), 0x00000000);
if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
......@@ -4294,6 +4367,7 @@ int32_t rcar_dram_init(void)
void pvtcode_update(void)
{
uint32_t ch;
uint32_t dataL;
uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init;
int32_t pvtp_tmp, pvtn_tmp;
......@@ -4321,58 +4395,39 @@ void pvtcode_update(void)
}
if ((Prr_Product == PRR_PRODUCT_H3)
&& (Prr_Cut <= PRR_PRODUCT_11)) {
dataL = pvtp[ch] | (pvtn[ch] << 6) | (tcal.tcomp_cal[ch] & 0xfffff000);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
pvtp[ch] | (pvtn[ch] << 6) | (tcal.
tcomp_cal
[ch] &
0xfffff000));
dataL | 0x00020000);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
pvtp[ch] | (pvtn[ch] << 6) | (tcal.
tcomp_cal
[ch] &
0xfffff000));
dataL);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
pvtp[ch] | (pvtn[ch] << 6) | (tcal.
tcomp_cal
[ch] &
0xfffff000));
dataL);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
pvtp[ch] | (pvtn[ch] << 6) | (tcal.
tcomp_cal
[ch] &
0xfffff000));
dataL);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
pvtp[ch] | (pvtn[ch] << 6) | (tcal.
tcomp_cal
[ch] &
0xfffff000));
dataL);
} else {
dataL = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000;
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
pvtp[ch] | (pvtn[ch] << 6) |
0x00035000);
dataL | 0x00020000);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
pvtp[ch] | (pvtn[ch] << 6) |
0x00015000);
dataL);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
pvtp[ch] | (pvtn[ch] << 6) |
0x00015000);
dataL);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
pvtp[ch] | (pvtn[ch] << 6) |
0x00015000);
dataL);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
pvtp[ch] | (pvtn[ch] << 6) |
0x00015000);
dataL);
}
}
}
......@@ -4412,7 +4467,7 @@ void ddr_padcal_tcompensate_getinit(uint32_t override)
}
if (!override) {
dataL = *((volatile uint32_t *)THS1_TEMP);
dataL = mmio_read_32(THS1_TEMP);
if (dataL < 2800) {
tcal.init_temp =
(143 * (int32_t) dataL - 359000) / 1000;
......@@ -4459,7 +4514,6 @@ void ddr_padcal_tcompensate_getinit(uint32_t override)
/* for QoS init */
uint8_t get_boardcnf_phyvalid(void)
{
/* return Boardcnf->phyvalid; */
return ddr_phyvalid;
}
#endif /* ddr_qos_init_setting */
......
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
View file @ 7825d719
......@@ -4,24 +4,33 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#define BOARDNUM 16
#define BOARDNUM 18
#define BOARD_JUDGE_AUTO
#ifdef BOARD_JUDGE_AUTO
static uint32_t _board_judge(void);
static uint32_t boardcnf_get_brd_type(void)
{
return _board_judge();
}
#else
static uint32_t boardcnf_get_brd_type(void)
{
return (1);
}
#endif
#define DDR_FAST_INIT
struct _boardcnf_ch {
uint8_t ddr_density[CS_CNT];
uint32_t ca_swap;
uint64_t ca_swap;
uint16_t dqs_swap;
uint32_t dq_swap[SLICE_CNT];
uint8_t dm_swap[SLICE_CNT];
uint16_t wdqlvl_patt[16];
int8_t cacs_adj[10];
int8_t cacs_adj[16];
int8_t dm_adj_w[SLICE_CNT];
int8_t dq_adj_w[SLICE_CNT * 8];
int8_t dm_adj_r[SLICE_CNT];
......@@ -876,7 +885,11 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
0x0a0,
{
{
#if (RCAR_DRAM_LPDDR4_MEMCONF == 2)
{0x04, 0x04},
#else
{0x02, 0x02},
#endif
0x00342501,
0x3201,
{0x10672534, 0x43257106, 0x34527601, 0x71605243},
......@@ -1227,6 +1240,88 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
0, 0, 0, 0, 0, 0, 0, 0}
}
}
},
/* boardcnf[16] RENESAS KRIEK-P2P board with M3-W/SoC */
{
0x03,
0x01,
0x0320,
0,
0x0300,
0x00a0,
{
{
{0x04, 0x04},
0x520314FFFF523041,
0x3201,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
{
{0x04, 0x04},
0x314250FFFF312405,
0x2310,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
}
}
},
/* boardcnf[17] RENESAS KRIEK-P2P board with M3-N/SoC */
{
0x01,
0x01,
0x0300,
0,
0x0300,
0x00a0,
{
{
{0x04, 0x04},
0x520314FFFF523041,
0x3201,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
}
}
}
};
......@@ -1258,6 +1353,7 @@ void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
break;
}
}
(void)brd;
}
void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t * mbps, uint32_t * div)
......@@ -1284,6 +1380,7 @@ void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t * mbps, uint32_t * div)
*div = 1;
break;
}
(void)brd;
}
#define _def_REFPERIOD 1890
......@@ -1393,10 +1490,10 @@ static uint32_t opencheck_SSI_WS6(void)
if (down == up) {
/* Same = Connect */
return 0;
}
} else {
/* Diff = Open */
return 1;
}
}
#endif
......@@ -1431,6 +1528,7 @@ static uint32_t _board_judge(void)
usb2_ovc_open = opencheck_SSI_WS6();
/* RENESAS Eva-borad */
brd = 99;
if (Prr_Product == PRR_PRODUCT_V3H) {
/* RENESAS Condor board */
brd = 12;
......@@ -1441,10 +1539,12 @@ static uint32_t _board_judge(void)
} else if (Prr_Product == PRR_PRODUCT_M3) {
/* RENESAS Kriek board with M3-W */
brd = 1;
} else if (Prr_Cut <= PRR_PRODUCT_11) {
} else if ((Prr_Product == PRR_PRODUCT_H3)
&& (Prr_Cut<=PRR_PRODUCT_11)) {
/* RENESAS Kriek board with PM3 */
brd = 13;
} else {
} else if ((Prr_Product == PRR_PRODUCT_H3)
&& (Prr_Cut > PRR_PRODUCT_20)) {
/* RENESAS Kriek board with H3N */
brd = 15;
}
......@@ -1467,12 +1567,13 @@ static uint32_t _board_judge(void)
} else if (Prr_Product == PRR_PRODUCT_M3N) {
/* RENESAS SALVATOR-X (M3-N/SIP) */
brd = 11;
} else {
} else if (Prr_Product == PRR_PRODUCT_M3) {
/* RENESAS SALVATOR-X (M3-W/SIP) */
brd = 0;
}
}
#endif
return brd;
}
#endif
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
View file @ 7825d719
......@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#define RCAR_DDR_VERSION "rev.0.33"
#define RCAR_DDR_VERSION "rev.0.34"
#define DRAM_CH_CNT (0x04)
#define SLICE_CNT (0x04)
#define CS_CNT (0x02)
......
drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
View file @ 7825d719
......@@ -267,7 +267,7 @@ static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = {
/*0bb9*/ 0x00000000,
/*0bba*/ 0x00000000,
/*0bbb*/ 0x00000000,
/*0bbc*/ 0x00000065,
/*0bbc*/ 0x00000265,
/*0bbd*/ 0x00000000,
/*0bbe*/ 0x00040401,
/*0bbf*/ 0x00000000,
......
drivers/staging/renesas/rcar/ddr/dram_sub_func.c
View file @ 7825d719
......@@ -19,10 +19,11 @@
#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */
#if RCAR_SYSTEM_SUSPEND
#include "iic_dvfs.h"
/* Local defines */
#define DRAM_BACKUP_GPIO_USE (0)
#include "iic_dvfs.h"
#if PMIC_ROHM_BD9571
#define PMIC_SLAVE_ADDR (0x30U)
#define PMIC_BKUP_MODE_CNT (0x20U)
#define PMIC_QLLM_CNT (0x27U)
#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4U))
......@@ -52,40 +53,53 @@
void rcar_dram_get_boot_status(uint32_t * status)
{
#if RCAR_SYSTEM_SUSPEND
uint32_t shift = GPIO_BKUP_TRG_SHIFT_SALVATOR;
uint32_t gpio = GPIO_INDT1;
uint32_t reg, product;
product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
uint32_t reg_data;
uint32_t product;
uint32_t shift;
uint32_t gpio;
product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
if (product == PRR_PRODUCT_V3H) {
shift = GPIO_BKUP_TRG_SHIFT_CONDOR;
gpio = GPIO_INDT3;
} else if (product == PRR_PRODUCT_E3) {
shift = GPIO_BKUP_TRG_SHIFT_EBISU;
gpio = GPIO_INDT6;
} else {
shift = GPIO_BKUP_TRG_SHIFT_SALVATOR;
gpio = GPIO_INDT1;
}
reg = mmio_read_32(gpio) & (1U << shift);
*status = reg ? DRAM_BOOT_STATUS_WARM : DRAM_BOOT_STATUS_COLD;
#else
reg_data = mmio_read_32(gpio);
if (0U != (reg_data & ((uint32_t)1U << shift))) {
*status = DRAM_BOOT_STATUS_WARM;
} else {
*status = DRAM_BOOT_STATUS_COLD;
#endif
}
#else /* RCAR_SYSTEM_SUSPEND */
*status = DRAM_BOOT_STATUS_COLD;
#endif /* RCAR_SYSTEM_SUSPEND */
}
int32_t rcar_dram_update_boot_status(uint32_t status)
{
int32_t ret = 0;
#if RCAR_SYSTEM_SUSPEND
uint32_t reg_data;
#if PMIC_ROHM_BD9571
#if DRAM_BACKUP_GPIO_USE == 0
uint8_t mode = 0U;
uint8_t bkup_mode_cnt = 0U;
#else
uint32_t reqb, outd;
#endif
uint8_t qllm = 0;
uint8_t qllm_cnt = 0U;
int32_t i2c_dvfs_ret = -1;
#endif
uint32_t i, product, trg, gpio;
uint32_t loop_count;
uint32_t product;
uint32_t trg;
uint32_t gpio;
product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
if (product == PRR_PRODUCT_V3H) {
......@@ -111,51 +125,59 @@ int32_t rcar_dram_update_boot_status(uint32_t status)
gpio = GPIO_INDT1;
}
if (status != DRAM_BOOT_STATUS_WARM)
goto cold;
if (status == DRAM_BOOT_STATUS_WARM) {
#if DRAM_BACKUP_GPIO_USE==1
mmio_setbits_32(outd, 1U << reqb);
#else
#if PMIC_ROHM_BD9571
if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode)) {
/* Set BKUP_CRTL_OUT=High (BKUP mode cnt register) */
i2c_dvfs_ret = rcar_iic_dvfs_receive(PMIC_SLAVE_ADDR,
PMIC_BKUP_MODE_CNT, &bkup_mode_cnt);
if (0 != i2c_dvfs_ret) {
ERROR("BKUP mode cnt READ ERROR.\n");
return DRAM_UPDATE_STATUS_ERR;
ret = DRAM_UPDATE_STATUS_ERR;
} else {
bkup_mode_cnt &= (uint8_t)~BIT_BKUP_CTRL_OUT;
i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
PMIC_BKUP_MODE_CNT, bkup_mode_cnt);
if (0 != i2c_dvfs_ret) {
ERROR("BKUP mode cnt WRITE ERROR. "
"value = %d\n", bkup_mode_cnt);
ret = DRAM_UPDATE_STATUS_ERR;
}
mode &= ~BIT_BKUP_CTRL_OUT;
if (rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode)) {
ERROR("BKUP mode cnt WRITE ERROR. value = %d\n", mode);
return DRAM_UPDATE_STATUS_ERR;
}
#endif
#endif
for (i = 0; i < DRAM_BKUP_TRG_LOOP_CNT; i++) {
if (mmio_read_32(gpio) & (1U << trg))
continue;
goto cold;
#endif /* PMIC_ROHM_BD9571 */
#endif /* DRAM_BACKUP_GPIO_USE==1 */
/* Wait BKUP_TRG=Low */
loop_count = DRAM_BKUP_TRG_LOOP_CNT;
while (0U < loop_count) {
reg_data = mmio_read_32(gpio);
if ((reg_data &
((uint32_t)1U << trg)) == 0U) {
break;
}
ERROR("\nWarm booting Error...\n"
" The potential of BKUP_TRG did not switch "
"to Low.\n If you expect the operation of "
"cold boot,\n check the board configuration"
loop_count--;
}
if (0U == loop_count) {
ERROR( "\nWarm booting...\n" \
" The potential of BKUP_TRG did not switch " \
"to Low.\n If you expect the operation of " \
"cold boot,\n check the board configuration" \
" (ex, Dip-SW) and/or the H/W failure.\n");
return DRAM_UPDATE_STATUS_ERR;
cold:
ret = DRAM_UPDATE_STATUS_ERR;
}
}
#if PMIC_ROHM_BD9571
if (ret)
return ret;
qllm = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
if (rcar_iic_dvfs_send(PMIC, PMIC_QLLM_CNT, qllm)) {
ERROR("QLLM cnt WRITE ERROR. value = %d\n", qllm);
if(0 == ret) {
qllm_cnt = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
PMIC_QLLM_CNT, qllm_cnt);
if (0 != i2c_dvfs_ret) {
ERROR("QLLM cnt WRITE ERROR. "
"value = %d\n", qllm_cnt);
ret = DRAM_UPDATE_STATUS_ERR;
}
}
#endif
#endif
return ret;
......
drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
View file @ 7825d719
......@@ -490,7 +490,8 @@ void pfc_init_e3(void)
| MOD_SEL0_REMOCON_A
| MOD_SEL0_SCIF_A
| MOD_SEL0_SCIF0_A
| MOD_SEL0_SCIF2_A | MOD_SEL0_SPEED_PULSE_IF_A);
| MOD_SEL0_SCIF2_A
| MOD_SEL0_SPEED_PULSE_IF_A);
pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_SIMCARD_A
| MOD_SEL1_SSI2_A
| MOD_SEL1_TIMER_TMU_A
......@@ -507,135 +508,137 @@ void pfc_init_e3(void)
| MOD_SEL1_SCIF4_A
| MOD_SEL1_SCIF5_A
| MOD_SEL1_VIN4_A
| MOD_SEL1_VIN5_A | MOD_SEL1_ADGC_A | MOD_SEL1_SSI9_A);
| MOD_SEL1_VIN5_A
| MOD_SEL1_ADGC_A
| MOD_SEL1_SSI9_A);
/* initialize peripheral function select */
pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0) /* QSPI1_MISO/IO1 */
|IPSR_24_FUNC(0) /* QSPI1_MOSI/IO0 */
|IPSR_20_FUNC(0) /* QSPI1_SPCLK */
|IPSR_16_FUNC(0) /* QSPI0_IO3 */
|IPSR_12_FUNC(0) /* QSPI0_IO2 */
|IPSR_8_FUNC(0) /* QSPI0_MISO/IO1 */
|IPSR_4_FUNC(0) /* QSPI0_MOSI/IO0 */
|IPSR_0_FUNC(0)); /* QSPI0_SPCLK */
| IPSR_24_FUNC(0) /* QSPI1_MOSI/IO0 */
| IPSR_20_FUNC(0) /* QSPI1_SPCLK */
| IPSR_16_FUNC(0) /* QSPI0_IO3 */
| IPSR_12_FUNC(0) /* QSPI0_IO2 */
| IPSR_8_FUNC(0) /* QSPI0_MISO/IO1 */
| IPSR_4_FUNC(0) /* QSPI0_MOSI/IO0 */
| IPSR_0_FUNC(0)); /* QSPI0_SPCLK */
pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0) /* AVB_RD2 */
|IPSR_24_FUNC(0) /* AVB_RD1 */
|IPSR_20_FUNC(0) /* AVB_RD0 */
|IPSR_16_FUNC(0) /* RPC_RESET# */
|IPSR_12_FUNC(0) /* RPC_INT# */
|IPSR_8_FUNC(0) /* QSPI1_SSL */
|IPSR_4_FUNC(0) /* QSPI1_IO3 */
|IPSR_0_FUNC(0)); /* QSPI1_IO2 */
| IPSR_24_FUNC(0) /* AVB_RD1 */
| IPSR_20_FUNC(0) /* AVB_RD0 */
| IPSR_16_FUNC(0) /* RPC_RESET# */
| IPSR_12_FUNC(0) /* RPC_INT# */
| IPSR_8_FUNC(0) /* QSPI1_SSL */
| IPSR_4_FUNC(0) /* QSPI1_IO3 */
| IPSR_0_FUNC(0)); /* QSPI1_IO2 */
pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(1) /* IRQ0 */
|IPSR_24_FUNC(0)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(2) /* AVB_LINK */
|IPSR_12_FUNC(0)
| IPSR_12_FUNC(0)
| IPSR_8_FUNC(0) /* AVB_MDC */
|IPSR_4_FUNC(0) /* AVB_MDIO */
|IPSR_0_FUNC(0)); /* AVB_TXCREFCLK */
| IPSR_4_FUNC(0) /* AVB_MDIO */
| IPSR_0_FUNC(0)); /* AVB_TXCREFCLK */
pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(5) /* DU_HSYNC */
|IPSR_24_FUNC(0)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
| IPSR_12_FUNC(5) /* DU_DG4 */
|IPSR_8_FUNC(5) /* DU_DOTCLKOUT0 */
|IPSR_4_FUNC(5) /* DU_DISP */
|IPSR_0_FUNC(1)); /* IRQ1 */
| IPSR_8_FUNC(5) /* DU_DOTCLKOUT0 */
| IPSR_4_FUNC(5) /* DU_DISP */
| IPSR_0_FUNC(1)); /* IRQ1 */
pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(5) /* DU_DB5 */
|IPSR_24_FUNC(5) /* DU_DB4 */
|IPSR_20_FUNC(5) /* DU_DB3 */
|IPSR_16_FUNC(5) /* DU_DB2 */
|IPSR_12_FUNC(5) /* DU_DG6 */
|IPSR_8_FUNC(5) /* DU_VSYNC */
|IPSR_4_FUNC(5) /* DU_DG5 */
|IPSR_0_FUNC(5)); /* DU_DG7 */
| IPSR_24_FUNC(5) /* DU_DB4 */
| IPSR_20_FUNC(5) /* DU_DB3 */
| IPSR_16_FUNC(5) /* DU_DB2 */
| IPSR_12_FUNC(5) /* DU_DG6 */
| IPSR_8_FUNC(5) /* DU_VSYNC */
| IPSR_4_FUNC(5) /* DU_DG5 */
| IPSR_0_FUNC(5)); /* DU_DG7 */
pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(5) /* DU_DR3 */
|IPSR_24_FUNC(5) /* DU_DB7 */
|IPSR_20_FUNC(5) /* DU_DR2 */
|IPSR_16_FUNC(5) /* DU_DR1 */
|IPSR_12_FUNC(5) /* DU_DR0 */
|IPSR_8_FUNC(5) /* DU_DB1 */
|IPSR_4_FUNC(5) /* DU_DB0 */
|IPSR_0_FUNC(5)); /* DU_DB6 */
| IPSR_24_FUNC(5) /* DU_DB7 */
| IPSR_20_FUNC(5) /* DU_DR2 */
| IPSR_16_FUNC(5) /* DU_DR1 */
| IPSR_12_FUNC(5) /* DU_DR0 */
| IPSR_8_FUNC(5) /* DU_DB1 */
| IPSR_4_FUNC(5) /* DU_DB0 */
| IPSR_0_FUNC(5)); /* DU_DB6 */
pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(5) /* DU_DG1 */
|IPSR_24_FUNC(5) /* DU_DG0 */
|IPSR_20_FUNC(5) /* DU_DR7 */
|IPSR_16_FUNC(2) /* IRQ5 */
|IPSR_12_FUNC(5) /* DU_DR6 */
|IPSR_8_FUNC(5) /* DU_DR5 */
|IPSR_4_FUNC(0)
| IPSR_24_FUNC(5) /* DU_DG0 */
| IPSR_20_FUNC(5) /* DU_DR7 */
| IPSR_16_FUNC(2) /* IRQ5 */
| IPSR_12_FUNC(5) /* DU_DR6 */
| IPSR_8_FUNC(5) /* DU_DR5 */
| IPSR_4_FUNC(0)
| IPSR_0_FUNC(5)); /* DU_DR4 */
pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0) /* SD0_CLK */
|IPSR_24_FUNC(0)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(5) /* DU_DOTCLKIN0 */
|IPSR_16_FUNC(5) /* DU_DG3 */
|IPSR_12_FUNC(0)
| IPSR_16_FUNC(5) /* DU_DG3 */
| IPSR_12_FUNC(0)
| IPSR_8_FUNC(0)
| IPSR_4_FUNC(0)
| IPSR_0_FUNC(5)); /* DU_DG2 */
pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0) /* SD1_DAT0 */
|IPSR_24_FUNC(0) /* SD1_CMD */
|IPSR_20_FUNC(0) /* SD1_CLK */
|IPSR_16_FUNC(0) /* SD0_DAT3 */
|IPSR_12_FUNC(0) /* SD0_DAT2 */
|IPSR_8_FUNC(0) /* SD0_DAT1 */
|IPSR_4_FUNC(0) /* SD0_DAT0 */
|IPSR_0_FUNC(0)); /* SD0_CMD */
| IPSR_24_FUNC(0) /* SD1_CMD */
| IPSR_20_FUNC(0) /* SD1_CLK */
| IPSR_16_FUNC(0) /* SD0_DAT3 */
| IPSR_12_FUNC(0) /* SD0_DAT2 */
| IPSR_8_FUNC(0) /* SD0_DAT1 */
| IPSR_4_FUNC(0) /* SD0_DAT0 */
| IPSR_0_FUNC(0)); /* SD0_CMD */
pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0) /* SD3_DAT2 */
|IPSR_24_FUNC(0) /* SD3_DAT1 */
|IPSR_20_FUNC(0) /* SD3_DAT0 */
|IPSR_16_FUNC(0) /* SD3_CMD */
|IPSR_12_FUNC(0) /* SD3_CLK */
|IPSR_8_FUNC(0) /* SD1_DAT3 */
|IPSR_4_FUNC(0) /* SD1_DAT2 */
|IPSR_0_FUNC(0)); /* SD1_DAT1 */
| IPSR_24_FUNC(0) /* SD3_DAT1 */
| IPSR_20_FUNC(0) /* SD3_DAT0 */
| IPSR_16_FUNC(0) /* SD3_CMD */
| IPSR_12_FUNC(0) /* SD3_CLK */
| IPSR_8_FUNC(0) /* SD1_DAT3 */
| IPSR_4_FUNC(0) /* SD1_DAT2 */
| IPSR_0_FUNC(0)); /* SD1_DAT1 */
pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0) /* SD0_WP */
|IPSR_24_FUNC(0) /* SD0_CD */
|IPSR_20_FUNC(0) /* SD3_DS */
|IPSR_16_FUNC(0) /* SD3_DAT7 */
|IPSR_12_FUNC(0) /* SD3_DAT6 */
|IPSR_8_FUNC(0) /* SD3_DAT5 */
|IPSR_4_FUNC(0) /* SD3_DAT4 */
|IPSR_0_FUNC(0)); /* SD3_DAT3 */
| IPSR_24_FUNC(0) /* SD0_CD */
| IPSR_20_FUNC(0) /* SD3_DS */
| IPSR_16_FUNC(0) /* SD3_DAT7 */
| IPSR_12_FUNC(0) /* SD3_DAT6 */
| IPSR_8_FUNC(0) /* SD3_DAT5 */
| IPSR_4_FUNC(0) /* SD3_DAT4 */
| IPSR_0_FUNC(0)); /* SD3_DAT3 */
pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(2) /* AUDIO_CLKOUT1_A */
|IPSR_16_FUNC(2) /* AUDIO_CLKOUT_A */
|IPSR_12_FUNC(0)
| IPSR_16_FUNC(2) /* AUDIO_CLKOUT_A */
| IPSR_12_FUNC(0)
| IPSR_8_FUNC(0)
| IPSR_4_FUNC(0) /* SD1_WP */
|IPSR_0_FUNC(0)); /* SD1_CD */
| IPSR_0_FUNC(0)); /* SD1_CD */
pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
| IPSR_12_FUNC(0) /* RX2_A */
|IPSR_8_FUNC(0) /* TX2_A */
|IPSR_4_FUNC(2) /* AUDIO_CLKB_A */
|IPSR_0_FUNC(0));
| IPSR_8_FUNC(0) /* TX2_A */
| IPSR_4_FUNC(2) /* AUDIO_CLKB_A */
| IPSR_0_FUNC(0));
pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
| IPSR_12_FUNC(0)
| IPSR_8_FUNC(2) /* AUDIO_CLKC_A */
|IPSR_4_FUNC(1) /* HTX2_A */
|IPSR_0_FUNC(1)); /* HRX2_A */
| IPSR_4_FUNC(1) /* HTX2_A */
| IPSR_0_FUNC(1)); /* HRX2_A */
pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(3) /* USB0_PWEN_B */
|IPSR_24_FUNC(0) /* SSI_SDATA4 */
|IPSR_20_FUNC(0) /* SSI_SDATA3 */
|IPSR_16_FUNC(0) /* SSI_WS349 */
|IPSR_12_FUNC(0) /* SSI_SCK349 */
|IPSR_8_FUNC(0)
| IPSR_24_FUNC(0) /* SSI_SDATA4 */
| IPSR_20_FUNC(0) /* SSI_SDATA3 */
| IPSR_16_FUNC(0) /* SSI_WS349 */
| IPSR_12_FUNC(0) /* SSI_SCK349 */
| IPSR_8_FUNC(0)
| IPSR_4_FUNC(0) /* SSI_SDATA1 */
|IPSR_0_FUNC(0)); /* SSI_SDATA0 */
| IPSR_0_FUNC(0)); /* SSI_SDATA0 */
pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0) /* USB30_OVC */
|IPSR_24_FUNC(0) /* USB30_PWEN */
|IPSR_20_FUNC(0) /* AUDIO_CLKA */
|IPSR_16_FUNC(1) /* HRTS2#_A */
|IPSR_12_FUNC(1) /* HCTS2#_A */
|IPSR_8_FUNC(0)
| IPSR_24_FUNC(0) /* USB30_PWEN */
| IPSR_20_FUNC(0) /* AUDIO_CLKA */
| IPSR_16_FUNC(1) /* HRTS2#_A */
| IPSR_12_FUNC(1) /* HCTS2#_A */
| IPSR_8_FUNC(0)
| IPSR_4_FUNC(0)
| IPSR_0_FUNC(3)); /* USB0_OVC_B */
......@@ -648,7 +651,11 @@ void pfc_init_e3(void)
| GPSR0_D8
| GPSR0_D7
| GPSR0_D6
| GPSR0_D5 | GPSR0_D3 | GPSR0_D2 | GPSR0_D1 | GPSR0_D0);
| GPSR0_D5
| GPSR0_D3
| GPSR0_D2
| GPSR0_D1
| GPSR0_D0);
pfc_reg_write(PFC_GPSR1, GPSR1_WE0
| GPSR1_CS0
| GPSR1_A19
......@@ -663,7 +670,11 @@ void pfc_init_e3(void)
| GPSR1_A10
| GPSR1_A9
| GPSR1_A8
| GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
| GPSR1_A4
| GPSR1_A3
| GPSR1_A2
| GPSR1_A1
| GPSR1_A0);
pfc_reg_write(PFC_GPSR2, GPSR2_BIT27_REVERCED
| GPSR2_BIT26_REVERCED
| GPSR2_RD
......@@ -687,7 +698,8 @@ void pfc_init_e3(void)
| GPSR2_QSPI0_IO3
| GPSR2_QSPI0_IO2
| GPSR2_QSPI0_MISO_IO1
| GPSR2_QSPI0_MOSI_IO0 | GPSR2_QSPI0_SPCLK);
| GPSR2_QSPI0_MOSI_IO0
| GPSR2_QSPI0_SPCLK);
pfc_reg_write(PFC_GPSR3, GPSR3_SD1_WP
| GPSR3_SD1_CD
| GPSR3_SD0_WP
......@@ -701,7 +713,9 @@ void pfc_init_e3(void)
| GPSR3_SD0_DAT3
| GPSR3_SD0_DAT2
| GPSR3_SD0_DAT1
| GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
| GPSR3_SD0_DAT0
| GPSR3_SD0_CMD
| GPSR3_SD0_CLK);
pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DS
| GPSR4_SD3_DAT7
| GPSR4_SD3_DAT6
......@@ -710,13 +724,17 @@ void pfc_init_e3(void)
| GPSR4_SD3_DAT3
| GPSR4_SD3_DAT2
| GPSR4_SD3_DAT1
| GPSR4_SD3_DAT0 | GPSR4_SD3_CMD | GPSR4_SD3_CLK);
| GPSR4_SD3_DAT0
| GPSR4_SD3_CMD
| GPSR4_SD3_CLK);
pfc_reg_write(PFC_GPSR5, GPSR5_SSI_SDATA9
| GPSR5_MSIOF0_SS2
| GPSR5_MSIOF0_SS1
| GPSR5_RX2_A
| GPSR5_TX2_A
| GPSR5_SCK2_A | GPSR5_RTS0_TANS_A | GPSR5_CTS0_A);
| GPSR5_SCK2_A
| GPSR5_RTS0_TANS_A
| GPSR5_CTS0_A);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_PWEN
| GPSR6_SSI_SDATA6
| GPSR6_SSI_WS6
......@@ -730,7 +748,8 @@ void pfc_init_e3(void)
| GPSR6_SSI_SCK349
| GPSR6_SSI_SDATA1
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS01239 | GPSR6_SSI_SCK01239);
| GPSR6_SSI_WS01239
| GPSR6_SSI_SCK01239);
/* initialize POC control */
reg = mmio_read_32(PFC_IOCTRL30);
......@@ -743,7 +762,9 @@ void pfc_init_e3(void)
| POC_SD0_DAT3_33V
| POC_SD0_DAT2_33V
| POC_SD0_DAT1_33V
| POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
| POC_SD0_DAT0_33V
| POC_SD0_CMD_33V
| POC_SD0_CLK_33V);
pfc_reg_write(PFC_IOCTRL30, reg);
reg = mmio_read_32(PFC_IOCTRL32);
reg = (reg & IOCTRL32_MASK);
......
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
View file @ 7825d719
......@@ -802,7 +802,9 @@ void pfc_init_h3_v1(void)
| MOD_SEL0_DRIF2_A
| MOD_SEL0_DRIF1_A
| MOD_SEL0_DRIF0_A
| MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A | MOD_SEL0_5LINE_A);
| MOD_SEL0_CANFD0_A
| MOD_SEL0_ADG_A
| MOD_SEL0_5LINE_A);
pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
| MOD_SEL1_TSIF0_A
| MOD_SEL1_TIMER_TMU_A
......@@ -822,9 +824,13 @@ void pfc_init_h3_v1(void)
| MOD_SEL1_PWM6_A
| MOD_SEL1_PWM5_A
| MOD_SEL1_PWM4_A
| MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
| MOD_SEL1_PWM3_A
| MOD_SEL1_PWM2_A
| MOD_SEL1_PWM1_A);
pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
| MOD_SEL2_I2C_3_A | MOD_SEL2_I2C_0_A | MOD_SEL2_VIN4_A);
| MOD_SEL2_I2C_3_A
| MOD_SEL2_I2C_0_A
| MOD_SEL2_VIN4_A);
/* initialize peripheral function select */
pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
......@@ -971,7 +977,10 @@ void pfc_init_h3_v1(void)
| GPSR0_D14
| GPSR0_D13
| GPSR0_D12
| GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
| GPSR0_D11
| GPSR0_D10
| GPSR0_D9
| GPSR0_D8);
pfc_reg_write(PFC_GPSR1, GPSR1_EX_WAIT0_A
| GPSR1_A19
| GPSR1_A18
......@@ -984,7 +993,11 @@ void pfc_init_h3_v1(void)
| GPSR1_A7
| GPSR1_A6
| GPSR1_A5
| GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
| GPSR1_A4
| GPSR1_A3
| GPSR1_A2
| GPSR1_A1
| GPSR1_A0);
pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
| GPSR2_AVB_AVTP_MATCH_A
| GPSR2_AVB_LINK
......@@ -994,7 +1007,10 @@ void pfc_init_h3_v1(void)
| GPSR2_PWM1_A
| GPSR2_IRQ5
| GPSR2_IRQ4
| GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
| GPSR2_IRQ3
| GPSR2_IRQ2
| GPSR2_IRQ1
| GPSR2_IRQ0);
pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
| GPSR3_SD0_CD
| GPSR3_SD1_DAT3
......@@ -1004,7 +1020,9 @@ void pfc_init_h3_v1(void)
| GPSR3_SD0_DAT3
| GPSR3_SD0_DAT2
| GPSR3_SD0_DAT1
| GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
| GPSR3_SD0_DAT0
| GPSR3_SD0_CMD
| GPSR3_SD0_CLK);
pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
| GPSR4_SD3_DAT6
| GPSR4_SD3_DAT3
......@@ -1017,7 +1035,9 @@ void pfc_init_h3_v1(void)
| GPSR4_SD2_DAT3
| GPSR4_SD2_DAT2
| GPSR4_SD2_DAT1
| GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
| GPSR4_SD2_DAT0
| GPSR4_SD2_CMD
| GPSR4_SD2_CLK);
pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
| GPSR5_MSIOF0_SS1
| GPSR5_MSIOF0_SYNC
......@@ -1032,7 +1052,9 @@ void pfc_init_h3_v1(void)
| GPSR5_RTS1_TANS
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
| GPSR5_RX1_A
| GPSR5_RTS0_TANS
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
| GPSR6_USB1_OVC
......@@ -1052,9 +1074,12 @@ void pfc_init_h3_v1(void)
| GPSR6_SSI_SCK4
| GPSR6_SSI_SDATA1_A
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
| GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
| GPSR7_HDMI0_CEC
| GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
......@@ -1071,7 +1096,9 @@ void pfc_init_h3_v1(void)
| POC_SD0_DAT3_33V
| POC_SD0_DAT2_33V
| POC_SD0_DAT1_33V
| POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
| POC_SD0_DAT0_33V
| POC_SD0_CMD_33V
| POC_SD0_CLK_33V);
/* initialize DRV control register */
reg = mmio_read_32(PFC_DRVCTRL0);
......
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
View file @ 7825d719
......@@ -833,7 +833,8 @@ void pfc_init_h3_v2(void)
| MOD_SEL0_DRIF2_A
| MOD_SEL0_DRIF1_A
| MOD_SEL0_DRIF0_A
| MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A_A);
| MOD_SEL0_CANFD0_A
| MOD_SEL0_ADG_A_A);
pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
| MOD_SEL1_TSIF0_A
| MOD_SEL1_TIMER_TMU_A
......@@ -853,7 +854,9 @@ void pfc_init_h3_v2(void)
| MOD_SEL1_PWM6_A
| MOD_SEL1_PWM5_A
| MOD_SEL1_PWM4_A
| MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
| MOD_SEL1_PWM3_A
| MOD_SEL1_PWM2_A
| MOD_SEL1_PWM1_A);
pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
| MOD_SEL2_I2C_3_A
| MOD_SEL2_I2C_0_A
......@@ -864,7 +867,9 @@ void pfc_init_h3_v2(void)
| MOD_SEL2_SSI2_A
| MOD_SEL2_SSI9_A
| MOD_SEL2_TIMER_TMU2_A
| MOD_SEL2_ADG_B_A | MOD_SEL2_ADG_C_A | MOD_SEL2_VIN4_A);
| MOD_SEL2_ADG_B_A
| MOD_SEL2_ADG_C_A
| MOD_SEL2_VIN4_A);
/* initialize peripheral function select */
pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
......@@ -1019,7 +1024,10 @@ void pfc_init_h3_v2(void)
| GPSR0_D14
| GPSR0_D13
| GPSR0_D12
| GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
| GPSR0_D11
| GPSR0_D10
| GPSR0_D9
| GPSR0_D8);
pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
| GPSR1_EX_WAIT0_A
| GPSR1_A19
......@@ -1033,7 +1041,11 @@ void pfc_init_h3_v2(void)
| GPSR1_A7
| GPSR1_A6
| GPSR1_A5
| GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
| GPSR1_A4
| GPSR1_A3
| GPSR1_A2
| GPSR1_A1
| GPSR1_A0);
pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
| GPSR2_AVB_AVTP_MATCH_A
| GPSR2_AVB_LINK
......@@ -1043,7 +1055,10 @@ void pfc_init_h3_v2(void)
| GPSR2_PWM1_A
| GPSR2_IRQ5
| GPSR2_IRQ4
| GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
| GPSR2_IRQ3
| GPSR2_IRQ2
| GPSR2_IRQ1
| GPSR2_IRQ0);
pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
| GPSR3_SD0_CD
| GPSR3_SD1_DAT3
......@@ -1053,7 +1068,9 @@ void pfc_init_h3_v2(void)
| GPSR3_SD0_DAT3
| GPSR3_SD0_DAT2
| GPSR3_SD0_DAT1
| GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
| GPSR3_SD0_DAT0
| GPSR3_SD0_CMD
| GPSR3_SD0_CLK);
pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
| GPSR4_SD3_DAT6
| GPSR4_SD3_DAT3
......@@ -1066,7 +1083,9 @@ void pfc_init_h3_v2(void)
| GPSR4_SD2_DAT3
| GPSR4_SD2_DAT2
| GPSR4_SD2_DAT1
| GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
| GPSR4_SD2_DAT0
| GPSR4_SD2_CMD
| GPSR4_SD2_CLK);
pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
| GPSR5_MSIOF0_SS1
| GPSR5_MSIOF0_SYNC
......@@ -1081,7 +1100,9 @@ void pfc_init_h3_v2(void)
| GPSR5_RTS1_TANS
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
| GPSR5_RX1_A
| GPSR5_RTS0_TANS
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
| GPSR6_USB1_OVC
......@@ -1101,9 +1122,12 @@ void pfc_init_h3_v2(void)
| GPSR6_SSI_SCK4
| GPSR6_SSI_SDATA1_A
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
| GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
| GPSR7_HDMI0_CEC
| GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
......@@ -1120,7 +1144,9 @@ void pfc_init_h3_v2(void)
| POC_SD0_DAT3_33V
| POC_SD0_DAT2_33V
| POC_SD0_DAT1_33V
| POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
| POC_SD0_DAT0_33V
| POC_SD0_CMD_33V
| POC_SD0_CLK_33V);
/* initialize DRV control register */
reg = mmio_read_32(PFC_DRVCTRL0);
......
drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
View file @ 7825d719
......@@ -867,7 +867,9 @@ static void StartRtDma0_Descriptor(void)
/* Set transfer parameter, Start transfer */
mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE
| RDMCHCR_RPT_TCR
| RDMCHCR_TS_2 | RDMCHCR_RS_AUTO | RDMCHCR_DE);
| RDMCHCR_TS_2
| RDMCHCR_RS_AUTO
| RDMCHCR_DE);
}
}
......@@ -913,7 +915,8 @@ void pfc_init_m3(void)
| MOD_SEL0_DRIF2_A
| MOD_SEL0_DRIF1_A
| MOD_SEL0_DRIF0_A
| MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A_A);
| MOD_SEL0_CANFD0_A
| MOD_SEL0_ADG_A_A);
pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
| MOD_SEL1_TSIF0_A
| MOD_SEL1_TIMER_TMU_A
......@@ -933,7 +936,9 @@ void pfc_init_m3(void)
| MOD_SEL1_PWM6_A
| MOD_SEL1_PWM5_A
| MOD_SEL1_PWM4_A
| MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
| MOD_SEL1_PWM3_A
| MOD_SEL1_PWM2_A
| MOD_SEL1_PWM1_A);
pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
| MOD_SEL2_I2C_3_A
| MOD_SEL2_I2C_0_A
......@@ -944,7 +949,9 @@ void pfc_init_m3(void)
| MOD_SEL2_SSI2_A
| MOD_SEL2_SSI9_A
| MOD_SEL2_TIMER_TMU2_A
| MOD_SEL2_ADG_B_A | MOD_SEL2_ADG_C_A | MOD_SEL2_VIN4_A);
| MOD_SEL2_ADG_B_A
| MOD_SEL2_ADG_C_A
| MOD_SEL2_VIN4_A);
/* initialize peripheral function select */
pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
......@@ -1099,7 +1106,10 @@ void pfc_init_m3(void)
| GPSR0_D14
| GPSR0_D13
| GPSR0_D12
| GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
| GPSR0_D11
| GPSR0_D10
| GPSR0_D9
| GPSR0_D8);
pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
| GPSR1_EX_WAIT0_A
| GPSR1_A19
......@@ -1113,7 +1123,11 @@ void pfc_init_m3(void)
| GPSR1_A7
| GPSR1_A6
| GPSR1_A5
| GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
| GPSR1_A4
| GPSR1_A3
| GPSR1_A2
| GPSR1_A1
| GPSR1_A0);
pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
| GPSR2_AVB_AVTP_MATCH_A
| GPSR2_AVB_LINK
......@@ -1123,7 +1137,10 @@ void pfc_init_m3(void)
| GPSR2_PWM1_A
| GPSR2_IRQ5
| GPSR2_IRQ4
| GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
| GPSR2_IRQ3
| GPSR2_IRQ2
| GPSR2_IRQ1
| GPSR2_IRQ0);
pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
| GPSR3_SD0_CD
| GPSR3_SD1_DAT3
......@@ -1133,7 +1150,9 @@ void pfc_init_m3(void)
| GPSR3_SD0_DAT3
| GPSR3_SD0_DAT2
| GPSR3_SD0_DAT1
| GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
| GPSR3_SD0_DAT0
| GPSR3_SD0_CMD
| GPSR3_SD0_CLK);
pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
| GPSR4_SD3_DAT6
| GPSR4_SD3_DAT3
......@@ -1146,7 +1165,9 @@ void pfc_init_m3(void)
| GPSR4_SD2_DAT3
| GPSR4_SD2_DAT2
| GPSR4_SD2_DAT1
| GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
| GPSR4_SD2_DAT0
| GPSR4_SD2_CMD
| GPSR4_SD2_CLK);
pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
| GPSR5_MSIOF0_SS1
| GPSR5_MSIOF0_SYNC
......@@ -1161,7 +1182,9 @@ void pfc_init_m3(void)
| GPSR5_RTS1_TANS
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
| GPSR5_RX1_A
| GPSR5_RTS0_TANS
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
| GPSR6_USB1_OVC
......@@ -1181,9 +1204,12 @@ void pfc_init_m3(void)
| GPSR6_SSI_SCK4
| GPSR6_SSI_SDATA1_A
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
| GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
| GPSR7_HDMI0_CEC
| GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
......@@ -1200,7 +1226,9 @@ void pfc_init_m3(void)
| POC_SD0_DAT3_33V
| POC_SD0_DAT2_33V
| POC_SD0_DAT1_33V
| POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
| POC_SD0_DAT0_33V
| POC_SD0_CMD_33V
| POC_SD0_CLK_33V);
/* initialize DRV control register */
reg = mmio_read_32(PFC_DRVCTRL0);
......
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