From 7aba390fd02dbc5525d216d5d2c6debe47a06df9 Mon Sep 17 00:00:00 2001
From: Anthony Zhou <anzhou@nvidia.com>
Date: Mon, 8 May 2017 20:34:11 +0800
Subject: [PATCH] Tegra: topology: fix MISRA defects for Rule 4.6
This patch uses int32_t to replace ints, to fix Rule 4.6 of the
MISRA standard.
Change-Id: I20ac6185929eced684b43da3ef1f8cd5fbddc83d
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
---
plat/nvidia/tegra/common/tegra_topology.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/plat/nvidia/tegra/common/tegra_topology.c b/plat/nvidia/tegra/common/tegra_topology.c
index c423d8c3e..4f6cf932e 100644
--- a/plat/nvidia/tegra/common/tegra_topology.c
+++ b/plat/nvidia/tegra/common/tegra_topology.c
@@ -18,15 +18,15 @@
* to convert an MPIDR to a unique linear index. An error code (-1) is returned
* in case the MPIDR is invalid.
******************************************************************************/
-int plat_core_pos_by_mpidr(u_register_t mpidr)
+int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
{
u_register_t cluster_id, cpu_id;
- int result;
+ int32_t result;
cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
- result = (int)cpu_id + ((int)cluster_id * 4);
+ result = (int32_t)cpu_id + ((int32_t)cluster_id * 4);
if (cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) {
result = PSCI_E_NOT_PRESENT;
--
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