Skip to content

GitLab

Commit 7cefb56d authored by danh-arm's avatar danh-arm Committed by GitHub
Browse files

Merge pull request #1011 from douglas-raillard-arm/dr/doc_convert_to_rst 

Convert Markdown to reStructuredText
parents aa5b843f 06fb4278
Show whitespace changes
Inline Side-by-side
docs/plat/xilinx-zynqmp.md → docs/plat/xilinx-zynqmp.rst
View file @ 7cefb56d
ARM Trusted Firmware for Xilinx Zynq UltraScale+ MPSoC
================================
======================================================
ARM Trusted Firmware implements the EL3 firmware layer for Xilinx Zynq
UltraScale + MPSoC.
......@@ -11,36 +11,47 @@ BL32 is an optional Secure Payload.
BL33 is the non-secure world software (U-Boot, Linux etc).
To build:
```bash
make ERROR_DEPRECATED=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp bl31
```
.. code:: bash
make ERROR_DEPRECATED=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp bl31
To build bl32 TSP you have to rebuild bl31 too:
```bash
make ERROR_DEPRECATED=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32
```
# ZynqMP platform specific build options
* `ZYNQMP_ATF_MEM_BASE`: Specifies the base address of the bl31 binary.
* `ZYNQMP_ATF_MEM_SIZE`: Specifies the size of the memory region of the bl31 binary.
* `ZYNQMP_BL32_MEM_BASE`: Specifies the base address of the bl32 binary.
* `ZYNQMP_BL32_MEM_SIZE`: Specifies the size of the memory region of the bl32 binary.
.. code:: bash
make ERROR_DEPRECATED=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32
ZynqMP platform specific build options
======================================
- ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary.
- ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary.
- ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary.
- ``ZYNQMP_BL32_MEM_SIZE``: Specifies the size of the memory region of the bl32 binary.
- ``ZYNQMP_CONSOLE``: Select the console driver. Options:
* `ZYNQMP_CONSOLE`: Select the console driver. Options:
- `cadence`, `cadence0`: Cadence UART 0
- `cadence1` : Cadence UART 1
- ``cadence``, ``cadence0``: Cadence UART 0
- ``cadence1`` : Cadence UART 1
FSBL->ATF Parameter Passing
===========================
# FSBL->ATF Parameter Passing
The FSBL populates a data structure with image information for the ATF. The ATF
uses that data to hand off to the loaded images. The address of the handoff data
structure is passed in the ```PMU_GLOBAL.GLOBAL_GEN_STORAGE6``` register. The
structure is passed in the ``PMU_GLOBAL.GLOBAL_GEN_STORAGE6`` register. The
register is free to be used by other software once the ATF is bringing up
further firmware images.
# Power Domain Tree
Power Domain Tree
=================
The following power domain tree represents the power domain model used by the
ATF for ZynqMP:
```
::
+-+
|0|
+-+
......@@ -51,6 +62,6 @@ ATF for ZynqMP:
+-+ +-+ +-+ +-+
|0| |1| |2| |3|
+-+ +-+ +-+ +-+
```
The 4 leaf power domains represent the individual A53 cores, while resources
common to the cluster are grouped in the power domain on the top.
docs/platform-migration-guide.md → docs/platform-migration-guide.rst
View file @ 7cefb56d
Guide to migrate to new Platform porting interface
==================================================
Contents
--------
1. [Introduction](#1--introduction)
2. [Platform API modification due to PSCI framework changes](#2--platform-api-modification-due-to-psci-framework-changes)
* [Power domain topology framework platform API modifications](#21-power-domain-topology-framework-platform-api-modifications)
* [Composite power state framework platform API modifications](#22-composite-power-state-framework-platform-api-modifications)
* [Miscellaneous modifications](#23-miscellaneous-modifications)
3. [Compatibility layer](#3--compatibility-layer)
4. [Deprecated Platform API](#4--deprecated-platform-api)
.. section-numbering::
:suffix: .
- - - - - - - - - - - - - - - - - -
.. contents::
--------------
1. Introduction
----------------
Introduction
------------
The PSCI implementation in Trusted Firmware has undergone a redesign because of
three requirements that the PSCI 1.0 specification introduced :
* Removing the framework assumption about the structure of the MPIDR, and
- Removing the framework assumption about the structure of the MPIDR, and
its relation to the power topology enables support for deeper and more
complex hierarchies.
* Reworking the power state coordination implementation in the framework
- Reworking the power state coordination implementation in the framework
to support the more detailed PSCI 1.0 requirements and reduce platform
port complexity
* Enable the use of the extended power_state parameter and the larger StateID
- Enable the use of the extended power\_state parameter and the larger StateID
field
The PSCI 1.0 implementation introduces new frameworks to fulfill the above
......@@ -42,61 +36,58 @@ deprecated API. It also describes the compatibility layer that enables the
existing platform ports to work with the PSCI 1.0 implementation. The
deprecated platform API is documented for reference.
2. Platform API modification due to PSCI framework changes
-----------------------------------------------------------
Platform API modification due to PSCI framework changes
-------------------------------------------------------
This section describes changes to the platform APIs.
2.1 Power domain topology framework platform API modifications
--------------------------------------------------------------
Power domain topology framework platform API modifications
----------------------------------------------------------
This removes the assumption in the PSCI implementation that MPIDR
based affinity instances map directly to power domains. A power domain, as
described in section 4.2 of [PSCI], could contain a core or a logical group
described in section 4.2 of `PSCI`_, could contain a core or a logical group
of cores (a cluster) which share some state on which power management
operations can be performed. The existing affinity instance based APIs
`plat_get_aff_count()` and `plat_get_aff_state()` are deprecated. The new
``plat_get_aff_count()`` and ``plat_get_aff_state()`` are deprecated. The new
platform interfaces that are introduced for this framework are:
* `plat_core_pos_by_mpidr()`
* `plat_my_core_pos()`
* `plat_get_power_domain_tree_desc()`
- ``plat_core_pos_by_mpidr()``
- ``plat_my_core_pos()``
- ``plat_get_power_domain_tree_desc()``
`plat_my_core_pos()` and `plat_core_pos_by_mpidr()` are mandatory
and are meant to replace the existing `platform_get_core_pos()` API.
The description of these APIs can be found in the [Porting Guide][my_core_pos].
``plat_my_core_pos()`` and ``plat_core_pos_by_mpidr()`` are mandatory
and are meant to replace the existing ``platform_get_core_pos()`` API.
The description of these APIs can be found in the `Porting Guide`_.
These are used by the power domain topology framework such that:
1. The generic PSCI code does not generate MPIDRs or use them to query the
#. The generic PSCI code does not generate MPIDRs or use them to query the
platform about the number of power domains at a particular power level. The
`plat_get_power_domain_tree_desc()` provides a description of the power
``plat_get_power_domain_tree_desc()`` provides a description of the power
domain tree on the SoC through a pointer to the byte array containing the
power domain topology tree description data structure.
2. The linear indices returned by `plat_core_pos_by_mpidr()` and
`plat_my_core_pos()` are used to retrieve core power domain nodes from
#. The linear indices returned by ``plat_core_pos_by_mpidr()`` and
``plat_my_core_pos()`` are used to retrieve core power domain nodes from
the power domain tree. These core indices are unique for a core and it is a
number between `0` and `PLATFORM_CORE_COUNT - 1`. The platform can choose
to implement a static mapping between `MPIDR` and core index or implement
number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The platform can choose
to implement a static mapping between ``MPIDR`` and core index or implement
a dynamic mapping, choosing to skip the unavailable/unused cores to compact
the core indices.
In addition, the platforms must define the macros `PLAT_NUM_PWR_DOMAINS` and
`PLAT_MAX_PWR_LVL` which replace the macros `PLAT_NUM_AFFS` and
`PLATFORM_MAX_AFFLVL` respectively. On platforms where the affinity instances
In addition, the platforms must define the macros ``PLAT_NUM_PWR_DOMAINS`` and
``PLAT_MAX_PWR_LVL`` which replace the macros ``PLAT_NUM_AFFS`` and
``PLATFORM_MAX_AFFLVL`` respectively. On platforms where the affinity instances
correspond to power domains, the values of new macros remain the same as the
old ones.
More details on the power domain topology description and its platform
interface can be found in [psci pd tree].
interface can be found in `psci pd tree`_.
Composite power state framework platform API modifications
----------------------------------------------------------
2.2 Composite power state framework platform API modifications
--------------------------------------------------------------
The state-ID field in the power-state parameter of a CPU_SUSPEND call can be
The state-ID field in the power-state parameter of a CPU\_SUSPEND call can be
used to describe the composite power states specific to a platform. The existing
PSCI state coordination had the limitation that it operates on a run/off
granularity of power states and it did not interpret the state-ID field. This
......@@ -112,41 +103,44 @@ platform specific states.
The PSCI 1.0 implementation now defines a generic representation of the
power-state parameter :
.. code:: c
typedef struct psci_power_state {
plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + 1];
} psci_power_state_t;
`pwr_domain_state` is an array where each index corresponds to a power level.
``pwr_domain_state`` is an array where each index corresponds to a power level.
Each entry in the array contains the local power state the power domain at
that power level could enter. The meaning of the local power state value is
platform defined, and can vary between levels in a single platform. The PSCI
implementation constraints the values only so that it can classify the state
as RUN, RETENTION or OFF as required by the specification:
1. Zero means RUN
#. Zero means RUN
2. All OFF state values at all levels must be higher than all
#. All OFF state values at all levels must be higher than all
RETENTION state values at all levels
The platform is required to define the macros `PLAT_MAX_RET_STATE` and
`PLAT_MAX_OFF_STATE` to the framework. The requirement for these macros can
be found in the [Porting Guide].
The platform is required to define the macros ``PLAT_MAX_RET_STATE`` and
``PLAT_MAX_OFF_STATE`` to the framework. The requirement for these macros can
be found in the `Porting Guide <porting-guide.rst>`__.
The PSCI 1.0 implementation adds support to involve the platform in state
coordination. This enables the platform to decide the final target state.
During a request to place a power domain in a low power state, the platform
is passed an array of requested `plat_local_state_t` for that power domain by
each core within it through the `plat_get_target_pwr_state()` API. This API
is passed an array of requested ``plat_local_state_t`` for that power domain by
each core within it through the ``plat_get_target_pwr_state()`` API. This API
coordinates amongst these requested states to determine a target
`plat_local_state_t` for that power domain. A default weak implementation of
``plat_local_state_t`` for that power domain. A default weak implementation of
this API is provided in the platform layer which returns the minimum of the
requested local states back to the PSCI state coordination. More details
of `plat_get_target_pwr_state()` API can be found in the
[Porting Guide][get_target_pwr_state].
of ``plat_get_target_pwr_state()`` API can be found in the
`Porting Guide <porting-guide.rst#user-content-function--plat_get_target_pwr_state-optional>`__.
The PSCI Generic implementation expects platform ports to populate the handlers
for the `plat_psci_ops` structure which is declared as :
for the ``plat_psci_ops`` structure which is declared as :
.. code:: c
typedef struct plat_psci_ops {
void (*cpu_standby)(plat_local_state_t cpu_state);
......@@ -165,41 +159,41 @@ for the `plat_psci_ops` structure which is declared as :
psci_power_state_t *req_state);
} plat_psci_ops_t;
The description of these handlers can be found in the [Porting Guide][psci_ops].
The previous `plat_pm_ops` structure is deprecated. Compared with the previous
The description of these handlers can be found in the `Porting Guide <porting-guide.rst#user-content-function--plat_setup_psci_ops-mandatory>`__.
The previous ``plat_pm_ops`` structure is deprecated. Compared with the previous
handlers, the major differences are:
* Difference in parameters
- Difference in parameters
The PSCI 1.0 implementation depends on the `validate_power_state` handler to
The PSCI 1.0 implementation depends on the ``validate_power_state`` handler to
convert the power-state parameter (possibly encoding a composite power state)
passed in a PSCI `CPU_SUSPEND` to the `psci_power_state` format. This handler
is now mandatory for PSCI `CPU_SUSPEND` support.
passed in a PSCI ``CPU_SUSPEND`` to the ``psci_power_state`` format. This handler
is now mandatory for PSCI ``CPU_SUSPEND`` support.
The `plat_psci_ops` handlers, `pwr_domain_off` and `pwr_domain_suspend`, are
The ``plat_psci_ops`` handlers, ``pwr_domain_off`` and ``pwr_domain_suspend``, are
passed the target local state for each affected power domain. The platform
must execute operations specific to these target states. Similarly,
`pwr_domain_on_finish` and `pwr_domain_suspend_finish` are passed the local
``pwr_domain_on_finish`` and ``pwr_domain_suspend_finish`` are passed the local
states of the affected power domains before wakeup. The platform
must execute actions to restore these power domains from these specific
local states.
* Difference in invocation
- Difference in invocation
Whereas the power management handlers in `plat_pm_ops` used to be invoked
Whereas the power management handlers in ``plat_pm_ops`` used to be invoked
for each affinity level till the target affinity level, the new handlers
are only invoked once. The `target_state` encodes the target low power
are only invoked once. The ``target_state`` encodes the target low power
state or the low power state woken up from for each affected power domain.
* Difference in semantics
- Difference in semantics
Although the previous `suspend` handlers could be used for power down as well
Although the previous ``suspend`` handlers could be used for power down as well
as retention at different affinity levels, the new handlers make this support
explicit. The `pwr_domain_suspend` can be used to specify powerdown and
explicit. The ``pwr_domain_suspend`` can be used to specify powerdown and
retention at various power domain levels subject to the conditions mentioned
in section 4.2.1 of [PSCI]
in section 4.2.1 of `PSCI`_
Unlike the previous `standby` handler, the `cpu_standby()` handler is only used
Unlike the previous ``standby`` handler, the ``cpu_standby()`` handler is only used
as a fast path for placing a core power domain into a standby or retention
state.
......@@ -207,46 +201,44 @@ The below diagram shows the sequence of a PSCI SUSPEND call and the interaction
with the platform layer depicting the exchange of data between PSCI Generic
layer and the platform layer.
![Image 1](diagrams/psci-suspend-sequence.png?raw=true)
|Image 1|
Refer [plat/arm/board/fvp/fvp_pm.c] for the implementation details of
these handlers for the FVP. The commit 38dce70f51fb83b27958ba3e2ad15f5635cb1061
Refer `plat/arm/board/fvp/fvp\_pm.c`_ for the implementation details of
these handlers for the FVP. The commit `38dce70f51fb83b27958ba3e2ad15f5635cb1061`_
demonstrates the migration of ARM reference platforms to the new platform API.
2.3 Miscellaneous modifications
-------------------------------
Miscellaneous modifications
---------------------------
In addition to the framework changes, unification of warm reset entry points on
wakeup from low power modes has led to a change in the platform API. In the
earlier implementation, the warm reset entry used to be programmed into the
mailboxes by the 'ON' and 'SUSPEND' power management hooks. In the PSCI 1.0
implementation, this information is not required, because it can figure that
out by querying affinity info state whether to execute the 'suspend_finisher`
or 'on_finisher'.
out by querying affinity info state whether to execute the 'suspend\_finisher\`
or 'on\_finisher'.
As a result, the warm reset entry point must be programmed only once. The
`plat_setup_psci_ops()` API takes the secure entry point as an
``plat_setup_psci_ops()`` API takes the secure entry point as an
additional parameter to enable the platforms to configure their mailbox. The
plat_psci_ops handlers `pwr_domain_on` and `pwr_domain_suspend` no longer take
plat\_psci\_ops handlers ``pwr_domain_on`` and ``pwr_domain_suspend`` no longer take
the warm reset entry point as a parameter.
Also, some platform APIs which took `MPIDR` as an argument were only ever
Also, some platform APIs which took ``MPIDR`` as an argument were only ever
invoked to perform actions specific to the caller core which makes the argument
redundant. Therefore the platform APIs `plat_get_my_entrypoint()`,
`plat_is_my_cpu_primary()`, `plat_set_my_stack()` and
`plat_get_my_stack()` are defined which are meant to be invoked only for
operations on the current caller core instead of `platform_get_entrypoint()`,
`platform_is_primary_cpu()`, `platform_set_stack()` and `platform_get_stack()`.
redundant. Therefore the platform APIs ``plat_get_my_entrypoint()``,
``plat_is_my_cpu_primary()``, ``plat_set_my_stack()`` and
``plat_get_my_stack()`` are defined which are meant to be invoked only for
operations on the current caller core instead of ``platform_get_entrypoint()``,
``platform_is_primary_cpu()``, ``platform_set_stack()`` and ``platform_get_stack()``.
3. Compatibility layer
----------------------
Compatibility layer
-------------------
To ease the migration of the platform ports to the new porting interface,
a compatibility layer is introduced that essentially implements a glue layer
between the old platform API and the new API. The build flag
`ENABLE_PLAT_COMPAT` (enabled by default), specifies whether to enable this
``ENABLE_PLAT_COMPAT`` (enabled by default), specifies whether to enable this
layer or not. A platform port which has migrated to the new API can disable
this flag within the platform specific makefile.
......@@ -259,39 +251,39 @@ new frameworks. Also, it assumes that the affinity levels of the platform
correspond directly to the power domain levels.
The compatibility layer dynamically constructs the new topology
description array by querying the platform using `plat_get_aff_count()`
and `plat_get_aff_state()` APIs. The linear index returned by
`platform_get_core_pos()` is used as the core index for the cores. The
description array by querying the platform using ``plat_get_aff_count()``
and ``plat_get_aff_state()`` APIs. The linear index returned by
``platform_get_core_pos()`` is used as the core index for the cores. The
higher level (non-core) power domain nodes must know the cores contained
within its domain. It does so by storing the core index of first core
within it and number of core indexes following it. This means that core
indices returned by `platform_get_core_pos()` for cores within a particular
indices returned by ``platform_get_core_pos()`` for cores within a particular
power domain must be consecutive. We expect that this is the case for most
platform ports including ARM reference platforms.
The old PSCI helpers like `psci_get_suspend_powerstate()`,
`psci_get_suspend_stateid()`, `psci_get_suspend_stateid_by_mpidr()`,
`psci_get_max_phys_off_afflvl()` and `psci_get_suspend_afflvl()` are also
The old PSCI helpers like ``psci_get_suspend_powerstate()``,
``psci_get_suspend_stateid()``, ``psci_get_suspend_stateid_by_mpidr()``,
``psci_get_max_phys_off_afflvl()`` and ``psci_get_suspend_afflvl()`` are also
implemented for the compatibility layer. This allows the existing
platform ports to work with the new PSCI frameworks without significant
rework.
4. Deprecated Platform API
---------------------------
Deprecated Platform API
-----------------------
This section documents the deprecated platform porting API.
## Common mandatory modifications
Common mandatory modifications
------------------------------
The mandatory macros to be defined by the platform port in `platform_def.h`
The mandatory macros to be defined by the platform port in ``platform_def.h``
* **#define : PLATFORM_NUM_AFFS**
- **#define : PLATFORM\_NUM\_AFFS**
Defines the total number of nodes in the affinity hierarchy at all affinity
levels used by the platform.
* **#define : PLATFORM_MAX_AFFLVL**
- **#define : PLATFORM\_MAX\_AFFLVL**
Defines the maximum affinity level that the power management operations
should apply to. ARMv8-A has support for four affinity levels. It is likely
......@@ -305,13 +297,16 @@ The mandatory macros to be defined by the platform port in `platform_def.h`
The following functions must be implemented by the platform port to enable
the reset vector code to perform the required tasks.
### Function : platform_get_entrypoint() [mandatory]
Function : platform\_get\_entrypoint() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : unsigned long
Return : unsigned long
This function is called with the `SCTLR.M` and `SCTLR.C` bits disabled. The core
is identified by its `MPIDR`, which is passed as the argument. The function is
This function is called with the ``SCTLR.M`` and ``SCTLR.C`` bits disabled. The core
is identified by its ``MPIDR``, which is passed as the argument. The function is
responsible for distinguishing between a warm and cold reset using platform-
specific means. If it is a warm reset, it returns the entrypoint into the
BL31 image that the core must jump to. If it is a cold reset, this function
......@@ -326,36 +321,47 @@ Application Binary Interface for the ARM 64-bit architecture. The caller should
not assume that callee saved registers are preserved across a call to this
function.
### Function : platform_is_primary_cpu() [mandatory]
Function : platform\_is\_primary\_cpu() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : unsigned long
Return : unsigned int
This function identifies a core by its `MPIDR`, which is passed as the argument,
This function identifies a core by its ``MPIDR``, which is passed as the argument,
to determine whether this core is the primary core or a secondary core. A return
value of zero indicates that the core is not the primary core, while a non-zero
return value indicates that the core is the primary core.
## Common optional modifications
Common optional modifications
-----------------------------
### Function : platform_get_core_pos()
Function : platform\_get\_core\_pos()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : unsigned long
Return : int
A platform may need to convert the `MPIDR` of a core to an absolute number, which
A platform may need to convert the ``MPIDR`` of a core to an absolute number, which
can be used as a core-specific linear index into blocks of memory (for example
while allocating per-core stacks). This routine contains a simple mechanism
to perform this conversion, using the assumption that each cluster contains a
maximum of four cores:
::
linear index = cpu_id + (cluster_id * 4)
cpu_id = 8-bit value in MPIDR at affinity level 0
cluster_id = 8-bit value in MPIDR at affinity level 1
Function : platform\_set\_stack()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : platform_set_stack()
::
Argument : unsigned long
Return : void
......@@ -364,14 +370,16 @@ This function sets the current stack pointer to the normal memory stack that
has been allocated for the core specified by MPIDR. For BL images that only
require a stack for the primary core the parameter is ignored. The size of
the stack allocated to each core is specified by the platform defined constant
`PLATFORM_STACK_SIZE`.
``PLATFORM_STACK_SIZE``.
Common implementations of this function for the UP and MP BL images are
provided in [plat/common/aarch64/platform_up_stack.S] and
[plat/common/aarch64/platform_mp_stack.S]
provided in `plat/common/aarch64/platform\_up\_stack.S`_ and
`plat/common/aarch64/platform\_mp\_stack.S`_
Function : platform\_get\_stack()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : platform_get_stack()
::
Argument : unsigned long
Return : unsigned long
......@@ -380,105 +388,114 @@ This function returns the base address of the normal memory stack that
has been allocated for the core specificed by MPIDR. For BL images that only
require a stack for the primary core the parameter is ignored. The size of
the stack allocated to each core is specified by the platform defined constant
`PLATFORM_STACK_SIZE`.
``PLATFORM_STACK_SIZE``.
Common implementations of this function for the UP and MP BL images are
provided in [plat/common/aarch64/platform_up_stack.S] and
[plat/common/aarch64/platform_mp_stack.S]
provided in `plat/common/aarch64/platform\_up\_stack.S`_ and
`plat/common/aarch64/platform\_mp\_stack.S`_
## Modifications for Power State Coordination Interface (in BL31)
Modifications for Power State Coordination Interface (in BL31)
--------------------------------------------------------------
The following functions must be implemented to initialize PSCI functionality in
the ARM Trusted Firmware.
Function : plat\_get\_aff\_count() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : plat_get_aff_count() [mandatory]
::
Argument : unsigned int, unsigned long
Return : unsigned int
This function may execute with the MMU and data caches enabled if the platform
port does the necessary initializations in `bl31_plat_arch_setup()`. It is only
port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
called by the primary core.
This function is called by the PSCI initialization code to detect the system
topology. Its purpose is to return the number of affinity instances implemented
at a given `affinity level` (specified by the first argument) and a given
`MPIDR` (specified by the second argument). For example, on a dual-cluster
at a given ``affinity level`` (specified by the first argument) and a given
``MPIDR`` (specified by the second argument). For example, on a dual-cluster
system where first cluster implements two cores and the second cluster
implements four cores, a call to this function with an `MPIDR` corresponding
to the first cluster (`0x0`) and affinity level 0, would return 2. A call
to this function with an `MPIDR` corresponding to the second cluster (`0x100`)
implements four cores, a call to this function with an ``MPIDR`` corresponding
to the first cluster (``0x0``) and affinity level 0, would return 2. A call
to this function with an ``MPIDR`` corresponding to the second cluster (``0x100``)
and affinity level 0, would return 4.
Function : plat\_get\_aff\_state() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : plat_get_aff_state() [mandatory]
::
Argument : unsigned int, unsigned long
Return : unsigned int
This function may execute with the MMU and data caches enabled if the platform
port does the necessary initializations in `bl31_plat_arch_setup()`. It is only
port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
called by the primary core.
This function is called by the PSCI initialization code. Its purpose is to
return the state of an affinity instance. The affinity instance is determined by
the affinity ID at a given `affinity level` (specified by the first argument)
and an `MPIDR` (specified by the second argument). The state can be one of
`PSCI_AFF_PRESENT` or `PSCI_AFF_ABSENT`. The latter state is used to cater for
the affinity ID at a given ``affinity level`` (specified by the first argument)
and an ``MPIDR`` (specified by the second argument). The state can be one of
``PSCI_AFF_PRESENT`` or ``PSCI_AFF_ABSENT``. The latter state is used to cater for
system topologies where certain affinity instances are unimplemented. For
example, consider a platform that implements a single cluster with four cores and
another core implemented directly on the interconnect with the cluster. The
`MPIDR`s of the cluster would range from `0x0-0x3`. The `MPIDR` of the single
``MPIDR``\ s of the cluster would range from ``0x0-0x3``. The ``MPIDR`` of the single
core is 0x100 to indicate that it does not belong to cluster 0. Cluster 1
is missing but needs to be accounted for to reach this single core in the
topology tree. Therefore it is marked as `PSCI_AFF_ABSENT`.
topology tree. Therefore it is marked as ``PSCI_AFF_ABSENT``.
Function : platform\_setup\_pm() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : platform_setup_pm() [mandatory]
::
Argument : const plat_pm_ops **
Return : int
This function may execute with the MMU and data caches enabled if the platform
port does the necessary initializations in `bl31_plat_arch_setup()`. It is only
port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
called by the primary core.
This function is called by PSCI initialization code. Its purpose is to export
handler routines for platform-specific power management actions by populating
the passed pointer with a pointer to the private `plat_pm_ops` structure of
the passed pointer with a pointer to the private ``plat_pm_ops`` structure of
BL31.
A description of each member of this structure is given below. A platform port
is expected to implement these handlers if the corresponding PSCI operation
is to be supported and these handlers are expected to succeed if the return
type is `void`.
type is ``void``.
#### plat_pm_ops.affinst_standby()
plat\_pm\_ops.affinst\_standby()
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Perform the platform-specific setup to enter the standby state indicated by the
passed argument. The generic code expects the handler to succeed.
#### plat_pm_ops.affinst_on()
plat\_pm\_ops.affinst\_on()
^^^^^^^^^^^^^^^^^^^^^^^^^^^
Perform the platform specific setup to power on an affinity instance, specified
by the `MPIDR` (first argument) and `affinity level` (third argument). The
`state` (fourth argument) contains the current state of that affinity instance
by the ``MPIDR`` (first argument) and ``affinity level`` (third argument). The
``state`` (fourth argument) contains the current state of that affinity instance
(ON or OFF). This is useful to determine whether any action must be taken. For
example, while powering on a core, the cluster that contains this core might
already be in the ON state. The platform decides what actions must be taken to
transition from the current state to the target state (indicated by the power
management operation). The generic code expects the platform to return
E_SUCCESS on success or E_INTERN_FAIL for any failure.
E\_SUCCESS on success or E\_INTERN\_FAIL for any failure.
#### plat_pm_ops.affinst_off()
plat\_pm\_ops.affinst\_off()
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Perform the platform specific setup to power off an affinity instance of the
calling core. It is called by the PSCI `CPU_OFF` API implementation.
calling core. It is called by the PSCI ``CPU_OFF`` API implementation.
The `affinity level` (first argument) and `state` (second argument) have
a similar meaning as described in the `affinst_on()` operation. They
The ``affinity level`` (first argument) and ``state`` (second argument) have
a similar meaning as described in the ``affinst_on()`` operation. They
identify the affinity instance on which the call is made and its
current state. This gives the platform port an indication of the
state transition it must make to perform the requested action. For example, if
......@@ -486,14 +503,15 @@ the calling core is the last powered on core in the cluster, after powering down
affinity level 0 (the core), the platform port should power down affinity
level 1 (the cluster) as well. The generic code expects the handler to succeed.
#### plat_pm_ops.affinst_suspend()
plat\_pm\_ops.affinst\_suspend()
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Perform the platform specific setup to power off an affinity instance of the
calling core. It is called by the PSCI `CPU_SUSPEND` API and `SYSTEM_SUSPEND`
calling core. It is called by the PSCI ``CPU_SUSPEND`` API and ``SYSTEM_SUSPEND``
API implementation
The `affinity level` (second argument) and `state` (third argument) have a
similar meaning as described in the `affinst_on()` operation. They are used to
The ``affinity level`` (second argument) and ``state`` (third argument) have a
similar meaning as described in the ``affinst_on()`` operation. They are used to
identify the affinity instance on which the call is made and its current state.
This gives the platform port an indication of the state transition it must
make to perform the requested action. For example, if the calling core is the
......@@ -503,73 +521,76 @@ as well.
The difference between turning an affinity instance off and suspending it
is that in the former case, the affinity instance is expected to re-initialize
its state when it is next powered on (see `affinst_on_finish()`). In the latter
its state when it is next powered on (see ``affinst_on_finish()``). In the latter
case, the affinity instance is expected to save enough state so that it can
resume execution by restoring this state when it is powered on (see
`affinst_suspend_finish()`).The generic code expects the handler to succeed.
``affinst_suspend_finish()``).The generic code expects the handler to succeed.
#### plat_pm_ops.affinst_on_finish()
plat\_pm\_ops.affinst\_on\_finish()
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This function is called by the PSCI implementation after the calling core is
powered on and released from reset in response to an earlier PSCI `CPU_ON` call.
powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
It performs the platform-specific setup required to initialize enough state for
this core to enter the Normal world and also provide secure runtime firmware
services.
The `affinity level` (first argument) and `state` (second argument) have a
The ``affinity level`` (first argument) and ``state`` (second argument) have a
similar meaning as described in the previous operations. The generic code
expects the handler to succeed.
#### plat_pm_ops.affinst_suspend_finish()
plat\_pm\_ops.affinst\_suspend\_finish()
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This function is called by the PSCI implementation after the calling core is
powered on and released from reset in response to an asynchronous wakeup
event, for example a timer interrupt that was programmed by the core during the
`CPU_SUSPEND` call or `SYSTEM_SUSPEND` call. It performs the platform-specific
``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific
setup required to restore the saved state for this core to resume execution
in the Normal world and also provide secure runtime firmware services.
The `affinity level` (first argument) and `state` (second argument) have a
The ``affinity level`` (first argument) and ``state`` (second argument) have a
similar meaning as described in the previous operations. The generic code
expects the platform to succeed.
#### plat_pm_ops.validate_power_state()
plat\_pm\_ops.validate\_power\_state()
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This function is called by the PSCI implementation during the `CPU_SUSPEND`
call to validate the `power_state` parameter of the PSCI API. If the
`power_state` is known to be invalid, the platform must return
PSCI_E_INVALID_PARAMS as an error, which is propagated back to the Normal
This function is called by the PSCI implementation during the ``CPU_SUSPEND``
call to validate the ``power_state`` parameter of the PSCI API. If the
``power_state`` is known to be invalid, the platform must return
PSCI\_E\_INVALID\_PARAMS as an error, which is propagated back to the Normal
world PSCI client.
#### plat_pm_ops.validate_ns_entrypoint()
plat\_pm\_ops.validate\_ns\_entrypoint()
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This function is called by the PSCI implementation during the `CPU_SUSPEND`,
`SYSTEM_SUSPEND` and `CPU_ON` calls to validate the Non-secure `entry_point`
parameter passed by the Normal world. If the `entry_point` is known to be
invalid, the platform must return PSCI_E_INVALID_PARAMS as an error, which is
This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the Non-secure ``entry_point``
parameter passed by the Normal world. If the ``entry_point`` is known to be
invalid, the platform must return PSCI\_E\_INVALID\_PARAMS as an error, which is
propagated back to the Normal world PSCI client.
#### plat_pm_ops.get_sys_suspend_power_state()
plat\_pm\_ops.get\_sys\_suspend\_power\_state()
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This function is called by the PSCI implementation during the `SYSTEM_SUSPEND`
call to return the `power_state` parameter. This allows the platform to encode
the appropriate State-ID field within the `power_state` parameter which can be
utilized in `affinst_suspend()` to suspend to system affinity level. The
`power_state` parameter should be in the same format as specified by the
PSCI specification for the CPU_SUSPEND API.
This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
call to return the ``power_state`` parameter. This allows the platform to encode
the appropriate State-ID field within the ``power_state`` parameter which can be
utilized in ``affinst_suspend()`` to suspend to system affinity level. The
``power_state`` parameter should be in the same format as specified by the
PSCI specification for the CPU\_SUSPEND API.
- - - - - - - - - - - - - - - - - - - - - - - - - -
--------------
_Copyright (c) 2015, ARM Limited and Contributors. All rights reserved._
*Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.*
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
.. _Porting Guide: porting-guide.rst#user-content-function--plat_my_core_pos
.. _psci pd tree: psci-pd-tree.rst
.. _plat/arm/board/fvp/fvp\_pm.c: ../plat/arm/board/fvp/fvp_pm.c
.. _38dce70f51fb83b27958ba3e2ad15f5635cb1061: https://github.com/ARM-software/arm-trusted-firmware/commit/38dce70f51fb83b27958ba3e2ad15f5635cb1061
.. _plat/common/aarch64/platform\_up\_stack.S: ../plat/common/aarch64/platform_up_stack.S
.. _plat/common/aarch64/platform\_mp\_stack.S: ../plat/common/aarch64/platform_mp_stack.S
[Porting Guide]: porting-guide.md
[Power Domain Topology Design]: psci-pd-tree.md
[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
[psci pd tree]: psci-pd-tree.md
[my_core_pos]: porting-guide.md#function--plat_my_core_pos
[get_target_pwr_state]: porting-guide.md#function--plat_get_target_pwr_state-optional
[psci_ops]: porting-guide.md#function--plat_setup_psci_ops-mandatory
[plat/arm/board/fvp/fvp_pm.c]: ../plat/arm/board/fvp/fvp_pm.c
[plat/common/aarch64/platform_mp_stack.S]: ../plat/common/aarch64/platform_mp_stack.S
[plat/common/aarch64/platform_up_stack.S]: ../plat/common/aarch64/platform_up_stack.S
.. |Image 1| image:: diagrams/psci-suspend-sequence.png?raw=true
docs/porting-guide.md → docs/porting-guide.rst
View file @ 7cefb56d
ARM Trusted Firmware Porting Guide
==================================
Contents
--------
1. [Introduction](#1--introduction)
2. [Common Modifications](#2--common-modifications)
* [Common mandatory modifications](#21-common-mandatory-modifications)
* [Handling reset](#22-handling-reset)
* [Common mandatory function modifications](#23-common-mandatory-function-modifications)
* [Common optional modifications](#24-common-optional-modifications)
3. [Boot Loader stage specific modifications](#3--modifications-specific-to-a-boot-loader-stage)
* [Boot Loader stage 1 (BL1)](#31-boot-loader-stage-1-bl1)
* [Boot Loader stage 2 (BL2)](#32-boot-loader-stage-2-bl2)
* [FWU Boot Loader stage 2 (BL2U)](#33-fwu-boot-loader-stage-2-bl2u)
* [Boot Loader stage 3-1 (BL31)](#34-boot-loader-stage-3-1-bl31)
* [PSCI implementation (in BL31)](#35-power-state-coordination-interface-in-bl31)
* [Interrupt Management framework (in BL31)](#36--interrupt-management-framework-in-bl31)
* [Crash Reporting mechanism (in BL31)](#37--crash-reporting-mechanism-in-bl31)
4. [Build flags](#4--build-flags)
5. [C Library](#5--c-library)
6. [Storage abstraction layer](#6--storage-abstraction-layer)
- - - - - - - - - - - - - - - - - -
1. Introduction
----------------
.. section-numbering::
:suffix: .
.. contents::
--------------
Introduction
------------
Please note that this document has been updated for the new platform API
as required by the PSCI v1.0 implementation. Please refer to the
[Migration Guide] for the previous platform API.
`Migration Guide`_ for the previous platform API.
Porting the ARM Trusted Firmware to a new platform involves making some
mandatory and optional modifications for both the cold and warm boot paths.
Modifications consist of:
* Implementing a platform-specific function or variable,
* Setting up the execution context in a certain way, or
* Defining certain constants (for example #defines).
- Implementing a platform-specific function or variable,
- Setting up the execution context in a certain way, or
- Defining certain constants (for example #defines).
The platform-specific functions and variables are declared in
[include/plat/common/platform.h]. The firmware provides a default implementation
`include/plat/common/platform.h`_. The firmware provides a default implementation
of variables and functions to fulfill the optional requirements. These
implementations are all weakly defined; they are provided to ease the porting
effort. Each platform port can override them with its own implementation if the
default implementation is inadequate.
Platform ports that want to be aligned with standard ARM platforms (for example
FVP and Juno) may also use [include/plat/arm/common/plat_arm.h] and the
corresponding source files in `plat/arm/common/`. These provide standard
FVP and Juno) may also use `include/plat/arm/common/plat\_arm.h`_ and the
corresponding source files in ``plat/arm/common/``. These provide standard
implementations for some of the required platform porting functions. However,
using these functions requires the platform port to implement additional
ARM standard platform porting functions. These additional functions are not
......@@ -59,24 +44,22 @@ discusses these in detail. The subsequent sections discuss the remaining
modifications for each BL stage in detail.
This document should be read in conjunction with the ARM Trusted Firmware
[User Guide].
`User Guide`_.
2. Common modifications
------------------------
Common modifications
--------------------
This section covers the modifications that should be made by the platform for
each BL stage to correctly port the firmware stack. They are categorized as
either mandatory or optional.
2.1 Common mandatory modifications
----------------------------------
Common mandatory modifications
------------------------------
A platform port must enable the Memory Management Unit (MMU) as well as the
instruction and data caches for each BL stage. Setting up the translation
tables is the responsibility of the platform port because memory maps differ
across platforms. A memory translation library (see `lib/xlat_tables/`) is
across platforms. A memory translation library (see ``lib/xlat_tables/``) is
provided to help in this setup. Note that although this library supports
non-identity mappings, this is intended only for re-mapping peripheral physical
addresses and allows platforms with high I/O addresses to reduce their virtual
......@@ -84,24 +67,28 @@ address space. All other addresses corresponding to code and data must currently
use an identity mapping.
In ARM standard platforms, each BL stage configures the MMU in the
platform-specific architecture setup function, `blX_plat_arch_setup()`, and uses
platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses
an identity mapping for all addresses.
If the build option `USE_COHERENT_MEM` is enabled, each platform can allocate a
If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a
block of identity mapped secure memory with Device-nGnRE attributes aligned to
page boundary (4K) for each BL stage. All sections which allocate coherent
memory are grouped under `coherent_ram`. For ex: Bakery locks are placed in a
section identified by name `bakery_lock` inside `coherent_ram` so that its
memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a
section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its
possible for the firmware to place variables in it using the following C code
directive:
::
__section("bakery_lock")
Or alternatively the following assembler code directive:
::
.section bakery_lock
The `coherent_ram` section is a sum of all sections like `bakery_lock` which are
The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are
used to allocate any data structures that are accessed both when a CPU is
executing with its MMU and caches enabled, and when it's running with its MMU
and caches disabled. Examples are given below.
......@@ -109,63 +96,63 @@ and caches disabled. Examples are given below.
The following variables, functions and constants must be defined by the platform
for the firmware to work correctly.
### File : platform_def.h [mandatory]
File : platform\_def.h [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Each platform must ensure that a header file of this name is in the system
include path with the following constants defined. This may require updating the
list of `PLAT_INCLUDES` in the `platform.mk` file. In the ARM development
platforms, this file is found in `plat/arm/board/<plat_name>/include/`.
list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. In the ARM development
platforms, this file is found in ``plat/arm/board/<plat_name>/include/``.
Platform ports may optionally use the file [include/plat/common/common_def.h],
Platform ports may optionally use the file `include/plat/common/common\_def.h`_,
which provides typical values for some of the constants below. These values are
likely to be suitable for all platform ports.
Platform ports that want to be aligned with standard ARM platforms (for example
FVP and Juno) may also use [include/plat/arm/common/arm_def.h], which provides
FVP and Juno) may also use `include/plat/arm/common/arm\_def.h`_, which provides
standard values for some of the constants below. However, this requires the
platform port to define additional platform porting constants in
`platform_def.h`. These additional constants are not documented here.
``platform_def.h``. These additional constants are not documented here.
* **#define : PLATFORM_LINKER_FORMAT**
- **#define : PLATFORM\_LINKER\_FORMAT**
Defines the linker format used by the platform, for example
`elf64-littleaarch64`.
``elf64-littleaarch64``.
* **#define : PLATFORM_LINKER_ARCH**
- **#define : PLATFORM\_LINKER\_ARCH**
Defines the processor architecture for the linker by the platform, for
example `aarch64`.
example ``aarch64``.
* **#define : PLATFORM_STACK_SIZE**
- **#define : PLATFORM\_STACK\_SIZE**
Defines the normal stack memory available to each CPU. This constant is used
by [plat/common/aarch64/platform_mp_stack.S] and
[plat/common/aarch64/platform_up_stack.S].
by `plat/common/aarch64/platform\_mp\_stack.S`_ and
`plat/common/aarch64/platform\_up\_stack.S`_.
* **define : CACHE_WRITEBACK_GRANULE**
- **define : CACHE\_WRITEBACK\_GRANULE**
Defines the size in bits of the largest cache line across all the cache
levels in the platform.
* **#define : FIRMWARE_WELCOME_STR**
- **#define : FIRMWARE\_WELCOME\_STR**
Defines the character string printed by BL1 upon entry into the `bl1_main()`
Defines the character string printed by BL1 upon entry into the ``bl1_main()``
function.
* **#define : PLATFORM_CORE_COUNT**
- **#define : PLATFORM\_CORE\_COUNT**
Defines the total number of CPUs implemented by the platform across all
clusters in the system.
* **#define : PLAT_NUM_PWR_DOMAINS**
- **#define : PLAT\_NUM\_PWR\_DOMAINS**
Defines the total number of nodes in the power domain topology
tree at all the power domain levels used by the platform.
This macro is used by the PSCI implementation to allocate
data structures to represent power domain topology.
* **#define : PLAT_MAX_PWR_LVL**
- **#define : PLAT\_MAX\_PWR\_LVL**
Defines the maximum power domain level that the power management operations
should apply to. More often, but not always, the power domain level
......@@ -175,24 +162,24 @@ platform port to define additional platform porting constants in
example, the Base AEM FVP implements two clusters with a configurable
number of CPUs and it reports the maximum power domain level as 1.
* **#define : PLAT_MAX_OFF_STATE**
- **#define : PLAT\_MAX\_OFF\_STATE**
Defines the local power state corresponding to the deepest power down
possible at every power domain level in the platform. The local power
states for each level may be sparsely allocated between 0 and this value
with 0 being reserved for the RUN state. The PSCI implementation uses this
value to initialize the local power states of the power domain nodes and
to specify the requested power state for a PSCI_CPU_OFF call.
to specify the requested power state for a PSCI\_CPU\_OFF call.
* **#define : PLAT_MAX_RET_STATE**
- **#define : PLAT\_MAX\_RET\_STATE**
Defines the local power state corresponding to the deepest retention state
possible at every power domain level in the platform. This macro should be
a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the
a value less than PLAT\_MAX\_OFF\_STATE and greater than 0. It is used by the
PSCI implementation to distinguish between retention and power down local
power states within PSCI_CPU_SUSPEND call.
power states within PSCI\_CPU\_SUSPEND call.
* **#define : PLAT_MAX_PWR_LVL_STATES**
- **#define : PLAT\_MAX\_PWR\_LVL\_STATES**
Defines the maximum number of local power states per power domain level
that the platform supports. The default value of this macro is 2 since
......@@ -201,43 +188,43 @@ platform port to define additional platform porting constants in
account for more local power states, then it must redefine this macro.
Currently, this macro is used by the Generic PSCI implementation to size
the array used for PSCI_STAT_COUNT/RESIDENCY accounting.
the array used for PSCI\_STAT\_COUNT/RESIDENCY accounting.
* **#define : BL1_RO_BASE**
- **#define : BL1\_RO\_BASE**
Defines the base address in secure ROM where BL1 originally lives. Must be
aligned on a page-size boundary.
* **#define : BL1_RO_LIMIT**
- **#define : BL1\_RO\_LIMIT**
Defines the maximum address in secure ROM that BL1's actual content (i.e.
excluding any data section allocated at runtime) can occupy.
* **#define : BL1_RW_BASE**
- **#define : BL1\_RW\_BASE**
Defines the base address in secure RAM where BL1's read-write data will live
at runtime. Must be aligned on a page-size boundary.
* **#define : BL1_RW_LIMIT**
- **#define : BL1\_RW\_LIMIT**
Defines the maximum address in secure RAM that BL1's read-write data can
occupy at runtime.
* **#define : BL2_BASE**
- **#define : BL2\_BASE**
Defines the base address in secure RAM where BL1 loads the BL2 binary image.
Must be aligned on a page-size boundary.
* **#define : BL2_LIMIT**
- **#define : BL2\_LIMIT**
Defines the maximum address in secure RAM that the BL2 image can occupy.
* **#define : BL31_BASE**
- **#define : BL31\_BASE**
Defines the base address in secure RAM where BL2 loads the BL31 binary
image. Must be aligned on a page-size boundary.
* **#define : BL31_LIMIT**
- **#define : BL31\_LIMIT**
Defines the maximum address in secure RAM that the BL31 image can occupy.
......@@ -249,185 +236,185 @@ information about the image to be loaded (file handler, load address,
authentication information, etc.). The following image identifiers are
mandatory:
* **#define : BL2_IMAGE_ID**
- **#define : BL2\_IMAGE\_ID**
BL2 image identifier, used by BL1 to load BL2.
* **#define : BL31_IMAGE_ID**
- **#define : BL31\_IMAGE\_ID**
BL31 image identifier, used by BL2 to load BL31.
* **#define : BL33_IMAGE_ID**
- **#define : BL33\_IMAGE\_ID**
BL33 image identifier, used by BL2 to load BL33.
If Trusted Board Boot is enabled, the following certificate identifiers must
also be defined:
* **#define : TRUSTED_BOOT_FW_CERT_ID**
- **#define : TRUSTED\_BOOT\_FW\_CERT\_ID**
BL2 content certificate identifier, used by BL1 to load the BL2 content
certificate.
* **#define : TRUSTED_KEY_CERT_ID**
- **#define : TRUSTED\_KEY\_CERT\_ID**
Trusted key certificate identifier, used by BL2 to load the trusted key
certificate.
* **#define : SOC_FW_KEY_CERT_ID**
- **#define : SOC\_FW\_KEY\_CERT\_ID**
BL31 key certificate identifier, used by BL2 to load the BL31 key
certificate.
* **#define : SOC_FW_CONTENT_CERT_ID**
- **#define : SOC\_FW\_CONTENT\_CERT\_ID**
BL31 content certificate identifier, used by BL2 to load the BL31 content
certificate.
* **#define : NON_TRUSTED_FW_KEY_CERT_ID**
- **#define : NON\_TRUSTED\_FW\_KEY\_CERT\_ID**
BL33 key certificate identifier, used by BL2 to load the BL33 key
certificate.
* **#define : NON_TRUSTED_FW_CONTENT_CERT_ID**
- **#define : NON\_TRUSTED\_FW\_CONTENT\_CERT\_ID**
BL33 content certificate identifier, used by BL2 to load the BL33 content
certificate.
* **#define : FWU_CERT_ID**
- **#define : FWU\_CERT\_ID**
Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the
Firmware Update (FWU) certificate identifier, used by NS\_BL1U to load the
FWU content certificate.
* **#define : PLAT_CRYPTOCELL_BASE**
- **#define : PLAT\_CRYPTOCELL\_BASE**
This defines the base address of ARM® TrustZone® CryptoCell and must be
defined if CryptoCell crypto driver is used for Trusted Board Boot. For
capable ARM platforms, this driver is used if `ARM_CRYPTOCELL_INTEG` is
capable ARM platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is
set.
If the AP Firmware Updater Configuration image, BL2U is used, the following
must also be defined:
* **#define : BL2U_BASE**
- **#define : BL2U\_BASE**
Defines the base address in secure memory where BL1 copies the BL2U binary
image. Must be aligned on a page-size boundary.
* **#define : BL2U_LIMIT**
- **#define : BL2U\_LIMIT**
Defines the maximum address in secure memory that the BL2U image can occupy.
* **#define : BL2U_IMAGE_ID**
- **#define : BL2U\_IMAGE\_ID**
BL2U image identifier, used by BL1 to fetch an image descriptor
corresponding to BL2U.
If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following
If the SCP Firmware Update Configuration Image, SCP\_BL2U is used, the following
must also be defined:
* **#define : SCP_BL2U_IMAGE_ID**
- **#define : SCP\_BL2U\_IMAGE\_ID**
SCP_BL2U image identifier, used by BL1 to fetch an image descriptor
corresponding to SCP_BL2U.
SCP\_BL2U image identifier, used by BL1 to fetch an image descriptor
corresponding to SCP\_BL2U.
NOTE: TF does not provide source code for this image.
If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must
If the Non-Secure Firmware Updater ROM, NS\_BL1U is used, the following must
also be defined:
* **#define : NS_BL1U_BASE**
- **#define : NS\_BL1U\_BASE**
Defines the base address in non-secure ROM where NS_BL1U executes.
Defines the base address in non-secure ROM where NS\_BL1U executes.
Must be aligned on a page-size boundary.
NOTE: TF does not provide source code for this image.
* **#define : NS_BL1U_IMAGE_ID**
- **#define : NS\_BL1U\_IMAGE\_ID**
NS_BL1U image identifier, used by BL1 to fetch an image descriptor
corresponding to NS_BL1U.
NS\_BL1U image identifier, used by BL1 to fetch an image descriptor
corresponding to NS\_BL1U.
If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also
If the Non-Secure Firmware Updater, NS\_BL2U is used, the following must also
be defined:
* **#define : NS_BL2U_BASE**
- **#define : NS\_BL2U\_BASE**
Defines the base address in non-secure memory where NS_BL2U executes.
Defines the base address in non-secure memory where NS\_BL2U executes.
Must be aligned on a page-size boundary.
NOTE: TF does not provide source code for this image.
* **#define : NS_BL2U_IMAGE_ID**
- **#define : NS\_BL2U\_IMAGE\_ID**
NS_BL2U image identifier, used by BL1 to fetch an image descriptor
corresponding to NS_BL2U.
NS\_BL2U image identifier, used by BL1 to fetch an image descriptor
corresponding to NS\_BL2U.
For the the Firmware update capability of TRUSTED BOARD BOOT, the following
macros may also be defined:
* **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES**
- **#define : PLAT\_FWU\_MAX\_SIMULTANEOUS\_IMAGES**
Total number of images that can be loaded simultaneously. If the platform
doesn't specify any value, it defaults to 10.
If a SCP_BL2 image is supported by the platform, the following constants must
If a SCP\_BL2 image is supported by the platform, the following constants must
also be defined:
* **#define : SCP_BL2_IMAGE_ID**
- **#define : SCP\_BL2\_IMAGE\_ID**
SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory
SCP\_BL2 image identifier, used by BL2 to load SCP\_BL2 into secure memory
from platform storage before being transfered to the SCP.
* **#define : SCP_FW_KEY_CERT_ID**
- **#define : SCP\_FW\_KEY\_CERT\_ID**
SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key
SCP\_BL2 key certificate identifier, used by BL2 to load the SCP\_BL2 key
certificate (mandatory when Trusted Board Boot is enabled).
* **#define : SCP_FW_CONTENT_CERT_ID**
- **#define : SCP\_FW\_CONTENT\_CERT\_ID**
SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2
SCP\_BL2 content certificate identifier, used by BL2 to load the SCP\_BL2
content certificate (mandatory when Trusted Board Boot is enabled).
If a BL32 image is supported by the platform, the following constants must
also be defined:
* **#define : BL32_IMAGE_ID**
- **#define : BL32\_IMAGE\_ID**
BL32 image identifier, used by BL2 to load BL32.
* **#define : TRUSTED_OS_FW_KEY_CERT_ID**
- **#define : TRUSTED\_OS\_FW\_KEY\_CERT\_ID**
BL32 key certificate identifier, used by BL2 to load the BL32 key
certificate (mandatory when Trusted Board Boot is enabled).
* **#define : TRUSTED_OS_FW_CONTENT_CERT_ID**
- **#define : TRUSTED\_OS\_FW\_CONTENT\_CERT\_ID**
BL32 content certificate identifier, used by BL2 to load the BL32 content
certificate (mandatory when Trusted Board Boot is enabled).
* **#define : BL32_BASE**
- **#define : BL32\_BASE**
Defines the base address in secure memory where BL2 loads the BL32 binary
image. Must be aligned on a page-size boundary.
* **#define : BL32_LIMIT**
- **#define : BL32\_LIMIT**
Defines the maximum address that the BL32 image can occupy.
If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the
platform, the following constants must also be defined:
* **#define : TSP_SEC_MEM_BASE**
- **#define : TSP\_SEC\_MEM\_BASE**
Defines the base address of the secure memory used by the TSP image on the
platform. This must be at the same address or below `BL32_BASE`.
platform. This must be at the same address or below ``BL32_BASE``.
* **#define : TSP_SEC_MEM_SIZE**
- **#define : TSP\_SEC\_MEM\_SIZE**
Defines the size of the secure memory used by the BL32 image on the
platform. `TSP_SEC_MEM_BASE` and `TSP_SEC_MEM_SIZE` must fully accomodate
the memory required by the BL32 image, defined by `BL32_BASE` and
`BL32_LIMIT`.
platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully accomodate
the memory required by the BL32 image, defined by ``BL32_BASE`` and
``BL32_LIMIT``.
* **#define : TSP_IRQ_SEC_PHY_TIMER**
- **#define : TSP\_IRQ\_SEC\_PHY\_TIMER**
Defines the ID of the secure physical generic timer interrupt used by the
TSP's interrupt handling code.
......@@ -435,81 +422,81 @@ platform, the following constants must also be defined:
If the platform port uses the translation table library code, the following
constants must also be defined:
* **#define : PLAT_XLAT_TABLES_DYNAMIC**
- **#define : PLAT\_XLAT\_TABLES\_DYNAMIC**
Optional flag that can be set per-image to enable the dynamic allocation of
regions even when the MMU is enabled. If not defined, only static
functionality will be available, if defined and set to 1 it will also
include the dynamic functionality.
* **#define : MAX_XLAT_TABLES**
- **#define : MAX\_XLAT\_TABLES**
Defines the maximum number of translation tables that are allocated by the
translation table library code. To minimize the amount of runtime memory
used, choose the smallest value needed to map the required virtual addresses
for each BL stage. If `PLAT_XLAT_TABLES_DYNAMIC` flag is enabled for a BL
image, `MAX_XLAT_TABLES` must be defined to accommodate the dynamic regions
for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL
image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions
as well.
* **#define : MAX_MMAP_REGIONS**
- **#define : MAX\_MMAP\_REGIONS**
Defines the maximum number of regions that are allocated by the translation
table library code. A region consists of physical base address, virtual base
address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
defined in the `mmap_region_t` structure. The platform defines the regions
defined in the ``mmap_region_t`` structure. The platform defines the regions
that should be mapped. Then, the translation table library will create the
corresponding tables and descriptors at runtime. To minimize the amount of
runtime memory used, choose the smallest value needed to register the
required regions for each BL stage. If `PLAT_XLAT_TABLES_DYNAMIC` flag is
enabled for a BL image, `MAX_MMAP_REGIONS` must be defined to accommodate
required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is
enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate
the dynamic regions as well.
* **#define : ADDR_SPACE_SIZE**
- **#define : ADDR\_SPACE\_SIZE**
Defines the total size of the address space in bytes. For example, for a 32
bit address space, this value should be `(1ull << 32)`. This definition is
now deprecated, platforms should use `PLAT_PHY_ADDR_SPACE_SIZE` and
`PLAT_VIRT_ADDR_SPACE_SIZE` instead.
bit address space, this value should be ``(1ull << 32)``. This definition is
now deprecated, platforms should use ``PLAT_PHY_ADDR_SPACE_SIZE`` and
``PLAT_VIRT_ADDR_SPACE_SIZE`` instead.
* **#define : PLAT_VIRT_ADDR_SPACE_SIZE**
- **#define : PLAT\_VIRT\_ADDR\_SPACE\_SIZE**
Defines the total size of the virtual address space in bytes. For example,
for a 32 bit virtual address space, this value should be `(1ull << 32)`.
for a 32 bit virtual address space, this value should be ``(1ull << 32)``.
* **#define : PLAT_PHY_ADDR_SPACE_SIZE**
- **#define : PLAT\_PHY\_ADDR\_SPACE\_SIZE**
Defines the total size of the physical address space in bytes. For example,
for a 32 bit physical address space, this value should be `(1ull << 32)`.
for a 32 bit physical address space, this value should be ``(1ull << 32)``.
If the platform port uses the IO storage framework, the following constants
must also be defined:
* **#define : MAX_IO_DEVICES**
- **#define : MAX\_IO\_DEVICES**
Defines the maximum number of registered IO devices. Attempting to register
more devices than this value using `io_register_device()` will fail with
more devices than this value using ``io_register_device()`` will fail with
-ENOMEM.
* **#define : MAX_IO_HANDLES**
- **#define : MAX\_IO\_HANDLES**
Defines the maximum number of open IO handles. Attempting to open more IO
entities than this value using `io_open()` will fail with -ENOMEM.
entities than this value using ``io_open()`` will fail with -ENOMEM.
* **#define : MAX_IO_BLOCK_DEVICES**
- **#define : MAX\_IO\_BLOCK\_DEVICES**
Defines the maximum number of registered IO block devices. Attempting to
register more devices this value using `io_dev_open()` will fail
with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES.
register more devices this value using ``io_dev_open()`` will fail
with -ENOMEM. MAX\_IO\_BLOCK\_DEVICES should be less than MAX\_IO\_DEVICES.
With this macro, multiple block devices could be supported at the same
time.
If the platform needs to allocate data within the per-cpu data framework in
BL31, it should define the following macro. Currently this is only required if
the platform decides not to use the coherent memory section by undefining the
`USE_COHERENT_MEM` build flag. In this case, the framework allocates the
``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the
required memory within the the per-cpu data to minimize wastage.
* **#define : PLAT_PCPU_DATA_SIZE**
- **#define : PLAT\_PCPU\_DATA\_SIZE**
Defines the memory (in bytes) to be reserved within the per-cpu data
structure for use by the platform layer.
......@@ -517,56 +504,54 @@ required memory within the the per-cpu data to minimize wastage.
The following constants are optional. They should be defined when the platform
memory layout implies some image overlaying like in ARM standard platforms.
* **#define : BL31_PROGBITS_LIMIT**
- **#define : BL31\_PROGBITS\_LIMIT**
Defines the maximum address in secure RAM that the BL31's progbits sections
can occupy.
* **#define : TSP_PROGBITS_LIMIT**
- **#define : TSP\_PROGBITS\_LIMIT**
Defines the maximum address that the TSP's progbits sections can occupy.
If the platform port uses the PL061 GPIO driver, the following constant may
optionally be defined:
* **PLAT_PL061_MAX_GPIOS**
- **PLAT\_PL061\_MAX\_GPIOS**
Maximum number of GPIOs required by the platform. This allows control how
much memory is allocated for PL061 GPIO controllers. The default value is
32.
[For example, define the build flag in platform.mk]:
PLAT_PL061_MAX_GPIOS := 160
$(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
#. $(eval $(call add\_define,PLAT\_PL061\_MAX\_GPIOS))
If the platform port uses the partition driver, the following constant may
optionally be defined:
* **PLAT_PARTITION_MAX_ENTRIES**
- **PLAT\_PARTITION\_MAX\_ENTRIES**
Maximum number of partition entries required by the platform. This allows
control how much memory is allocated for partition entries. The default
value is 128.
[For example, define the build flag in platform.mk]:
PLAT_PARTITION_MAX_ENTRIES := 12
$(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
`For example, define the build flag in platform.mk`_:
PLAT\_PARTITION\_MAX\_ENTRIES := 12
$(eval $(call add\_define,PLAT\_PARTITION\_MAX\_ENTRIES))
The following constant is optional. It should be defined to override the default
behaviour of the `assert()` function (for example, to save memory).
behaviour of the ``assert()`` function (for example, to save memory).
* **PLAT_LOG_LEVEL_ASSERT**
If `PLAT_LOG_LEVEL_ASSERT` is higher or equal than `LOG_LEVEL_VERBOSE`,
`assert()` prints the name of the file, the line number and the asserted
expression. Else if it is higher than `LOG_LEVEL_INFO`, it prints the file
name and the line number. Else if it is lower than `LOG_LEVEL_INFO`, it
doesn't print anything to the console. If `PLAT_LOG_LEVEL_ASSERT` isn't
defined, it defaults to `LOG_LEVEL`.
- **PLAT\_LOG\_LEVEL\_ASSERT**
If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``,
``assert()`` prints the name of the file, the line number and the asserted
expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file
name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it
doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't
defined, it defaults to ``LOG_LEVEL``.
### File : plat_macros.S [mandatory]
File : plat\_macros.S [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Each platform must ensure a file of this name is in the system include path with
the following macro defined. In the ARM development platforms, this file is
found in `plat/arm/board/<plat_name>/include/plat_macros.S`.
found in ``plat/arm/board/<plat_name>/include/plat_macros.S``.
* **Macro : plat_crash_print_regs**
- **Macro : plat\_crash\_print\_regs**
This macro allows the crash reporting routine to print relevant platform
registers in case of an unhandled exception in BL31. This aids in debugging
......@@ -576,40 +561,41 @@ found in `plat/arm/board/<plat_name>/include/plat_macros.S`.
For instance, GIC or interconnect registers may be helpful for
troubleshooting.
2.2 Handling Reset
------------------
Handling Reset
--------------
BL1 by default implements the reset vector where execution starts from a cold
or warm boot. BL31 can be optionally set as a reset vector using the
`RESET_TO_BL31` make variable.
``RESET_TO_BL31`` make variable.
For each CPU, the reset vector code is responsible for the following tasks:
1. Distinguishing between a cold boot and a warm boot.
#. Distinguishing between a cold boot and a warm boot.
2. In the case of a cold boot and the CPU being a secondary CPU, ensuring that
#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that
the CPU is placed in a platform-specific state until the primary CPU
performs the necessary steps to remove it from this state.
3. In the case of a warm boot, ensuring that the CPU jumps to a platform-
#. In the case of a warm boot, ensuring that the CPU jumps to a platform-
specific address in the BL31 image in the same processor mode as it was
when released from reset.
The following functions need to be implemented by the platform port to enable
reset vector code to perform the above tasks.
Function : plat\_get\_my\_entrypoint() [mandatory when PROGRAMMABLE\_RESET\_ADDRESS == 0]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0]
::
Argument : void
Return : uintptr_t
This function is called with the MMU and caches disabled
(`SCTLR_EL3.M` = 0 and `SCTLR_EL3.C` = 0). The function is responsible for
(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for
distinguishing between a warm and cold reset for the current CPU using
platform-specific means. If it's a warm reset, then it returns the warm
reset entrypoint point provided to `plat_setup_psci_ops()` during
reset entrypoint point provided to ``plat_setup_psci_ops()`` during
BL31 initialization. If it's a cold reset then this function must return zero.
This function does not follow the Procedure Call Standard used by the
......@@ -625,8 +611,10 @@ both on a cold and warm reset. In this case, there is no need to identify the
type of reset nor to query the warm reset entrypoint. Therefore, implementing
this function is not required on such platforms.
Function : plat\_secondary\_cold\_boot\_setup() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
::
Argument : void
......@@ -647,8 +635,10 @@ Note that for platforms that can't release secondary CPUs out of reset, only the
primary CPU will execute the cold boot code. Therefore, implementing this
function is not required on such platforms.
Function : plat\_is\_my\_cpu\_primary() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
::
Argument : void
Return : unsigned int
......@@ -663,8 +653,10 @@ primary CPU will execute the cold boot code. Therefore, there is no need to
distinguish between primary and secondary CPUs and implementing this function is
not required.
Function : platform\_mem\_init() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : platform_mem_init() [mandatory]
::
Argument : void
Return : void
......@@ -672,8 +664,10 @@ not required.
This function is called before any access to data is made by the firmware, in
order to carry out any essential memory initialization.
Function: plat\_get\_rotpk\_info()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function: plat_get_rotpk_info()
::
Argument : void *, void **, unsigned int *, unsigned int *
Return : int
......@@ -683,6 +677,8 @@ pointer to the ROTPK stored in the platform (or a hash of it) and its length.
The ROTPK must be encoded in DER format according to the following ASN.1
structure:
::
AlgorithmIdentifier ::= SEQUENCE {
algorithm OBJECT IDENTIFIER,
parameters ANY DEFINED BY algorithm OPTIONAL
......@@ -695,6 +691,8 @@ structure:
In case the function returns a hash of the key:
::
DigestInfo ::= SEQUENCE {
digestAlgorithm AlgorithmIdentifier,
digest OCTET STRING
......@@ -704,6 +702,8 @@ The function returns 0 on success. Any other value is treated as error by the
Trusted Board Boot. The function also reports extra information related
to the ROTPK in the flags parameter:
::
ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a
hash.
ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK
......@@ -714,7 +714,10 @@ to the ROTPK in the flags parameter:
verifying it against the platform value. This flag
must not be used in a deployed production environment.
### Function: plat_get_nv_ctr()
Function: plat\_get\_nv\_ctr()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void *, unsigned int *
Return : int
......@@ -724,33 +727,37 @@ non-volatile counter value stored in the platform in the second argument. The
cookie in the first argument may be used to select the counter in case the
platform provides more than one (for example, on platforms that use the default
TBBR CoT, the cookie will correspond to the OID values defined in
TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID).
TRUSTED\_FW\_NVCOUNTER\_OID or NON\_TRUSTED\_FW\_NVCOUNTER\_OID).
The function returns 0 on success. Any other value means the counter value could
not be retrieved from the platform.
Function: plat\_set\_nv\_ctr()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function: plat_set_nv_ctr()
::
Argument : void *, unsigned int
Return : int
This function is mandatory when Trusted Board Boot is enabled. It sets a new
counter value in the platform. The cookie in the first argument may be used to
select the counter (as explained in plat_get_nv_ctr()). The second argument is
select the counter (as explained in plat\_get\_nv\_ctr()). The second argument is
the updated counter value to be written to the NV counter.
The function returns 0 on success. Any other value means the counter value could
not be updated.
Function: plat\_set\_nv\_ctr2()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function: plat_set_nv_ctr2()
::
Argument : void *, const auth_img_desc_t *, unsigned int
Return : int
This function is optional when Trusted Board Boot is enabled. If this
interface is defined, then `plat_set_nv_ctr()` need not be defined. The
interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The
first argument passed is a cookie and is typically used to
differentiate between a Non Trusted NV Counter and a Trusted NV
Counter. The second argument is a pointer to an authentication image
......@@ -762,14 +769,16 @@ The function returns 0 on success. Any other value means the counter value
either could not be updated or the authentication image descriptor indicates
that it is not allowed to be updated.
2.3 Common mandatory function modifications
---------------------------------
Common mandatory function modifications
---------------------------------------
The following functions are mandatory functions which need to be implemented
by the platform port.
### Function : plat_my_core_pos()
Function : plat\_my\_core\_pos()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : unsigned int
......@@ -783,30 +792,35 @@ runtime environment. This function can clobber x0 - x8 and must preserve
x9 - x29.
This function plays a crucial role in the power domain topology framework in
PSCI and details of this can be found in [Power Domain Topology Design].
PSCI and details of this can be found in `Power Domain Topology Design`_.
Function : plat\_core\_pos\_by\_mpidr()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : plat_core_pos_by_mpidr()
::
Argument : u_register_t
Return : int
This function validates the `MPIDR` of a CPU and converts it to an index,
This function validates the ``MPIDR`` of a CPU and converts it to an index,
which can be used as a CPU-specific linear index into blocks of memory. In
case the `MPIDR` is invalid, this function returns -1. This function will only
case the ``MPIDR`` is invalid, this function returns -1. This function will only
be invoked by BL31 after the power domain topology is initialized and can
utilize the C runtime environment. For further details about how ARM Trusted
Firmware represents the power domain topology and how this relates to the
linear CPU index, please refer [Power Domain Topology Design].
linear CPU index, please refer `Power Domain Topology Design`_.
2.4 Common optional modifications
---------------------------------
Common optional modifications
-----------------------------
The following are helper functions implemented by the firmware that perform
common platform-specific tasks. A platform may choose to override these
definitions.
### Function : plat_set_my_stack()
Function : plat\_set\_my\_stack()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : void
......@@ -815,14 +829,16 @@ This function sets the current stack pointer to the normal memory stack that
has been allocated for the current CPU. For BL images that only require a
stack for the primary CPU, the UP version of the function is used. The size
of the stack allocated to each CPU is specified by the platform defined
constant `PLATFORM_STACK_SIZE`.
constant ``PLATFORM_STACK_SIZE``.
Common implementations of this function for the UP and MP BL images are
provided in [plat/common/aarch64/platform_up_stack.S] and
[plat/common/aarch64/platform_mp_stack.S]
provided in `plat/common/aarch64/platform\_up\_stack.S`_ and
`plat/common/aarch64/platform\_mp\_stack.S`_
Function : plat\_get\_my\_stack()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : plat_get_my_stack()
::
Argument : void
Return : uintptr_t
......@@ -831,14 +847,16 @@ This function returns the base address of the normal memory stack that
has been allocated for the current CPU. For BL images that only require a
stack for the primary CPU, the UP version of the function is used. The size
of the stack allocated to each CPU is specified by the platform defined
constant `PLATFORM_STACK_SIZE`.
constant ``PLATFORM_STACK_SIZE``.
Common implementations of this function for the UP and MP BL images are
provided in [plat/common/aarch64/platform_up_stack.S] and
[plat/common/aarch64/platform_mp_stack.S]
provided in `plat/common/aarch64/platform\_up\_stack.S`_ and
`plat/common/aarch64/platform\_mp\_stack.S`_
Function : plat\_report\_exception()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : plat_report_exception()
::
Argument : unsigned int
Return : void
......@@ -848,23 +866,26 @@ exception is taken, for example the current exception level, the CPU security
state (secure/non-secure), the exception type, and so on. This function is
called in the following circumstances:
* In BL1, whenever an exception is taken.
* In BL2, whenever an exception is taken.
- In BL1, whenever an exception is taken.
- In BL2, whenever an exception is taken.
The default implementation doesn't do anything, to avoid making assumptions
about the way the platform displays its status information.
For AArch64, this function receives the exception type as its argument.
Possible values for exceptions types are listed in the
[include/common/bl_common.h] header file. Note that these constants are not
`include/common/bl\_common.h`_ header file. Note that these constants are not
related to any architectural exception code; they are just an ARM Trusted
Firmware convention.
For AArch32, this function receives the exception mode as its argument.
Possible values for exception modes are listed in the
[include/lib/aarch32/arch.h] header file.
`include/lib/aarch32/arch.h`_ header file.
### Function : plat_reset_handler()
Function : plat\_reset\_handler()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : void
......@@ -875,10 +896,13 @@ specific errata workarounds could also be implemented here. The api should
preserve the values of callee saved registers x19 to x29.
The default implementation doesn't do anything. If a platform needs to override
the default implementation, refer to the [Firmware Design] for general
the default implementation, refer to the `Firmware Design`_ for general
guidelines.
### Function : plat_disable_acp()
Function : plat\_disable\_acp()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : void
......@@ -890,7 +914,10 @@ it has restrictions for stack usage and it can use the registers x0 - x17 as
scratch registers. It should preserve the value in x18 register as it is used
by the caller to store the return address.
### Function : plat_error_handler()
Function : plat\_error\_handler()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : int
Return : void
......@@ -899,19 +926,22 @@ This API is called when the generic code encounters an error situation from
which it cannot continue. It allows the platform to perform error reporting or
recovery actions (for example, reset the system). This function must not return.
The parameter indicates the type of error using standard codes from `errno.h`.
The parameter indicates the type of error using standard codes from ``errno.h``.
Possible errors reported by the generic code are:
* `-EAUTH`: a certificate or image could not be authenticated (when Trusted
- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted
Board Boot is enabled)
* `-ENOENT`: the requested image or certificate could not be found or an IO
- ``-ENOENT``: the requested image or certificate could not be found or an IO
error was detected
* `-ENOMEM`: resources exhausted. Trusted Firmware does not use dynamic
- ``-ENOMEM``: resources exhausted. Trusted Firmware does not use dynamic
memory, so this error is usually an indication of an incorrect array size
The default implementation simply spins.
### Function : plat_panic_handler()
Function : plat\_panic\_handler()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : void
......@@ -924,17 +954,22 @@ environment is initialized.
Note: The address from where it was called is stored in x30 (Link Register).
The default implementation simply spins.
Function : plat\_get\_bl\_image\_load\_info()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : plat_get_bl_image_load_info()
::
Argument : void
Return : bl_load_info_t *
This function returns pointer to the list of images that the platform has
populated to load. This function is currently invoked in BL2 to load the
BL3xx images, when LOAD_IMAGE_V2 is enabled.
BL3xx images, when LOAD\_IMAGE\_V2 is enabled.
### Function : plat_get_next_bl_params()
Function : plat\_get\_next\_bl\_params()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : bl_params_t *
......@@ -942,14 +977,18 @@ BL3xx images, when LOAD_IMAGE_V2 is enabled.
This function returns a pointer to the shared memory that the platform has
kept aside to pass trusted firmware related information that next BL image
needs. This function is currently invoked in BL2 to pass this information to
the next BL image, when LOAD_IMAGE_V2 is enabled.
the next BL image, when LOAD\_IMAGE\_V2 is enabled.
Function : plat\_get\_stack\_protector\_canary()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
### Function : plat_get_stack_protector_canary()
Argument : void
Return : u_register_t
This function returns a random value that is used to initialize the canary used
when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable
when the stack protector is enabled with ENABLE\_STACK\_PROTECTOR. A predictable
value will weaken the protection as the attacker could easily write the right
value as part of the attack most of the time. Therefore, it should return a
true random number.
......@@ -958,64 +997,71 @@ Note: For the protection to be effective, the global data need to be placed at
a lower address than the stack bases. Failure to do so would allow an attacker
to overwrite the canary as part of the stack buffer overflow attack.
### Function : plat_flush_next_bl_params()
Function : plat\_flush\_next\_bl\_params()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : void
This function flushes to main memory all the image params that are passed to
next image. This function is currently invoked in BL2 to flush this information
to the next BL image, when LOAD_IMAGE_V2 is enabled.
to the next BL image, when LOAD\_IMAGE\_V2 is enabled.
3. Modifications specific to a Boot Loader stage
-------------------------------------------------
Modifications specific to a Boot Loader stage
---------------------------------------------
3.1 Boot Loader Stage 1 (BL1)
-----------------------------
Boot Loader Stage 1 (BL1)
-------------------------
BL1 implements the reset vector where execution starts from after a cold or
warm boot. For each CPU, BL1 is responsible for the following tasks:
1. Handling the reset as described in section 2.2
#. Handling the reset as described in section 2.2
2. In the case of a cold boot and the CPU being the primary CPU, ensuring that
#. In the case of a cold boot and the CPU being the primary CPU, ensuring that
only this CPU executes the remaining BL1 code, including loading and passing
control to the BL2 stage.
3. Identifying and starting the Firmware Update process (if required).
#. Identifying and starting the Firmware Update process (if required).
4. Loading the BL2 image from non-volatile storage into secure memory at the
address specified by the platform defined constant `BL2_BASE`.
#. Loading the BL2 image from non-volatile storage into secure memory at the
address specified by the platform defined constant ``BL2_BASE``.
5. Populating a `meminfo` structure with the following information in memory,
#. Populating a ``meminfo`` structure with the following information in memory,
accessible by BL2 immediately upon entry.
::
meminfo.total_base = Base address of secure RAM visible to BL2
meminfo.total_size = Size of secure RAM visible to BL2
meminfo.free_base = Base address of secure RAM available for
allocation to BL2
meminfo.free_size = Size of secure RAM available for allocation to BL2
BL1 places this `meminfo` structure at the beginning of the free memory
BL1 places this ``meminfo`` structure at the beginning of the free memory
available for its use. Since BL1 cannot allocate memory dynamically at the
moment, its free memory will be available for BL2's use as-is. However, this
means that BL2 must read the `meminfo` structure before it starts using its
means that BL2 must read the ``meminfo`` structure before it starts using its
free memory (this is discussed in Section 3.2).
In future releases of the ARM Trusted Firmware it will be possible for
the platform to decide where it wants to place the `meminfo` structure for
the platform to decide where it wants to place the ``meminfo`` structure for
BL2.
BL1 implements the `bl1_init_bl2_mem_layout()` function to populate the
BL2 `meminfo` structure. The platform may override this implementation, for
BL1 implements the ``bl1_init_bl2_mem_layout()`` function to populate the
BL2 ``meminfo`` structure. The platform may override this implementation, for
example if the platform wants to restrict the amount of memory visible to
BL2. Details of how to do this are given below.
The following functions need to be implemented by the platform port to enable
BL1 to perform the above tasks.
Function : bl1\_early\_platform\_setup() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl1_early_platform_setup() [mandatory]
::
Argument : void
Return : void
......@@ -1025,16 +1071,19 @@ by the primary CPU.
On ARM standard platforms, this function:
* Enables a secure instance of SP805 to act as the Trusted Watchdog.
- Enables a secure instance of SP805 to act as the Trusted Watchdog.
* Initializes a UART (PL011 console), which enables access to the `printf`
- Initializes a UART (PL011 console), which enables access to the ``printf``
family of functions in BL1.
* Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to
- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to
the CCI slave interface corresponding to the cluster that includes the
primary CPU.
### Function : bl1_plat_arch_setup() [mandatory]
Function : bl1\_plat\_arch\_setup() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : void
......@@ -1047,8 +1096,10 @@ In ARM standard platforms, this function enables the MMU.
This function helps fulfill requirement 2 above.
Function : bl1\_platform\_setup() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl1_platform_setup() [mandatory]
::
Argument : void
Return : void
......@@ -1062,17 +1113,21 @@ layer used to load the next bootloader image.
This function helps fulfill requirement 4 above.
Function : bl1\_plat\_sec\_mem\_layout() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl1_plat_sec_mem_layout() [mandatory]
::
Argument : void
Return : meminfo *
This function should only be called on the cold boot path. It executes with the
MMU and data caches enabled. The pointer returned by this function must point to
a `meminfo` structure containing the extents and availability of secure RAM for
a ``meminfo`` structure containing the extents and availability of secure RAM for
the BL1 stage.
::
meminfo.total_base = Base address of secure RAM visible to BL1
meminfo.total_size = Size of secure RAM visible to BL1
meminfo.free_base = Base address of secure RAM available for allocation
......@@ -1085,45 +1140,55 @@ its own use.
This function helps fulfill requirements 4 and 5 above.
Function : bl1\_init\_bl2\_mem\_layout() [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl1_init_bl2_mem_layout() [optional]
::
Argument : meminfo *, meminfo *
Return : void
BL1 needs to tell the next stage the amount of secure RAM available
for it to use. This information is populated in a `meminfo`
for it to use. This information is populated in a ``meminfo``
structure.
Depending upon where BL2 has been loaded in secure RAM (determined by
`BL2_BASE`), BL1 calculates the amount of free memory available for BL2 to use.
``BL2_BASE``), BL1 calculates the amount of free memory available for BL2 to use.
BL1 also ensures that its data sections resident in secure RAM are not visible
to BL2. An illustration of how this is done in ARM standard platforms is given
in the **Memory layout on ARM development platforms** section in the
[Firmware Design].
`Firmware Design`_.
Function : bl1\_plat\_prepare\_exit() [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl1_plat_prepare_exit() [optional]
::
Argument : entry_point_info_t *
Return : void
This function is called prior to exiting BL1 in response to the
`BL1_SMC_RUN_IMAGE` SMC request raised by BL2. It should be used to perform
``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform
platform specific clean up or bookkeeping operations before transferring
control to the next image. It receives the address of the `entry_point_info_t`
control to the next image. It receives the address of the ``entry_point_info_t``
structure passed from BL2. This function runs with MMU disabled.
### Function : bl1_plat_set_ep_info() [optional]
Function : bl1\_plat\_set\_ep\_info() [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : unsigned int image_id, entry_point_info_t *ep_info
Return : void
This function allows platforms to override `ep_info` for the given `image_id`.
This function allows platforms to override ``ep_info`` for the given ``image_id``.
The default implementation just returns.
### Function : bl1_plat_get_next_image_id() [optional]
Function : bl1\_plat\_get\_next\_image\_id() [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : unsigned int
......@@ -1131,28 +1196,34 @@ The default implementation just returns.
This and the following function must be overridden to enable the FWU feature.
BL1 calls this function after platform setup to identify the next image to be
loaded and executed. If the platform returns `BL2_IMAGE_ID` then BL1 proceeds
loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds
with the normal boot sequence, which loads and executes BL2. If the platform
returns a different image id, BL1 assumes that Firmware Update is required.
The default implementation always returns `BL2_IMAGE_ID`. The ARM development
The default implementation always returns ``BL2_IMAGE_ID``. The ARM development
platforms override this function to detect if firmware update is required, and
if so, return the first image in the firmware update process.
### Function : bl1_plat_get_image_desc() [optional]
Function : bl1\_plat\_get\_image\_desc() [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : unsigned int image_id
Return : image_desc_t *
BL1 calls this function to get the image descriptor information `image_desc_t`
for the provided `image_id` from the platform.
BL1 calls this function to get the image descriptor information ``image_desc_t``
for the provided ``image_id`` from the platform.
The default implementation always returns a common BL2 image descriptor. ARM
standard platforms return an image descriptor corresponding to BL2 or one of
the firmware update images defined in the Trusted Board Boot Requirements
specification.
### Function : bl1_plat_fwu_done() [optional]
Function : bl1\_plat\_fwu\_done() [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : unsigned int image_id, uintptr_t image_src,
unsigned int image_size
......@@ -1164,7 +1235,10 @@ example to initiate the normal boot flow.
The default implementation spins forever.
### Function : bl1_plat_mem_check() [mandatory]
Function : bl1\_plat\_mem\_check() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : uintptr_t mem_base, unsigned int mem_size,
unsigned int flags
......@@ -1172,12 +1246,12 @@ The default implementation spins forever.
BL1 calls this function while handling FWU related SMCs, more specifically when
copying or authenticating an image. Its responsibility is to ensure that the
region of memory identified by `mem_base` and `mem_size` is mapped in BL1, and
region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and
that this memory corresponds to either a secure or non-secure memory region as
indicated by the security state of the `flags` argument.
indicated by the security state of the ``flags`` argument.
This function can safely assume that the value resulting from the addition of
`mem_base` and `mem_size` fits into a `uintptr_t` type variable and does not
``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not
overflow.
This function must return 0 on success, a non-null error code otherwise.
......@@ -1185,82 +1259,85 @@ This function must return 0 on success, a non-null error code otherwise.
The default implementation of this function asserts therefore platforms must
override it when using the FWU feature.
3.2 Boot Loader Stage 2 (BL2)
-----------------------------
Boot Loader Stage 2 (BL2)
-------------------------
The BL2 stage is executed only by the primary CPU, which is determined in BL1
using the `platform_is_primary_cpu()` function. BL1 passed control to BL2 at
`BL2_BASE`. BL2 executes in Secure EL1 and is responsible for:
1. (Optional) Loading the SCP_BL2 binary image (if present) from platform
provided non-volatile storage. To load the SCP_BL2 image, BL2 makes use of
the `meminfo` returned by the `bl2_plat_get_scp_bl2_meminfo()` function.
The platform also defines the address in memory where SCP_BL2 is loaded
through the optional constant `SCP_BL2_BASE`. BL2 uses this information
to determine if there is enough memory to load the SCP_BL2 image.
Subsequent handling of the SCP_BL2 image is platform-specific and is
implemented in the `bl2_plat_handle_scp_bl2()` function.
If `SCP_BL2_BASE` is not defined then this step is not performed.
2. Loading the BL31 binary image into secure RAM from non-volatile storage. To
load the BL31 image, BL2 makes use of the `meminfo` structure passed to it
using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at
``BL2_BASE``. BL2 executes in Secure EL1 and is responsible for:
#. (Optional) Loading the SCP\_BL2 binary image (if present) from platform
provided non-volatile storage. To load the SCP\_BL2 image, BL2 makes use of
the ``meminfo`` returned by the ``bl2_plat_get_scp_bl2_meminfo()`` function.
The platform also defines the address in memory where SCP\_BL2 is loaded
through the optional constant ``SCP_BL2_BASE``. BL2 uses this information
to determine if there is enough memory to load the SCP\_BL2 image.
Subsequent handling of the SCP\_BL2 image is platform-specific and is
implemented in the ``bl2_plat_handle_scp_bl2()`` function.
If ``SCP_BL2_BASE`` is not defined then this step is not performed.
#. Loading the BL31 binary image into secure RAM from non-volatile storage. To
load the BL31 image, BL2 makes use of the ``meminfo`` structure passed to it
by BL1. This structure allows BL2 to calculate how much secure RAM is
available for its use. The platform also defines the address in secure RAM
where BL31 is loaded through the constant `BL31_BASE`. BL2 uses this
where BL31 is loaded through the constant ``BL31_BASE``. BL2 uses this
information to determine if there is enough memory to load the BL31 image.
3. (Optional) Loading the BL32 binary image (if present) from platform
#. (Optional) Loading the BL32 binary image (if present) from platform
provided non-volatile storage. To load the BL32 image, BL2 makes use of
the `meminfo` returned by the `bl2_plat_get_bl32_meminfo()` function.
the ``meminfo`` returned by the ``bl2_plat_get_bl32_meminfo()`` function.
The platform also defines the address in memory where BL32 is loaded
through the optional constant `BL32_BASE`. BL2 uses this information
through the optional constant ``BL32_BASE``. BL2 uses this information
to determine if there is enough memory to load the BL32 image.
If `BL32_BASE` is not defined then this and the next step is not performed.
If ``BL32_BASE`` is not defined then this and the next step is not performed.
4. (Optional) Arranging to pass control to the BL32 image (if present) that
has been pre-loaded at `BL32_BASE`. BL2 populates an `entry_point_info`
#. (Optional) Arranging to pass control to the BL32 image (if present) that
has been pre-loaded at ``BL32_BASE``. BL2 populates an ``entry_point_info``
structure in memory provided by the platform with information about how
BL31 should pass control to the BL32 image.
5. (Optional) Loading the normal world BL33 binary image (if not loaded by
#. (Optional) Loading the normal world BL33 binary image (if not loaded by
other means) into non-secure DRAM from platform storage and arranging for
BL31 to pass control to this image. This address is determined using the
`plat_get_ns_image_entrypoint()` function described below.
``plat_get_ns_image_entrypoint()`` function described below.
6. BL2 populates an `entry_point_info` structure in memory provided by the
#. BL2 populates an ``entry_point_info`` structure in memory provided by the
platform with information about how BL31 should pass control to the
other BL images.
The following functions must be implemented by the platform port to enable BL2
to perform the above tasks.
Function : bl2\_early\_platform\_setup() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl2_early_platform_setup() [mandatory]
::
Argument : meminfo *
Return : void
This function executes with the MMU and data caches disabled. It is only called
by the primary CPU. The arguments to this function is the address of the
`meminfo` structure populated by BL1.
``meminfo`` structure populated by BL1.
The platform may copy the contents of the `meminfo` structure into a private
The platform may copy the contents of the ``meminfo`` structure into a private
variable as the original memory may be subsequently overwritten by BL2. The
copied structure is made available to all BL2 code through the
`bl2_plat_sec_mem_layout()` function.
``bl2_plat_sec_mem_layout()`` function.
On ARM standard platforms, this function also:
* Initializes a UART (PL011 console), which enables access to the `printf`
- Initializes a UART (PL011 console), which enables access to the ``printf``
family of functions in BL2.
* Initializes the storage abstraction layer used to load further bootloader
images. It is necessary to do this early on platforms with a SCP_BL2 image,
since the later `bl2_platform_setup` must be done after SCP_BL2 is loaded.
- Initializes the storage abstraction layer used to load further bootloader
images. It is necessary to do this early on platforms with a SCP\_BL2 image,
since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded.
Function : bl2\_plat\_arch\_setup() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl2_plat_arch_setup() [mandatory]
::
Argument : void
Return : void
......@@ -1273,13 +1350,16 @@ that varies across platforms.
On ARM standard platforms, this function enables the MMU.
### Function : bl2_platform_setup() [mandatory]
Function : bl2\_platform\_setup() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : void
This function may execute with the MMU and data caches enabled if the platform
port does the necessary initialization in `bl2_plat_arch_setup()`. It is only
port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only
called by the primary CPU.
The purpose of this function is to perform any platform initialization
......@@ -1289,52 +1369,61 @@ In ARM standard platforms, this function performs security setup, including
configuration of the TrustZone controller to allow non-secure masters access
to most of DRAM. Part of DRAM is reserved for secure world use.
Function : bl2\_plat\_sec\_mem\_layout() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl2_plat_sec_mem_layout() [mandatory]
::
Argument : void
Return : meminfo *
This function should only be called on the cold boot path. It may execute with
the MMU and data caches enabled if the platform port does the necessary
initialization in `bl2_plat_arch_setup()`. It is only called by the primary CPU.
initialization in ``bl2_plat_arch_setup()``. It is only called by the primary CPU.
The purpose of this function is to return a pointer to a `meminfo` structure
The purpose of this function is to return a pointer to a ``meminfo`` structure
populated with the extents of secure RAM available for BL2 to use. See
`bl2_early_platform_setup()` above.
``bl2_early_platform_setup()`` above.
Following function is required only when LOAD\_IMAGE\_V2 is enabled.
Following function is required only when LOAD_IMAGE_V2 is enabled.
Function : bl2\_plat\_handle\_post\_image\_load() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl2_plat_handle_post_image_load() [mandatory]
::
Argument : unsigned int
Return : int
This function can be used by the platforms to update/use image information
for given `image_id`. This function is currently invoked in BL2 to handle
BL image specific information based on the `image_id` passed, when
LOAD_IMAGE_V2 is enabled.
for given ``image_id``. This function is currently invoked in BL2 to handle
BL image specific information based on the ``image_id`` passed, when
LOAD\_IMAGE\_V2 is enabled.
Following functions are required only when LOAD_IMAGE_V2 is disabled.
Following functions are required only when LOAD\_IMAGE\_V2 is disabled.
### Function : bl2_plat_get_scp_bl2_meminfo() [mandatory]
Function : bl2\_plat\_get\_scp\_bl2\_meminfo() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : meminfo *
Return : void
This function is used to get the memory limits where BL2 can load the
SCP_BL2 image. The meminfo provided by this is used by load_image() to
validate whether the SCP_BL2 image can be loaded within the given
SCP\_BL2 image. The meminfo provided by this is used by load\_image() to
validate whether the SCP\_BL2 image can be loaded within the given
memory from the given base.
Function : bl2\_plat\_handle\_scp\_bl2() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl2_plat_handle_scp_bl2() [mandatory]
::
Argument : image_info *
Return : int
This function is called after loading SCP_BL2 image and it is used to perform
This function is called after loading SCP\_BL2 image and it is used to perform
any platform-specific actions required to handle the SCP firmware. Typically it
transfers the image into SCP memory using a platform-specific protocol and waits
until SCP executes it and signals to the Application Processor (AP) for BL2
......@@ -1342,32 +1431,36 @@ execution to continue.
This function returns 0 on success, a negative error code otherwise.
Function : bl2\_plat\_get\_bl31\_params() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl2_plat_get_bl31_params() [mandatory]
::
Argument : void
Return : bl31_params *
BL2 platform code needs to return a pointer to a `bl31_params` structure it
will use for passing information to BL31. The `bl31_params` structure carries
BL2 platform code needs to return a pointer to a ``bl31_params`` structure it
will use for passing information to BL31. The ``bl31_params`` structure carries
the following information.
- Header describing the version information for interpreting the bl31_param
structure
- Information about executing the BL33 image in the `bl33_ep_info` field
- Information about executing the BL32 image in the `bl32_ep_info` field
- Information about the type and extents of BL31 image in the
`bl31_image_info` field
- Information about the type and extents of BL32 image in the
`bl32_image_info` field
- Information about the type and extents of BL33 image in the
`bl33_image_info` field
- Header describing the version information for interpreting the bl31\_param
structure
- Information about executing the BL33 image in the ``bl33_ep_info`` field
- Information about executing the BL32 image in the ``bl32_ep_info`` field
- Information about the type and extents of BL31 image in the
``bl31_image_info`` field
- Information about the type and extents of BL32 image in the
``bl32_image_info`` field
- Information about the type and extents of BL33 image in the
``bl33_image_info`` field
The memory pointed by this structure and its sub-structures should be
accessible from BL31 initialisation code. BL31 might choose to copy the
necessary content, or maintain the structures until BL33 is initialised.
Funtion : bl2\_plat\_get\_bl31\_ep\_info() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Funtion : bl2_plat_get_bl31_ep_info() [mandatory]
::
Argument : void
Return : entry_point_info *
......@@ -1376,11 +1469,13 @@ BL2 platform code returns a pointer which is used to populate the entry point
information for BL31 entry point. The location pointed by it should be
accessible from BL1 while processing the synchronous exception to run to BL31.
In ARM standard platforms this is allocated inside a bl2_to_bl31_params_mem
In ARM standard platforms this is allocated inside a bl2\_to\_bl31\_params\_mem
structure in BL2 memory.
Function : bl2\_plat\_set\_bl31\_ep\_info() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl2_plat_set_bl31_ep_info() [mandatory]
::
Argument : image_info *, entry_point_info *
Return : void
......@@ -1393,7 +1488,10 @@ When booting an EL3 payload instead, this function is called after populating
its entry point address and can be used for the same purpose for the payload
image. It receives a null pointer as its first argument in this case.
### Function : bl2_plat_set_bl32_ep_info() [mandatory]
Function : bl2\_plat\_set\_bl32\_ep\_info() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : image_info *, entry_point_info *
Return : void
......@@ -1402,8 +1500,10 @@ This function is called after loading BL32 image and it can be used to
overwrite the entry point set by loader and also set the security state
and SPSR which represents the entry point system state for BL32.
Function : bl2\_plat\_set\_bl33\_ep\_info() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl2_plat_set_bl33_ep_info() [mandatory]
::
Argument : image_info *, entry_point_info *
Return : void
......@@ -1416,42 +1516,53 @@ In the preloaded BL33 alternative boot flow, this function is called after
populating its entry point address. It is passed a null pointer as its first
argument in this case.
Function : bl2\_plat\_get\_bl32\_meminfo() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl2_plat_get_bl32_meminfo() [mandatory]
::
Argument : meminfo *
Return : void
This function is used to get the memory limits where BL2 can load the
BL32 image. The meminfo provided by this is used by load_image() to
BL32 image. The meminfo provided by this is used by load\_image() to
validate whether the BL32 image can be loaded with in the given
memory from the given base.
### Function : bl2_plat_get_bl33_meminfo() [mandatory]
Function : bl2\_plat\_get\_bl33\_meminfo() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : meminfo *
Return : void
This function is used to get the memory limits where BL2 can load the
BL33 image. The meminfo provided by this is used by load_image() to
BL33 image. The meminfo provided by this is used by load\_image() to
validate whether the BL33 image can be loaded with in the given
memory from the given base.
This function isn't needed if either `PRELOADED_BL33_BASE` or `EL3_PAYLOAD_BASE`
This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE``
build options are used.
### Function : bl2_plat_flush_bl31_params() [mandatory]
Function : bl2\_plat\_flush\_bl31\_params() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : void
Once BL2 has populated all the structures that needs to be read by BL1
and BL31 including the bl31_params structures and its sub-structures,
the bl31_ep_info structure and any platform specific data. It flushes
and BL31 including the bl31\_params structures and its sub-structures,
the bl31\_ep\_info structure and any platform specific data. It flushes
all these data to the main memory so that it is available when we jump to
later Bootloader stages with MMU off
### Function : plat_get_ns_image_entrypoint() [mandatory]
Function : plat\_get\_ns\_image\_entrypoint() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : uintptr_t
......@@ -1462,48 +1573,53 @@ entrypoint of that image, which BL31 uses to jump to it.
BL2 is responsible for loading the normal world BL33 image (e.g. UEFI).
This function isn't needed if either `PRELOADED_BL33_BASE` or `EL3_PAYLOAD_BASE`
This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE``
build options are used.
3.3 FWU Boot Loader Stage 2 (BL2U)
----------------------------------
FWU Boot Loader Stage 2 (BL2U)
------------------------------
The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU
process and is executed only by the primary CPU. BL1 passes control to BL2U at
`BL2U_BASE`. BL2U executes in Secure-EL1 and is responsible for:
``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for:
1. (Optional) Transfering the optional SCP_BL2U binary image from AP secure
memory to SCP RAM. BL2U uses the SCP_BL2U `image_info` passed by BL1.
`SCP_BL2U_BASE` defines the address in AP secure memory where SCP_BL2U
should be copied from. Subsequent handling of the SCP_BL2U image is
implemented by the platform specific `bl2u_plat_handle_scp_bl2u()` function.
If `SCP_BL2U_BASE` is not defined then this step is not performed.
#. (Optional) Transfering the optional SCP\_BL2U binary image from AP secure
memory to SCP RAM. BL2U uses the SCP\_BL2U ``image_info`` passed by BL1.
``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP\_BL2U
should be copied from. Subsequent handling of the SCP\_BL2U image is
implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function.
If ``SCP_BL2U_BASE`` is not defined then this step is not performed.
2. Any platform specific setup required to perform the FWU process. For
#. Any platform specific setup required to perform the FWU process. For
example, ARM standard platforms initialize the TZC controller so that the
normal world can access DDR memory.
The following functions must be implemented by the platform port to enable
BL2U to perform the tasks mentioned above.
### Function : bl2u_early_platform_setup() [mandatory]
Function : bl2u\_early\_platform\_setup() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : meminfo *mem_info, void *plat_info
Return : void
This function executes with the MMU and data caches disabled. It is only
called by the primary CPU. The arguments to this function is the address
of the `meminfo` structure and platform specific info provided by BL1.
of the ``meminfo`` structure and platform specific info provided by BL1.
The platform may copy the contents of the `mem_info` and `plat_info` into
The platform may copy the contents of the ``mem_info`` and ``plat_info`` into
private storage as the original memory may be subsequently overwritten by BL2U.
On ARM CSS platforms `plat_info` is interpreted as an `image_info_t` structure,
to extract SCP_BL2U image information, which is then copied into a private
On ARM CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure,
to extract SCP\_BL2U image information, which is then copied into a private
variable.
### Function : bl2u_plat_arch_setup() [mandatory]
Function : bl2u\_plat\_arch\_setup() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : void
......@@ -1515,13 +1631,16 @@ The purpose of this function is to perform any architectural initialization
that varies across platforms, for example enabling the MMU (since the memory
map differs across platforms).
### Function : bl2u_platform_setup() [mandatory]
Function : bl2u\_platform\_setup() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : void
This function may execute with the MMU and data caches enabled if the platform
port does the necessary initialization in `bl2u_plat_arch_setup()`. It is only
port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only
called by the primary CPU.
The purpose of this function is to perform any platform initialization
......@@ -1531,7 +1650,10 @@ In ARM standard platforms, this function performs security setup, including
configuration of the TrustZone controller to allow non-secure masters access
to most of DRAM. Part of DRAM is reserved for secure world use.
### Function : bl2u_plat_handle_scp_bl2u() [optional]
Function : bl2u\_plat\_handle\_scp\_bl2u() [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : int
......@@ -1542,35 +1664,34 @@ a platform-specific protocol and waits until SCP executes it and signals to the
Application Processor (AP) for BL2U execution to continue.
This function returns 0 on success, a negative error code otherwise.
This function is included if SCP_BL2U_BASE is defined.
This function is included if SCP\_BL2U\_BASE is defined.
3.4 Boot Loader Stage 3-1 (BL31)
---------------------------------
Boot Loader Stage 3-1 (BL31)
----------------------------
During cold boot, the BL31 stage is executed only by the primary CPU. This is
determined in BL1 using the `platform_is_primary_cpu()` function. BL1 passes
control to BL31 at `BL31_BASE`. During warm boot, BL31 is executed by all
determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes
control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all
CPUs. BL31 executes at EL3 and is responsible for:
1. Re-initializing all architectural and platform state. Although BL1 performs
#. Re-initializing all architectural and platform state. Although BL1 performs
some of this initialization, BL31 remains resident in EL3 and must ensure
that EL3 architectural and platform state is completely initialized. It
should make no assumptions about the system state when it receives control.
2. Passing control to a normal world BL image, pre-loaded at a platform-
specific address by BL2. BL31 uses the `entry_point_info` structure that BL2
#. Passing control to a normal world BL image, pre-loaded at a platform-
specific address by BL2. BL31 uses the ``entry_point_info`` structure that BL2
populated in memory to do this.
3. Providing runtime firmware services. Currently, BL31 only implements a
#. Providing runtime firmware services. Currently, BL31 only implements a
subset of the Power State Coordination Interface (PSCI) API as a runtime
service. See Section 3.3 below for details of porting the PSCI
implementation.
4. Optionally passing control to the BL32 image, pre-loaded at a platform-
#. Optionally passing control to the BL32 image, pre-loaded at a platform-
specific address by BL2. BL31 exports a set of apis that allow runtime
services to specify the security state in which the next image should be
executed and run the corresponding image. BL31 uses the `entry_point_info`
executed and run the corresponding image. BL31 uses the ``entry_point_info``
structure populated by BL2 to do this.
If BL31 is a reset vector, It also needs to handle the reset as specified in
......@@ -1579,8 +1700,10 @@ section 2.2 before the tasks described above.
The following functions must be implemented by the platform port to enable BL31
to perform the above tasks.
Function : bl31\_early\_platform\_setup() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl31_early_platform_setup() [mandatory]
::
Argument : bl31_params *, void *
Return : void
......@@ -1588,27 +1711,29 @@ to perform the above tasks.
This function executes with the MMU and data caches disabled. It is only called
by the primary CPU. The arguments to this function are:
* The address of the `bl31_params` structure populated by BL2.
* An opaque pointer that the platform may use as needed.
- The address of the ``bl31_params`` structure populated by BL2.
- An opaque pointer that the platform may use as needed.
The platform can copy the contents of the `bl31_params` structure and its
The platform can copy the contents of the ``bl31_params`` structure and its
sub-structures into private variables if the original memory may be
subsequently overwritten by BL31 and similarly the `void *` pointing
subsequently overwritten by BL31 and similarly the ``void *`` pointing
to the platform data also needs to be saved.
In ARM standard platforms, BL2 passes a pointer to a `bl31_params` structure
In ARM standard platforms, BL2 passes a pointer to a ``bl31_params`` structure
in BL2 memory. BL31 copies the information in this pointer to internal data
structures. It also performs the following:
* Initialize a UART (PL011 console), which enables access to the `printf`
- Initialize a UART (PL011 console), which enables access to the ``printf``
family of functions in BL31.
* Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the
- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the
CCI slave interface corresponding to the cluster that includes the primary
CPU.
Function : bl31\_plat\_arch\_setup() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl31_plat_arch_setup() [mandatory]
::
Argument : void
Return : void
......@@ -1621,14 +1746,16 @@ that varies across platforms.
On ARM standard platforms, this function enables the MMU.
Function : bl31\_platform\_setup() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl31_platform_setup() [mandatory]
::
Argument : void
Return : void
This function may execute with the MMU and data caches enabled if the platform
port does the necessary initialization in `bl31_plat_arch_setup()`. It is only
port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only
called by the primary CPU.
The purpose of this function is to complete platform initialization so that both
......@@ -1636,7 +1763,7 @@ BL31 runtime services and normal world software can function correctly.
On ARM standard platforms, this function does the following:
* Initialize the generic interrupt controller.
- Initialize the generic interrupt controller.
Depending on the GIC driver selected by the platform, the appropriate GICv2
or GICv3 initialization will be done, which mainly consists of:
......@@ -1651,145 +1778,160 @@ On ARM standard platforms, this function does the following:
- Configure all other interrupts as non-secure.
- Enable signaling of secure interrupts in the GIC distributor.
* Enable system-level implementation of the generic timer counter through the
- Enable system-level implementation of the generic timer counter through the
memory mapped interface.
* Grant access to the system counter timer module
- Grant access to the system counter timer module
* Initialize the power controller device.
- Initialize the power controller device.
In particular, initialise the locks that prevent concurrent accesses to the
power controller device.
Function : bl31\_plat\_runtime\_setup() [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl31_plat_runtime_setup() [optional]
::
Argument : void
Return : void
The purpose of this function is allow the platform to perform any BL31 runtime
setup just prior to BL31 exit during cold boot. The default weak
implementation of this function will invoke `console_uninit()` which will
implementation of this function will invoke ``console_uninit()`` which will
suppress any BL31 runtime logs.
In ARM Standard platforms, this function will initialize the BL31 runtime
console which will cause all further BL31 logs to be output to the
runtime console.
Function : bl31\_get\_next\_image\_info() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : bl31_get_next_image_info() [mandatory]
::
Argument : unsigned int
Return : entry_point_info *
This function may execute with the MMU and data caches enabled if the platform
port does the necessary initializations in `bl31_plat_arch_setup()`.
port does the necessary initializations in ``bl31_plat_arch_setup()``.
This function is called by `bl31_main()` to retrieve information provided by
This function is called by ``bl31_main()`` to retrieve information provided by
BL2 for the next image in the security state specified by the argument. BL31
uses this information to pass control to that image in the specified security
state. This function must return a pointer to the `entry_point_info` structure
(that was copied during `bl31_early_platform_setup()`) if the image exists. It
state. This function must return a pointer to the ``entry_point_info`` structure
(that was copied during ``bl31_early_platform_setup()``) if the image exists. It
should return NULL otherwise.
### Function : plat_get_syscnt_freq2() [mandatory]
Function : plat\_get\_syscnt\_freq2() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : unsigned int
This function is used by the architecture setup code to retrieve the counter
frequency for the CPU's generic timer. This value will be programmed into the
`CNTFRQ_EL0` register. In ARM standard platforms, it returns the base frequency
``CNTFRQ_EL0`` register. In ARM standard platforms, it returns the base frequency
of the system counter, which is retrieved from the first entry in the frequency
modes table.
#define : PLAT\_PERCPU\_BAKERY\_LOCK\_SIZE [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### #define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]
When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in
bytes) aligned to the cache line boundary that should be allocated per-cpu to
accommodate all the bakery locks.
When `USE_COHERENT_MEM = 0`, this constant defines the total memory (in
bytes) aligned to the cache line boundary that should be allocated per-cpu to
accommodate all the bakery locks.
If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker
calculates the size of the ``bakery_lock`` input section, aligns it to the
nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT``
and stores the result in a linker symbol. This constant prevents a platform
from relying on the linker and provide a more efficient mechanism for
accessing per-cpu bakery lock information.
If this constant is not defined when `USE_COHERENT_MEM = 0`, the linker
calculates the size of the `bakery_lock` input section, aligns it to the
nearest `CACHE_WRITEBACK_GRANULE`, multiplies it with `PLATFORM_CORE_COUNT`
and stores the result in a linker symbol. This constant prevents a platform
from relying on the linker and provide a more efficient mechanism for
accessing per-cpu bakery lock information.
If this constant is defined and its value is not equal to the value
calculated by the linker then a link time assertion is raised. A compile time
assertion is raised if the value of the constant is not aligned to the cache
line boundary.
If this constant is defined and its value is not equal to the value
calculated by the linker then a link time assertion is raised. A compile time
assertion is raised if the value of the constant is not aligned to the cache
line boundary.
3.5 Power State Coordination Interface (in BL31)
------------------------------------------------
Power State Coordination Interface (in BL31)
--------------------------------------------
The ARM Trusted Firmware's implementation of the PSCI API is based around the
concept of a _power domain_. A _power domain_ is a CPU or a logical group of
concept of a *power domain*. A *power domain* is a CPU or a logical group of
CPUs which share some state on which power management operations can be
performed as specified by [PSCI]. Each CPU in the system is assigned a cpu
index which is a unique number between `0` and `PLATFORM_CORE_COUNT - 1`.
The _power domains_ are arranged in a hierarchical tree structure and
each _power domain_ can be identified in a system by the cpu index of any CPU
that is part of that domain and a _power domain level_. A processing element
(for example, a CPU) is at level 0. If the _power domain_ node above a CPU is
performed as specified by `PSCI`_. Each CPU in the system is assigned a cpu
index which is a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``.
The *power domains* are arranged in a hierarchical tree structure and
each *power domain* can be identified in a system by the cpu index of any CPU
that is part of that domain and a *power domain level*. A processing element
(for example, a CPU) is at level 0. If the *power domain* node above a CPU is
a logical grouping of CPUs that share some state, then level 1 is that group
of CPUs (for example, a cluster), and level 2 is a group of clusters
(for example, the system). More details on the power domain topology and its
organization can be found in [Power Domain Topology Design].
organization can be found in `Power Domain Topology Design`_.
BL31's platform initialization code exports a pointer to the platform-specific
power management operations required for the PSCI implementation to function
correctly. This information is populated in the `plat_psci_ops` structure. The
PSCI implementation calls members of the `plat_psci_ops` structure for performing
correctly. This information is populated in the ``plat_psci_ops`` structure. The
PSCI implementation calls members of the ``plat_psci_ops`` structure for performing
power management operations on the power domains. For example, the target
CPU is specified by its `MPIDR` in a PSCI `CPU_ON` call. The `pwr_domain_on()`
CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()``
handler (if present) is called for the CPU power domain.
The `power-state` parameter of a PSCI `CPU_SUSPEND` call can be used to
The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to
describe composite power states specific to a platform. The PSCI implementation
defines a generic representation of the power-state parameter viz which is an
array of local power states where each index corresponds to a power domain
level. Each entry contains the local power state the power domain at that power
level could enter. It depends on the `validate_power_state()` handler to
level could enter. It depends on the ``validate_power_state()`` handler to
convert the power-state parameter (possibly encoding a composite power state)
passed in a PSCI `CPU_SUSPEND` call to this representation.
passed in a PSCI ``CPU_SUSPEND`` call to this representation.
The following functions form part of platform port of PSCI functionality.
Function : plat\_psci\_stat\_accounting\_start() [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : plat_psci_stat_accounting_start() [optional]
::
Argument : const psci_power_state_t *
Return : void
This is an optional hook that platforms can implement for residency statistics
accounting before entering a low power state. The `pwr_domain_state` field of
`state_info` (first argument) can be inspected if stat accounting is done
accounting before entering a low power state. The ``pwr_domain_state`` field of
``state_info`` (first argument) can be inspected if stat accounting is done
differently at CPU level versus higher levels. As an example, if the element at
index 0 (CPU power level) in the `pwr_domain_state` array indicates a power down
index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
state, special hardware logic may be programmed in order to keep track of the
residency statistics. For higher levels (array indices > 0), the residency
statistics could be tracked in software using PMF. If `ENABLE_PMF` is set, the
statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
default implementation will use PMF to capture timestamps.
### Function : plat_psci_stat_accounting_stop() [optional]
Function : plat\_psci\_stat\_accounting\_stop() [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : const psci_power_state_t *
Return : void
This is an optional hook that platforms can implement for residency statistics
accounting after exiting from a low power state. The `pwr_domain_state` field
of `state_info` (first argument) can be inspected if stat accounting is done
accounting after exiting from a low power state. The ``pwr_domain_state`` field
of ``state_info`` (first argument) can be inspected if stat accounting is done
differently at CPU level versus higher levels. As an example, if the element at
index 0 (CPU power level) in the `pwr_domain_state` array indicates a power down
index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
state, special hardware logic may be programmed in order to keep track of the
residency statistics. For higher levels (array indices > 0), the residency
statistics could be tracked in software using PMF. If `ENABLE_PMF` is set, the
statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
default implementation will use PMF to capture timestamps.
### Function : plat_psci_stat_get_residency() [optional]
Function : plat\_psci\_stat\_get\_residency() [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : unsigned int, const psci_power_state_t *, int
Return : u_register_t
......@@ -1799,24 +1941,27 @@ state and provides the time spent resident in that low power state by the power
domain at a particular power domain level. When a CPU wakes up from suspend,
all its parent power domain levels are also woken up. The generic PSCI code
invokes this function for each parent power domain that is resumed and it
identified by the `lvl` (first argument) parameter. The `state_info` (second
identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second
argument) describes the low power state that the power domain has resumed from.
The current CPU is the first CPU in the power domain to resume from the low
power state and the `last_cpu_idx` (third parameter) is the index of the last
power state and the ``last_cpu_idx`` (third parameter) is the index of the last
CPU in the power domain to suspend and may be needed to calculate the residency
for that power domain.
### Function : plat_get_target_pwr_state() [optional]
Function : plat\_get\_target\_pwr\_state() [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : unsigned int, const plat_local_state_t *, unsigned int
Return : plat_local_state_t
The PSCI generic code uses this function to let the platform participate in
state coordination during a power management operation. The function is passed
a pointer to an array of platform specific local power state `states` (second
a pointer to an array of platform specific local power state ``states`` (second
argument) which contains the requested power state for each CPU at a particular
power domain level `lvl` (first argument) within the power domain. The function
is expected to traverse this array of upto `ncpus` (third argument) and return
power domain level ``lvl`` (first argument) within the power domain. The function
is expected to traverse this array of upto ``ncpus`` (third argument) and return
a coordinated target power state by the comparing all the requested power
states. The target power state should not be deeper than any of the requested
power states.
......@@ -1828,72 +1973,79 @@ then X represents a shallower power state than Y. As a result, the
coordinated target local power state for a power domain will be the minimum
of the requested local power state values.
Function : plat\_get\_power\_domain\_tree\_desc() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : plat_get_power_domain_tree_desc() [mandatory]
::
Argument : void
Return : const unsigned char *
This function returns a pointer to the byte array containing the power domain
topology tree description. The format and method to construct this array are
described in [Power Domain Topology Design]. The BL31 PSCI initilization code
described in `Power Domain Topology Design`_. The BL31 PSCI initilization code
requires this array to be described by the platform, either statically or
dynamically, to initialize the power domain topology tree. In case the array
is populated dynamically, then plat_core_pos_by_mpidr() and
plat_my_core_pos() should also be implemented suitably so that the topology
is populated dynamically, then plat\_core\_pos\_by\_mpidr() and
plat\_my\_core\_pos() should also be implemented suitably so that the topology
tree description matches the CPU indices returned by these APIs. These APIs
together form the platform interface for the PSCI topology framework.
Function : plat\_setup\_psci\_ops() [mandatory]
-----------------------------------------------
## Function : plat_setup_psci_ops() [mandatory]
::
Argument : uintptr_t, const plat_psci_ops **
Return : int
This function may execute with the MMU and data caches enabled if the platform
port does the necessary initializations in `bl31_plat_arch_setup()`. It is only
port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
called by the primary CPU.
This function is called by PSCI initialization code. Its purpose is to let
the platform layer know about the warm boot entrypoint through the
`sec_entrypoint` (first argument) and to export handler routines for
``sec_entrypoint`` (first argument) and to export handler routines for
platform-specific psci power management actions by populating the passed
pointer with a pointer to BL31's private `plat_psci_ops` structure.
pointer with a pointer to BL31's private ``plat_psci_ops`` structure.
A description of each member of this structure is given below. Please refer to
the ARM FVP specific implementation of these handlers in
[plat/arm/board/fvp/fvp_pm.c] as an example. For each PSCI function that the
`plat/arm/board/fvp/fvp\_pm.c`_ as an example. For each PSCI function that the
platform wants to support, the associated operation or operations in this
structure must be provided and implemented (Refer section 4 of
[Firmware Design] for the PSCI API supported in Trusted Firmware). To disable
`Firmware Design`_ for the PSCI API supported in Trusted Firmware). To disable
a PSCI function in a platform port, the operation should be removed from this
structure instead of providing an empty implementation.
#### plat_psci_ops.cpu_standby()
plat\_psci\_ops.cpu\_standby()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Perform the platform-specific actions to enter the standby state for a cpu
indicated by the passed argument. This provides a fast path for CPU standby
wherein overheads of PSCI state management and lock acquistion is avoided.
For this handler to be invoked by the PSCI `CPU_SUSPEND` API implementation,
the suspend state type specified in the `power-state` parameter should be
For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation,
the suspend state type specified in the ``power-state`` parameter should be
STANDBY and the target power domain level specified should be the CPU. The
handler should put the CPU into a low power retention state (usually by
issuing a wfi instruction) and ensure that it can be woken up from that
state by a normal interrupt. The generic code expects the handler to succeed.
#### plat_psci_ops.pwr_domain_on()
plat\_psci\_ops.pwr\_domain\_on()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Perform the platform specific actions to power on a CPU, specified
by the `MPIDR` (first argument). The generic code expects the platform to
return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure.
by the ``MPIDR`` (first argument). The generic code expects the platform to
return PSCI\_E\_SUCCESS on success or PSCI\_E\_INTERN\_FAIL for any failure.
#### plat_psci_ops.pwr_domain_off()
plat\_psci\_ops.pwr\_domain\_off()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Perform the platform specific actions to prepare to power off the calling CPU
and its higher parent power domain levels as indicated by the `target_state`
(first argument). It is called by the PSCI `CPU_OFF` API implementation.
and its higher parent power domain levels as indicated by the ``target_state``
(first argument). It is called by the PSCI ``CPU_OFF`` API implementation.
The `target_state` encodes the platform coordinated target local power states
The ``target_state`` encodes the platform coordinated target local power states
for the CPU power domain and its parent power domain levels. The handler
needs to perform power management operation corresponding to the local state
at each power level.
......@@ -1903,15 +2055,16 @@ power down state where as it could be either power down, retention or run state
for the higher power domain levels depending on the result of state
coordination. The generic code expects the handler to succeed.
#### plat_psci_ops.pwr_domain_suspend()
plat\_psci\_ops.pwr\_domain\_suspend()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Perform the platform specific actions to prepare to suspend the calling
CPU and its higher parent power domain levels as indicated by the
`target_state` (first argument). It is called by the PSCI `CPU_SUSPEND`
``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND``
API implementation.
The `target_state` has a similar meaning as described in
the `pwr_domain_off()` operation. It encodes the platform coordinated
The ``target_state`` has a similar meaning as described in
the ``pwr_domain_off()`` operation. It encodes the platform coordinated
target local power states for the CPU power domain and its parent
power domain levels. The handler needs to perform power management operation
corresponding to the local state at each power level. The generic code
......@@ -1919,152 +2072,167 @@ expects the handler to succeed.
The difference between turning a power domain off versus suspending it
is that in the former case, the power domain is expected to re-initialize
its state when it is next powered on (see `pwr_domain_on_finish()`). In the
its state when it is next powered on (see ``pwr_domain_on_finish()``). In the
latter case, the power domain is expected to save enough state so that it can
resume execution by restoring this state when its powered on (see
`pwr_domain_suspend_finish()`).
``pwr_domain_suspend_finish()``).
#### plat_psci_ops.pwr_domain_pwr_down_wfi()
plat\_psci\_ops.pwr\_domain\_pwr\_down\_wfi()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This is an optional function and, if implemented, is expected to perform
platform specific actions including the `wfi` invocation which allows the
platform specific actions including the ``wfi`` invocation which allows the
CPU to powerdown. Since this function is invoked outside the PSCI locks,
the actions performed in this hook must be local to the CPU or the platform
must ensure that races between multiple CPUs cannot occur.
The `target_state` has a similar meaning as described in the `pwr_domain_off()`
The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()``
operation and it encodes the platform coordinated target local power states for
the CPU power domain and its parent power domain levels. This function must
not return back to the caller.
If this function is not implemented by the platform, PSCI generic
implementation invokes `psci_power_down_wfi()` for power down.
implementation invokes ``psci_power_down_wfi()`` for power down.
#### plat_psci_ops.pwr_domain_on_finish()
plat\_psci\_ops.pwr\_domain\_on\_finish()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This function is called by the PSCI implementation after the calling CPU is
powered on and released from reset in response to an earlier PSCI `CPU_ON` call.
powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
It performs the platform-specific setup required to initialize enough state for
this CPU to enter the normal world and also provide secure runtime firmware
services.
The `target_state` (first argument) is the prior state of the power domains
The ``target_state`` (first argument) is the prior state of the power domains
immediately before the CPU was turned on. It indicates which power domains
above the CPU might require initialization due to having previously been in
low power states. The generic code expects the handler to succeed.
#### plat_psci_ops.pwr_domain_suspend_finish()
plat\_psci\_ops.pwr\_domain\_suspend\_finish()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This function is called by the PSCI implementation after the calling CPU is
powered on and released from reset in response to an asynchronous wakeup
event, for example a timer interrupt that was programmed by the CPU during the
`CPU_SUSPEND` call or `SYSTEM_SUSPEND` call. It performs the platform-specific
``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific
setup required to restore the saved state for this CPU to resume execution
in the normal world and also provide secure runtime firmware services.
The `target_state` (first argument) has a similar meaning as described in
the `pwr_domain_on_finish()` operation. The generic code expects the platform
The ``target_state`` (first argument) has a similar meaning as described in
the ``pwr_domain_on_finish()`` operation. The generic code expects the platform
to succeed.
#### plat_psci_ops.system_off()
plat\_psci\_ops.system\_off()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This function is called by PSCI implementation in response to a `SYSTEM_OFF`
This function is called by PSCI implementation in response to a ``SYSTEM_OFF``
call. It performs the platform-specific system poweroff sequence after
notifying the Secure Payload Dispatcher.
#### plat_psci_ops.system_reset()
plat\_psci\_ops.system\_reset()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This function is called by PSCI implementation in response to a `SYSTEM_RESET`
This function is called by PSCI implementation in response to a ``SYSTEM_RESET``
call. It performs the platform-specific system reset sequence after
notifying the Secure Payload Dispatcher.
#### plat_psci_ops.validate_power_state()
plat\_psci\_ops.validate\_power\_state()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This function is called by the PSCI implementation during the `CPU_SUSPEND`
call to validate the `power_state` parameter of the PSCI API and if valid,
populate it in `req_state` (second argument) array as power domain level
specific local states. If the `power_state` is invalid, the platform must
return PSCI_E_INVALID_PARAMS as error, which is propagated back to the
This function is called by the PSCI implementation during the ``CPU_SUSPEND``
call to validate the ``power_state`` parameter of the PSCI API and if valid,
populate it in ``req_state`` (second argument) array as power domain level
specific local states. If the ``power_state`` is invalid, the platform must
return PSCI\_E\_INVALID\_PARAMS as error, which is propagated back to the
normal world PSCI client.
#### plat_psci_ops.validate_ns_entrypoint()
plat\_psci\_ops.validate\_ns\_entrypoint()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This function is called by the PSCI implementation during the `CPU_SUSPEND`,
`SYSTEM_SUSPEND` and `CPU_ON` calls to validate the non-secure `entry_point`
parameter passed by the normal world. If the `entry_point` is invalid,
the platform must return PSCI_E_INVALID_ADDRESS as error, which is
This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point``
parameter passed by the normal world. If the ``entry_point`` is invalid,
the platform must return PSCI\_E\_INVALID\_ADDRESS as error, which is
propagated back to the normal world PSCI client.
#### plat_psci_ops.get_sys_suspend_power_state()
plat\_psci\_ops.get\_sys\_suspend\_power\_state()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This function is called by the PSCI implementation during the `SYSTEM_SUSPEND`
call to get the `req_state` parameter from platform which encodes the power
This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
call to get the ``req_state`` parameter from platform which encodes the power
domain level specific local states to suspend to system affinity level. The
`req_state` will be utilized to do the PSCI state coordination and
`pwr_domain_suspend()` will be invoked with the coordinated target state to
``req_state`` will be utilized to do the PSCI state coordination and
``pwr_domain_suspend()`` will be invoked with the coordinated target state to
enter system suspend.
#### plat_psci_ops.get_pwr_lvl_state_idx()
plat\_psci\_ops.get\_pwr\_lvl\_state\_idx()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This is an optional function and, if implemented, is invoked by the PSCI
implementation to convert the `local_state` (first argument) at a specified
`pwr_lvl` (second argument) to an index between 0 and
`PLAT_MAX_PWR_LVL_STATES` - 1. This function is only needed if the platform
implementation to convert the ``local_state`` (first argument) at a specified
``pwr_lvl`` (second argument) to an index between 0 and
``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform
supports more than two local power states at each power domain level, that is
`PLAT_MAX_PWR_LVL_STATES` is greater than 2, and needs to account for these
``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these
local power states.
#### plat_psci_ops.translate_power_state_by_mpidr()
plat\_psci\_ops.translate\_power\_state\_by\_mpidr()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This is an optional function and, if implemented, verifies the `power_state`
This is an optional function and, if implemented, verifies the ``power_state``
(second argument) parameter of the PSCI API corresponding to a target power
domain. The target power domain is identified by using both `MPIDR` (first
argument) and the power domain level encoded in `power_state`. The power domain
level specific local states are to be extracted from `power_state` and be
populated in the `output_state` (third argument) array. The functionality
is similar to the `validate_power_state` function described above and is
envisaged to be used in case the validity of `power_state` depend on the
targeted power domain. If the `power_state` is invalid for the targeted power
domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this
domain. The target power domain is identified by using both ``MPIDR`` (first
argument) and the power domain level encoded in ``power_state``. The power domain
level specific local states are to be extracted from ``power_state`` and be
populated in the ``output_state`` (third argument) array. The functionality
is similar to the ``validate_power_state`` function described above and is
envisaged to be used in case the validity of ``power_state`` depend on the
targeted power domain. If the ``power_state`` is invalid for the targeted power
domain, the platform must return PSCI\_E\_INVALID\_PARAMS as error. If this
function is not implemented, then the generic implementation relies on
`validate_power_state` function to translate the `power_state`.
``validate_power_state`` function to translate the ``power_state``.
This function can also be used in case the platform wants to support local
power state encoding for `power_state` parameter of PSCI_STAT_COUNT/RESIDENCY
APIs as described in Section 5.18 of [PSCI].
power state encoding for ``power_state`` parameter of PSCI\_STAT\_COUNT/RESIDENCY
APIs as described in Section 5.18 of `PSCI`_.
#### plat_psci_ops.get_node_hw_state()
plat\_psci\_ops.get\_node\_hw\_state()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This is an optional function. If implemented this function is intended to return
the power state of a node (identified by the first parameter, the `MPIDR`) in
the power domain topology (identified by the second parameter, `power_level`),
the power state of a node (identified by the first parameter, the ``MPIDR``) in
the power domain topology (identified by the second parameter, ``power_level``),
as retrieved from a power controller or equivalent component on the platform.
Upon successful completion, the implementation must map and return the final
status among `HW_ON`, `HW_OFF` or `HW_STANDBY`. Upon encountering failures, it
must return either `PSCI_E_INVALID_PARAMS` or `PSCI_E_NOT_SUPPORTED` as
status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it
must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as
appropriate.
Implementations are not expected to handle `power_levels` greater than
`PLAT_MAX_PWR_LVL`.
Implementations are not expected to handle ``power_levels`` greater than
``PLAT_MAX_PWR_LVL``.
Interrupt Management framework (in BL31)
----------------------------------------
3.6 Interrupt Management framework (in BL31)
----------------------------------------------
BL31 implements an Interrupt Management Framework (IMF) to manage interrupts
generated in either security state and targeted to EL1 or EL2 in the non-secure
state or EL3/S-EL1 in the secure state. The design of this framework is
described in the [IMF Design Guide]
described in the `IMF Design Guide`_
A platform should export the following APIs to support the IMF. The following
text briefly describes each api and its implementation in ARM standard
platforms. The API implementation depends upon the type of interrupt controller
present in the platform. ARM standard platform layer supports both [ARM Generic
Interrupt Controller version 2.0 (GICv2)][ARM GIC Architecture Specification 2.0]
and [3.0 (GICv3)][ARM GIC Architecture Specification 3.0]. Juno builds the ARM
present in the platform. ARM standard platform layer supports both
`ARM Generic Interrupt Controller version 2.0 (GICv2)`_
and `3.0 (GICv3)`_. Juno builds the ARM
Standard layer to use GICv2 and the FVP can be configured to use either GICv2 or
GICv3 depending on the build flag `FVP_USE_GIC_DRIVER` (See FVP platform
specific build options in [User Guide] for more details).
GICv3 depending on the build flag ``FVP_USE_GIC_DRIVER`` (See FVP platform
specific build options in `User Guide`_ for more details).
### Function : plat_interrupt_type_to_line() [mandatory]
Function : plat\_interrupt\_type\_to\_line() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : uint32_t, uint32_t
Return : uint32_t
......@@ -2076,10 +2244,10 @@ either security state. The IMF uses this API to determine which interrupt line
the platform IC uses to signal each type of interrupt supported by the framework
from a given security state. This API must be invoked at EL3.
The first parameter will be one of the `INTR_TYPE_*` values (see [IMF Design
Guide]) indicating the target type of the interrupt, the second parameter is the
The first parameter will be one of the ``INTR_TYPE_*`` values (see
`IMF Design Guide`_) indicating the target type of the interrupt, the second parameter is the
security state of the originating execution context. The return result is the
bit position in the `SCR_EL3` register of the respective interrupt trap: IRQ=1,
bit position in the ``SCR_EL3`` register of the respective interrupt trap: IRQ=1,
FIQ=2.
In the case of ARM standard platforms using GICv2, S-EL1 interrupts are
......@@ -2089,85 +2257,93 @@ state.
In the case of ARM standard platforms using GICv3, the interrupt line to be
configured depends on the security state of the execution context when the
interrupt is signalled and are as follows:
* The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in
- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in
NS-EL0/1/2 context.
* The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ
- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ
in the NS-EL0/1/2 context.
* The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2
- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2
context.
Function : plat\_ic\_get\_pending\_interrupt\_type() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : plat_ic_get_pending_interrupt_type() [mandatory]
::
Argument : void
Return : uint32_t
This API returns the type of the highest priority pending interrupt at the
platform IC. The IMF uses the interrupt type to retrieve the corresponding
handler function. `INTR_TYPE_INVAL` is returned when there is no interrupt
pending. The valid interrupt types that can be returned are `INTR_TYPE_EL3`,
`INTR_TYPE_S_EL1` and `INTR_TYPE_NS`. This API must be invoked at EL3.
handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt
pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``,
``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3.
In the case of ARM standard platforms using GICv2, the _Highest Priority
Pending Interrupt Register_ (`GICC_HPPIR`) is read to determine the id of
In the case of ARM standard platforms using GICv2, the *Highest Priority
Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of
the pending interrupt. The type of interrupt depends upon the id value as
follows.
1. id < 1022 is reported as a S-EL1 interrupt
2. id = 1022 is reported as a Non-secure interrupt.
3. id = 1023 is reported as an invalid interrupt type.
#. id < 1022 is reported as a S-EL1 interrupt
#. id = 1022 is reported as a Non-secure interrupt.
#. id = 1023 is reported as an invalid interrupt type.
In the case of ARM standard platforms using GICv3, the system register
`ICC_HPPIR0_EL1`, _Highest Priority Pending group 0 Interrupt Register_,
``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*,
is read to determine the id of the pending interrupt. The type of interrupt
depends upon the id value as follows.
1. id = `PENDING_G1S_INTID` (1020) is reported as a S-EL1 interrupt
2. id = `PENDING_G1NS_INTID` (1021) is reported as a Non-secure interrupt.
3. id = `GIC_SPURIOUS_INTERRUPT` (1023) is reported as an invalid interrupt type.
4. All other interrupt id's are reported as EL3 interrupt.
#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt
#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt.
#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type.
#. All other interrupt id's are reported as EL3 interrupt.
Function : plat\_ic\_get\_pending\_interrupt\_id() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : plat_ic_get_pending_interrupt_id() [mandatory]
::
Argument : void
Return : uint32_t
This API returns the id of the highest priority pending interrupt at the
platform IC. `INTR_ID_UNAVAILABLE` is returned when there is no interrupt
platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt
pending.
In the case of ARM standard platforms using GICv2, the _Highest Priority
Pending Interrupt Register_ (`GICC_HPPIR`) is read to determine the id of the
In the case of ARM standard platforms using GICv2, the *Highest Priority
Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the
pending interrupt. The id that is returned by API depends upon the value of
the id read from the interrupt controller as follows.
1. id < 1022. id is returned as is.
2. id = 1022. The _Aliased Highest Priority Pending Interrupt Register_
(`GICC_AHPPIR`) is read to determine the id of the non-secure interrupt.
#. id < 1022. id is returned as is.
#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register*
(``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt.
This id is returned by the API.
3. id = 1023. `INTR_ID_UNAVAILABLE` is returned.
#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned.
In the case of ARM standard platforms using GICv3, if the API is invoked from
EL3, the system register `ICC_HPPIR0_EL1`, _Highest Priority Pending Interrupt
group 0 Register_, is read to determine the id of the pending interrupt. The id
EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt
group 0 Register*, is read to determine the id of the pending interrupt. The id
that is returned by API depends upon the value of the id read from the
interrupt controller as follows.
1. id < `PENDING_G1S_INTID` (1020). id is returned as is.
2. id = `PENDING_G1S_INTID` (1020) or `PENDING_G1NS_INTID` (1021). The system
register `ICC_HPPIR1_EL1`, _Highest Priority Pending Interrupt group 1
Register_ is read to determine the id of the group 1 interrupt. This id
#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is.
#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system
register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1
Register* is read to determine the id of the group 1 interrupt. This id
is returned by the API as long as it is a valid interrupt id
3. If the id is any of the special interrupt identifiers,
`INTR_ID_UNAVAILABLE` is returned.
#. If the id is any of the special interrupt identifiers,
``INTR_ID_UNAVAILABLE`` is returned.
When the API invoked from S-EL1 for GICv3 systems, the id read from system
register `ICC_HPPIR1_EL1`, _Highest Priority Pending group 1 Interrupt
Register_, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else
`INTR_ID_UNAVAILABLE` is returned.
register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt
Register*, is returned if is not equal to GIC\_SPURIOUS\_INTERRUPT (1023) else
``INTR_ID_UNAVAILABLE`` is returned.
### Function : plat_ic_acknowledge_interrupt() [mandatory]
Function : plat\_ic\_acknowledge\_interrupt() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : uint32_t
......@@ -2176,25 +2352,27 @@ This API is used by the CPU to indicate to the platform IC that processing of
the highest pending interrupt has begun. It should return the id of the
interrupt which is being processed.
This function in ARM standard platforms using GICv2, reads the _Interrupt
Acknowledge Register_ (`GICC_IAR`). This changes the state of the highest
This function in ARM standard platforms using GICv2, reads the *Interrupt
Acknowledge Register* (``GICC_IAR``). This changes the state of the highest
priority pending interrupt from pending to active in the interrupt controller.
It returns the value read from the `GICC_IAR`. This value is the id of the
It returns the value read from the ``GICC_IAR``. This value is the id of the
interrupt whose state has been changed.
In the case of ARM standard platforms using GICv3, if the API is invoked
from EL3, the function reads the system register `ICC_IAR0_EL1`, _Interrupt
Acknowledge Register group 0_. If the API is invoked from S-EL1, the function
reads the system register `ICC_IAR1_EL1`, _Interrupt Acknowledge Register
group 1_. The read changes the state of the highest pending interrupt from
from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt
Acknowledge Register group 0*. If the API is invoked from S-EL1, the function
reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register
group 1*. The read changes the state of the highest pending interrupt from
pending to active in the interrupt controller. The value read is returned
and is the id of the interrupt whose state has been changed.
The TSP uses this API to start processing of the secure physical timer
interrupt.
Function : plat\_ic\_end\_of\_interrupt() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : plat_ic_end_of_interrupt() [mandatory]
::
Argument : uint32_t
Return : void
......@@ -2202,10 +2380,10 @@ interrupt.
This API is used by the CPU to indicate to the platform IC that processing of
the interrupt corresponding to the id (passed as the parameter) has
finished. The id should be the same as the id returned by the
`plat_ic_acknowledge_interrupt()` API.
``plat_ic_acknowledge_interrupt()`` API.
ARM standard platforms write the id to the _End of Interrupt Register_
(`GICC_EOIR`) in case of GICv2, and to `ICC_EOIR0_EL1` or `ICC_EOIR1_EL1`
ARM standard platforms write the id to the *End of Interrupt Register*
(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1``
system register in case of GICv3 depending on where the API is invoked from,
EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt
controller.
......@@ -2213,31 +2391,33 @@ controller.
The TSP uses this API to finish processing of the secure physical timer
interrupt.
Function : plat\_ic\_get\_interrupt\_type() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Function : plat_ic_get_interrupt_type() [mandatory]
::
Argument : uint32_t
Return : uint32_t
This API returns the type of the interrupt id passed as the parameter.
`INTR_TYPE_INVAL` is returned if the id is invalid. If the id is valid, a valid
interrupt type (one of `INTR_TYPE_EL3`, `INTR_TYPE_S_EL1` and `INTR_TYPE_NS`) is
``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid
interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is
returned depending upon how the interrupt has been configured by the platform
IC. This API must be invoked at EL3.
ARM standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts
and Non-secure interrupts as Group1 interrupts. It reads the group value
corresponding to the interrupt id from the relevant _Interrupt Group Register_
(`GICD_IGROUPRn`). It uses the group value to determine the type of interrupt.
corresponding to the interrupt id from the relevant *Interrupt Group Register*
(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt.
In the case of ARM standard platforms using GICv3, both the _Interrupt Group
Register_ (`GICD_IGROUPRn`) and _Interrupt Group Modifier Register_
(`GICD_IGRPMODRn`) is read to figure out whether the interrupt is configured
In the case of ARM standard platforms using GICv3, both the *Interrupt Group
Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register*
(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured
as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt.
Crash Reporting mechanism (in BL31)
-----------------------------------
3.7 Crash Reporting mechanism (in BL31)
----------------------------------------------
BL31 implements a crash reporting mechanism which prints the various registers
of the CPU to enable quick crash analysis and debugging. It requires that a
console is designated as the crash console by the platform which will be used to
......@@ -2247,7 +2427,10 @@ The following functions must be implemented by the platform if it wants crash
reporting mechanism in BL31. The functions are implemented in assembly so that
they can be invoked without a C Runtime stack.
### Function : plat_crash_console_init
Function : plat\_crash\_console\_init
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : int
......@@ -2256,7 +2439,10 @@ This API is used by the crash reporting mechanism to initialize the crash
console. It must only use the general purpose registers x0 to x4 to do the
initialization and returns 1 on success.
### Function : plat_crash_console_putc
Function : plat\_crash\_console\_putc
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : int
Return : int
......@@ -2266,7 +2452,10 @@ designated crash console. It must only use general purpose registers x1 and
x2 to do its work. The parameter and the return value are in general purpose
register x0.
### Function : plat_crash_console_flush
Function : plat\_crash\_console\_flush
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : int
......@@ -2276,102 +2465,102 @@ data on the designated crash console. It should only use general purpose
registers x0 and x1 to do its work. The return value is 0 on successful
completion; otherwise the return value is -1.
Build flags
-----------
4. Build flags
---------------
* **ENABLE_PLAT_COMPAT**
- **ENABLE\_PLAT\_COMPAT**
All the platforms ports conforming to this API specification should define
the build flag `ENABLE_PLAT_COMPAT` to 0 as the compatibility layer should
the build flag ``ENABLE_PLAT_COMPAT`` to 0 as the compatibility layer should
be disabled. For more details on compatibility layer, refer
[Migration Guide].
`Migration Guide`_.
There are some build flags which can be defined by the platform to control
inclusion or exclusion of certain BL stages from the FIP image. These flags
need to be defined in the platform makefile which will get included by the
build system.
* **NEED_BL33**
By default, this flag is defined `yes` by the build system and `BL33`
- **NEED\_BL33**
By default, this flag is defined ``yes`` by the build system and ``BL33``
build option should be supplied as a build option. The platform has the
option of excluding the BL33 image in the `fip` image by defining this flag
to `no`. If any of the options `EL3_PAYLOAD_BASE` or `PRELOADED_BL33_BASE`
are used, this flag will be set to `no` automatically.
option of excluding the BL33 image in the ``fip`` image by defining this flag
to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE``
are used, this flag will be set to ``no`` automatically.
5. C Library
-------------
C Library
---------
To avoid subtle toolchain behavioral dependencies, the header files provided
by the compiler are not used. The software is built with the `-nostdinc` flag
by the compiler are not used. The software is built with the ``-nostdinc`` flag
to ensure no headers are included from the toolchain inadvertently. Instead the
required headers are included in the ARM Trusted Firmware source tree. The
library only contains those C library definitions required by the local
implementation. If more functionality is required, the needed library functions
will need to be added to the local implementation.
Versions of [FreeBSD] headers can be found in `include/lib/stdlib`. Some of
Versions of `FreeBSD`_ headers can be found in ``include/lib/stdlib``. Some of
these headers have been cut down in order to simplify the implementation. In
order to minimize changes to the header files, the [FreeBSD] layout has been
order to minimize changes to the header files, the `FreeBSD`_ layout has been
maintained. The generic C library definitions can be found in
`include/lib/stdlib` with more system and machine specific declarations in
`include/lib/stdlib/sys` and `include/lib/stdlib/machine`.
``include/lib/stdlib`` with more system and machine specific declarations in
``include/lib/stdlib/sys`` and ``include/lib/stdlib/machine``.
The local C library implementations can be found in `lib/stdlib`. In order to
The local C library implementations can be found in ``lib/stdlib``. In order to
extend the C library these files may need to be modified. It is recommended to
use a release version of [FreeBSD] as a starting point.
use a release version of `FreeBSD`_ as a starting point.
The C library header files in the [FreeBSD] source tree are located in the
`include` and `sys/sys` directories. [FreeBSD] machine specific definitions
can be found in the `sys/<machine-type>` directories. These files define things
The C library header files in the `FreeBSD`_ source tree are located in the
``include`` and ``sys/sys`` directories. `FreeBSD`_ machine specific definitions
can be found in the ``sys/<machine-type>`` directories. These files define things
like 'the size of a pointer' and 'the range of an integer'. Since an AArch64
port for [FreeBSD] does not yet exist, the machine specific definitions are
port for `FreeBSD`_ does not yet exist, the machine specific definitions are
based on existing machine types with similar properties (for example SPARC64).
Where possible, C library function implementations were taken from [FreeBSD]
as found in the `lib/libc` directory.
Where possible, C library function implementations were taken from `FreeBSD`_
as found in the ``lib/libc`` directory.
A copy of the `FreeBSD`_ sources can be downloaded with ``git``.
A copy of the [FreeBSD] sources can be downloaded with `git`.
::
git clone git://github.com/freebsd/freebsd.git -b origin/release/9.2.0
6. Storage abstraction layer
-----------------------------
Storage abstraction layer
-------------------------
In order to improve platform independence and portability an storage abstraction
layer is used to load data from non-volatile platform storage.
Each platform should register devices and their drivers via the Storage layer.
These drivers then need to be initialized by bootloader phases as
required in their respective `blx_platform_setup()` functions. Currently
storage access is only required by BL1 and BL2 phases. The `load_image()`
required in their respective ``blx_platform_setup()`` functions. Currently
storage access is only required by BL1 and BL2 phases. The ``load_image()``
function uses the storage layer to access non-volatile platform storage.
It is mandatory to implement at least one storage driver. For the ARM
development platforms the Firmware Image Package (FIP) driver is provided as
the default means to load data from storage (see the "Firmware Image Package"
section in the [User Guide]). The storage layer is described in the header file
`include/drivers/io/io_storage.h`. The implementation of the common library
is in `drivers/io/io_storage.c` and the driver files are located in
`drivers/io/`.
section in the `User Guide`_). The storage layer is described in the header file
``include/drivers/io/io_storage.h``. The implementation of the common library
is in ``drivers/io/io_storage.c`` and the driver files are located in
``drivers/io/``.
Each IO driver must provide `io_dev_*` structures, as described in
`drivers/io/io_driver.h`. These are returned via a mandatory registration
Each IO driver must provide ``io_dev_*`` structures, as described in
``drivers/io/io_driver.h``. These are returned via a mandatory registration
function that is called on platform initialization. The semi-hosting driver
implementation in `io_semihosting.c` can be used as an example.
implementation in ``io_semihosting.c`` can be used as an example.
The Storage layer provides mechanisms to initialize storage devices before
IO operations are called. The basic operations supported by the layer
include `open()`, `close()`, `read()`, `write()`, `size()` and `seek()`.
include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``.
Drivers do not have to implement all operations, but each platform must
provide at least one driver for a device capable of supporting generic
operations such as loading a bootloader image.
The current implementation only allows for known images to be loaded by the
firmware. These images are specified by using their identifiers, as defined in
[include/plat/common/platform_def.h] (or a separate header file included from
there). The platform layer (`plat_get_image_source()`) then returns a reference
to a device and a driver-specific `spec` which will be understood by the driver
[include/plat/common/platform\_def.h] (or a separate header file included from
there). The platform layer (``plat_get_image_source()``) then returns a reference
to a device and a driver-specific ``spec`` which will be understood by the driver
to allow access to the image data.
The layer is designed in such a way that is it possible to chain drivers with
......@@ -2385,29 +2574,26 @@ by the drivers and callers, as the system does not yet provide a means of
dynamically allocating memory. This may also have the affect of limiting the
amount of open resources per driver.
- - - - - - - - - - - - - - - - - - - - - - - - - -
_Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved._
[ARM GIC Architecture Specification 2.0]: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
[ARM GIC Architecture Specification 3.0]: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html
[IMF Design Guide]: interrupt-framework-design.md
[User Guide]: user-guide.md
[FreeBSD]: http://www.freebsd.org
[Firmware Design]: firmware-design.md
[Power Domain Topology Design]: psci-pd-tree.md
[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
[Migration Guide]: platform-migration-guide.md
[Firmware Update]: firmware-update.md
[plat/common/aarch64/platform_mp_stack.S]: ../plat/common/aarch64/platform_mp_stack.S
[plat/common/aarch64/platform_up_stack.S]: ../plat/common/aarch64/platform_up_stack.S
[plat/arm/board/fvp/fvp_pm.c]: ../plat/arm/board/fvp/fvp_pm.c
[include/common/bl_common.h]: ../include/common/bl_common.h
[include/lib/aarch32/arch.h]: ../include/lib/aarch32/arch.h
[include/plat/arm/common/arm_def.h]: ../include/plat/arm/common/arm_def.h
[include/plat/common/common_def.h]: ../include/plat/common/common_def.h
[include/plat/common/platform.h]: ../include/plat/common/platform.h
[include/plat/arm/common/plat_arm.h]: ../include/plat/arm/common/plat_arm.h]
--------------
*Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.*
.. _Migration Guide: platform-migration-guide.rst
.. _include/plat/common/platform.h: ../include/plat/common/platform.h
.. _include/plat/arm/common/plat\_arm.h: ../include/plat/arm/common/plat_arm.h%5D
.. _User Guide: user-guide.rst
.. _include/plat/common/common\_def.h: ../include/plat/common/common_def.h
.. _include/plat/arm/common/arm\_def.h: ../include/plat/arm/common/arm_def.h
.. _plat/common/aarch64/platform\_mp\_stack.S: ../plat/common/aarch64/platform_mp_stack.S
.. _plat/common/aarch64/platform\_up\_stack.S: ../plat/common/aarch64/platform_up_stack.S
.. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160
.. _Power Domain Topology Design: psci-pd-tree.rst
.. _include/common/bl\_common.h: ../include/common/bl_common.h
.. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h
.. _Firmware Design: firmware-design.rst
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
.. _plat/arm/board/fvp/fvp\_pm.c: ../plat/arm/board/fvp/fvp_pm.c
.. _IMF Design Guide: interrupt-framework-design.rst
.. _ARM Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html
.. _FreeBSD: http://www.freebsd.org
docs/psci-lib-integration-guide.md → docs/psci-lib-integration-guide.rst
View file @ 7cefb56d
PSCI Library Integration guide for ARMv8-A AArch32 systems
==========================================================
Contents
--------
1. [Introduction](#1-introduction)
2. [Generic call sequence for PSCI Library interface (AArch32)](#2-generic-call-sequence-for-psci-library-interface-aarch32)
3. [PSCI CPU context management](#3-psci-cpu-context-management)
4. [PSCI Library Interface](#4-psci-library-interface)
5. [EL3 Runtime Software dependencies](#5-el3-runtime-software-dependencies)
.. section-numbering::
:suffix: .
1. Introduction
---------------
.. contents::
This document describes the PSCI library interface with a focus on how to
integrate with a suitable Trusted OS for an ARMv8-A AArch32 system. The PSCI
Library implements the PSCI Standard as described in [PSCI spec] and is meant
Library implements the PSCI Standard as described in `PSCI spec`_ and is meant
to be integrated with EL3 Runtime Software which invokes the PSCI Library
interface appropriately. **EL3 Runtime Software** refers to software executing
at the highest secure privileged mode, which is EL3 in AArch64 or Secure SVC/
Monitor mode in AArch32, and provides runtime services to the non-secure world.
The runtime service request is made via SMC (Secure Monitor Call) and the call
must adhere to [SMCCC]. In AArch32, EL3 Runtime Software may additionally
must adhere to `SMCCC`_. In AArch32, EL3 Runtime Software may additionally
include Trusted OS functionality. A minimal AArch32 Secure Payload, SP-MIN, is
provided in ARM Trusted Firmware to illustrate the usage and integration of the
PSCI library. The description of PSCI library interface and its integration
with EL3 Runtime Software in this document is targeted towards AArch32 systems.
2. Generic call sequence for PSCI Library interface (AArch32)
-------------------------------------------------------------
Generic call sequence for PSCI Library interface (AArch32)
----------------------------------------------------------
The generic call sequence of PSCI Library interfaces
[(see section 4)](#4-psci-library-interface) during cold boot in AArch32
The generic call sequence of PSCI Library interfaces (see
`PSCI Library Interface`_) during cold boot in AArch32
system is described below:
1. After cold reset, the EL3 Runtime Software performs its cold boot
#. After cold reset, the EL3 Runtime Software performs its cold boot
initialization including the PSCI library pre-requisites mentioned in
[section 4](#4-psci-library-interface), and also the necessary platform
`PSCI Library Interface`_, and also the necessary platform
setup.
2. Call `psci_setup()` in Monitor mode.
#. Call ``psci_setup()`` in Monitor mode.
3. Optionally call `psci_register_spd_pm_hook()` to register callbacks to
#. Optionally call ``psci_register_spd_pm_hook()`` to register callbacks to
do bookkeeping for the EL3 Runtime Software during power management.
4. Call `psci_prepare_next_non_secure_ctx()` to initialize the non-secure CPU
#. Call ``psci_prepare_next_non_secure_ctx()`` to initialize the non-secure CPU
context.
5. Get the non-secure `cpu_context_t` for the current CPU by calling
`cm_get_context()` , then programming the registers in the non-secure
#. Get the non-secure ``cpu_context_t`` for the current CPU by calling
``cm_get_context()`` , then programming the registers in the non-secure
context and exiting to non-secure world. If the EL3 Runtime Software needs
additional configuration to be set for non-secure context, like routing
FIQs to the secure world, the values of the registers can be modified prior
to programming. See [section 3](#3-psci-cpu-context-management) for more
to programming. See `PSCI CPU context management`_ for more
details on CPU context management.
The generic call sequence of PSCI library interfaces during warm boot in
AArch32 systems is described below:
1. After warm reset, the EL3 Runtime Software performs the necessary warm
#. After warm reset, the EL3 Runtime Software performs the necessary warm
boot initialization including the PSCI library pre-requisites mentioned in
[section 4](#4-psci-library-interface) (Note that the Data cache
`PSCI Library Interface`_ (Note that the Data cache
**must not** be enabled).
2. Call `psci_warmboot_entrypoint()` in Monitor mode. This interface
#. Call ``psci_warmboot_entrypoint()`` in Monitor mode. This interface
initializes/restores the non-secure CPU context as well.
3. Do step 5 of the cold boot call sequence described above.
#. Do step 5 of the cold boot call sequence described above.
The generic call sequence of PSCI library interfaces on receipt of a PSCI SMC
on an AArch32 system is described below:
1. On receipt of an SMC, save the register context as per [SMCCC].
#. On receipt of an SMC, save the register context as per `SMCCC`_.
2. If the SMC function identifier corresponds to a SMC32 PSCI API, construct
the appropriate arguments and call the `psci_smc_handler()` interface.
#. If the SMC function identifier corresponds to a SMC32 PSCI API, construct
the appropriate arguments and call the ``psci_smc_handler()`` interface.
The invocation may or may not return back to the caller depending on
whether the PSCI API resulted in power down of the CPU.
3. If `psci_smc_handler()` returns, populate the return value in R0 (AArch32)/
X0 (AArch64) and restore other registers as per [SMCCC].
#. If ``psci_smc_handler()`` returns, populate the return value in R0 (AArch32)/
X0 (AArch64) and restore other registers as per `SMCCC`_.
3. PSCI CPU context management
------------------------------
PSCI CPU context management
---------------------------
PSCI library is in charge of initializing/restoring the non-secure CPU system
registers according to [PSCI specification][PSCI spec] during cold/warm boot.
This is referred to as `PSCI CPU Context Management`. Registers that need to
registers according to `PSCI specification`_ during cold/warm boot.
This is referred to as ``PSCI CPU Context Management``. Registers that need to
be preserved across CPU power down/power up cycles are maintained in
`cpu_context_t` data structure. The initialization of other non-secure CPU
``cpu_context_t`` data structure. The initialization of other non-secure CPU
system registers which do not require coordination with the EL3 Runtime
Software is done directly by the PSCI library (see `cm_prepare_el3_exit()`).
Software is done directly by the PSCI library (see ``cm_prepare_el3_exit()``).
The EL3 Runtime Software is responsible for managing register context
during switch between Normal and Secure worlds. The register context to be
saved and restored depends on the mechanism used to trigger the world switch.
For example, if the world switch was triggered by an SMC call, then the
registers need to be saved and restored according to [SMCCC]. In AArch64,
registers need to be saved and restored according to `SMCCC`_. In AArch64,
due to the tight integration with BL31, both BL31 and PSCI library
use the same `cpu_context_t` data structure for PSCI CPU context management
use the same ``cpu_context_t`` data structure for PSCI CPU context management
and register context management during world switch. This cannot be assumed
for AArch32 EL3 Runtime Software since most AArch32 Trusted OSes already implement
a mechanism for register context management during world switch. Hence, when
the PSCI library is integrated with a AArch32 EL3 Runtime Software, the
`cpu_context_t` is stripped down for just PSCI CPU context management.
``cpu_context_t`` is stripped down for just PSCI CPU context management.
During cold/warm boot, after invoking appropriate PSCI library interfaces, it
is expected that the EL3 Runtime Software will query the `cpu_context_t` and
is expected that the EL3 Runtime Software will query the ``cpu_context_t`` and
write appropriate values to the corresponding system registers. This mechanism
resolves 2 additional problems for AArch32 EL3 Runtime Software:
1. Values for certain system registers like SCR and SCTLR cannot be
#. Values for certain system registers like SCR and SCTLR cannot be
unilaterally determined by PSCI library and need inputs from the EL3
Runtime Software. Using `cpu_context_t` as an intermediary data store
Runtime Software. Using ``cpu_context_t`` as an intermediary data store
allows EL3 Runtime Software to modify the register values appropriately
before programming them.
2. The PSCI library provides appropriate LR and SPSR values (entrypoint
information) for exit into non-secure world. Using `cpu_context_t` as an
#. The PSCI library provides appropriate LR and SPSR values (entrypoint
information) for exit into non-secure world. Using ``cpu_context_t`` as an
intermediary data store allows the EL3 Runtime Software to store these
values safely until it is ready for exit to non-secure world.
Currently the `cpu_context_t` data structure for AArch32 stores the following
Currently the ``cpu_context_t`` data structure for AArch32 stores the following
registers: R0 - R3, LR (R14), SCR, SPSR, SCTLR.
The EL3 Runtime Software must implement accessors to get/set pointers
to CPU context `cpu_context_t` data and these are described in
[section 5.2](#52-cpu-context-management-api).
to CPU context ``cpu_context_t`` data and these are described in
`CPU Context management API`_.
PSCI Library Interface
----------------------
4. PSCI Library Interface
-------------------------
The PSCI library implements the `PSCI Specification`_. The interfaces
to this library are declared in ``psci.h`` and are as listed below:
The PSCI library implements the [PSCI Specification][PSCI spec]. The interfaces
to this library are declared in `psci.h` and are as listed below:
.. code:: c
```
u_register_t psci_smc_handler(uint32_t smc_fid, u_register_t x1,
u_register_t x2, u_register_t x3,
u_register_t x4, void *cookie,
......@@ -146,104 +138,115 @@ to this library are declared in `psci.h` and are as listed below:
void psci_warmboot_entrypoint(void);
void psci_register_spd_pm_hook(const spd_pm_ops_t *pm);
void psci_prepare_next_non_secure_ctx(entry_point_info_t *next_image_info);
```
The CPU context data 'cpu_context_t' is programmed to the registers differently
The CPU context data 'cpu\_context\_t' is programmed to the registers differently
when PSCI is integrated with an AArch32 EL3 Runtime Software compared to
when the PSCI is integrated with an AArch64 EL3 Runtime Software (BL31). For
example, in the case of AArch64, there is no need to retrieve `cpu_context_t`
example, in the case of AArch64, there is no need to retrieve ``cpu_context_t``
data and program the registers as it will done implicitly as part of
`el3_exit`. The description below of the PSCI interfaces is targeted at
``el3_exit``. The description below of the PSCI interfaces is targeted at
integration with an AArch32 EL3 Runtime Software.
The PSCI library is responsible for initializing/restoring the non-secure world
to an appropriate state after boot and may choose to directly program the
non-secure system registers. The PSCI generic code takes care not to directly
modify any of the system registers affecting the secure world and instead
returns the values to be programmed to these registers via `cpu_context_t`.
returns the values to be programmed to these registers via ``cpu_context_t``.
The EL3 Runtime Software is responsible for programming those registers and
can use the proposed values provided in the `cpu_context_t`, modifying the
can use the proposed values provided in the ``cpu_context_t``, modifying the
values if required.
PSCI library needs the flexibility to access both secure and non-secure
copies of banked registers. Hence it needs to be invoked in Monitor mode
for AArch32 and in EL3 for AArch64. The NS bit in SCR (in AArch32) or SCR_EL3
for AArch32 and in EL3 for AArch64. The NS bit in SCR (in AArch32) or SCR\_EL3
(in AArch64) must be set to 0. Additional requirements for the PSCI library
interfaces are:
* Instruction cache must be enabled
* Both IRQ and FIQ must be masked for the current CPU
* The page tables must be setup and the MMU enabled
* The C runtime environment must be setup and stack initialized
* The Data cache must be enabled prior to invoking any of the PSCI library
interfaces except for `psci_warmboot_entrypoint()`. For
`psci_warmboot_entrypoint()`, if the build option `HW_ASSISTED_COHERENCY`
- Instruction cache must be enabled
- Both IRQ and FIQ must be masked for the current CPU
- The page tables must be setup and the MMU enabled
- The C runtime environment must be setup and stack initialized
- The Data cache must be enabled prior to invoking any of the PSCI library
interfaces except for ``psci_warmboot_entrypoint()``. For
``psci_warmboot_entrypoint()``, if the build option ``HW_ASSISTED_COHERENCY``
is enabled however, data caches are expected to be enabled.
Further requirements for each interface can be found in the interface
description.
### 4.1 Interface : psci_setup()
Interface : psci\_setup()
~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : const psci_lib_args_t *lib_args
Return : void
This function is to be called by the primary CPU during cold boot before
any other interface to the PSCI library. It takes `lib_args`, a const pointer
to `psci_lib_args_t`, as the argument. The `psci_lib_args_t` is a versioned
structure and is declared in `psci.h` header as follows:
any other interface to the PSCI library. It takes ``lib_args``, a const pointer
to ``psci_lib_args_t``, as the argument. The ``psci_lib_args_t`` is a versioned
structure and is declared in ``psci.h`` header as follows:
.. code:: c
```
typedef struct psci_lib_args {
/* The version information of PSCI Library Interface */
param_header_t h;
/* The warm boot entrypoint function */
mailbox_entrypoint_t mailbox_ep;
} psci_lib_args_t;
```
The first field `h`, of `param_header_t` type, provides the version
information. The second field `mailbox_ep` is the warm boot entrypoint address
The first field ``h``, of ``param_header_t`` type, provides the version
information. The second field ``mailbox_ep`` is the warm boot entrypoint address
and is used to configure the platform mailbox. Helper macros are provided in
psci.h to construct the `lib_args` argument statically or during runtime. Prior
to calling the `psci_setup()` interface, the platform setup for cold boot
psci.h to construct the ``lib_args`` argument statically or during runtime. Prior
to calling the ``psci_setup()`` interface, the platform setup for cold boot
must have completed. Major actions performed by this interface are:
* Initializes architecture.
* Initializes PSCI power domain and state coordination data structures.
* Calls `plat_setup_psci_ops()` with warm boot entrypoint `mailbox_ep` as
- Initializes architecture.
- Initializes PSCI power domain and state coordination data structures.
- Calls ``plat_setup_psci_ops()`` with warm boot entrypoint ``mailbox_ep`` as
argument.
* Calls `cm_set_context_by_index()` (see
[section 5.2](#52-cpu-context-management-api)) for all the CPUs in the
- Calls ``cm_set_context_by_index()`` (see
`CPU Context management API`_) for all the CPUs in the
platform
### 4.2 Interface : psci_prepare_next_non_secure_ctx()
Interface : psci\_prepare\_next\_non\_secure\_ctx()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : entry_point_info_t *next_image_info
Return : void
After `psci_setup()` and prior to exit to the non-secure world, this function
After ``psci_setup()`` and prior to exit to the non-secure world, this function
must be called by the EL3 Runtime Software to initialize the non-secure world
context. The non-secure world entrypoint information `next_image_info` (first
context. The non-secure world entrypoint information ``next_image_info`` (first
argument) will be used to determine the non-secure context. After this function
returns, the EL3 Runtime Software must retrieve the `cpu_context_t` (using
cm_get_context()) for the current CPU and program the registers prior to exit
returns, the EL3 Runtime Software must retrieve the ``cpu_context_t`` (using
cm\_get\_context()) for the current CPU and program the registers prior to exit
to the non-secure world.
### 4.3 Interface : psci_register_spd_pm_hook()
Interface : psci\_register\_spd\_pm\_hook()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : const spd_pm_ops_t *
Return : void
As explained in [section 5.4](#54-secure-payload-power-management-callback),
As explained in `Secure payload power management callback`_,
the EL3 Runtime Software may want to perform some bookkeeping during power
management operations. This function is used to register the `spd_pm_ops_t`
management operations. This function is used to register the ``spd_pm_ops_t``
(first argument) callbacks with the PSCI library which will be called
ppropriately during power management. Calling this function is optional and
need to be called by the primary CPU during the cold boot sequence after
`psci_setup()` has completed.
``psci_setup()`` has completed.
Interface : psci\_smc\_handler()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### 4.4 Interface : psci_smc_handler()
::
Argument : uint32_t smc_fid, u_register_t x1,
u_register_t x2, u_register_t x3,
......@@ -252,60 +255,63 @@ need to be called by the primary CPU during the cold boot sequence after
Return : u_register_t
This function is the top level handler for SMCs which fall within the
PSCI service range specified in [SMCCC]. The function ID `smc_fid` (first
argument) determines the PSCI API to be called. The `x1` to `x4` (2nd to 5th
PSCI service range specified in `SMCCC`_. The function ID ``smc_fid`` (first
argument) determines the PSCI API to be called. The ``x1`` to ``x4`` (2nd to 5th
arguments), are the values of the registers r1 - r4 (in AArch32) or x1 - x4
(in AArch64) when the SMC is received. These are the arguments to PSCI API as
described in [PSCI spec]. The 'flags' (8th argument) is a bit field parameter
described in `PSCI spec`_. The 'flags' (8th argument) is a bit field parameter
and is detailed in 'smcc.h' header. It includes whether the call is from the
secure or non-secure world. The `cookie` (6th argument) and the `handle`
secure or non-secure world. The ``cookie`` (6th argument) and the ``handle``
(7th argument) are not used and are reserved for future use.
The return value from this interface is the return value from the underlying
PSCI API corresponding to `smc_fid`. This function may not return back to the
PSCI API corresponding to ``smc_fid``. This function may not return back to the
caller if PSCI API causes power down of the CPU. In this case, when the CPU
wakes up, it will start execution from the warm reset address.
### 4.5 Interface : psci_warmboot_entrypoint()
Interface : psci\_warmboot\_entrypoint()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : void
This function performs the warm boot initialization/restoration as mandated by
[PSCI spec]. For AArch32, on wakeup from power down the CPU resets to secure SVC
`PSCI spec`_. For AArch32, on wakeup from power down the CPU resets to secure SVC
mode and the EL3 Runtime Software must perform the prerequisite initializations
mentioned at top of this section. This function must be called with Data cache
disabled (unless build option `HW_ASSISTED_COHERENCY` is enabled) but with MMU
disabled (unless build option ``HW_ASSISTED_COHERENCY`` is enabled) but with MMU
initialized and enabled. The major actions performed by this function are:
* Invalidates the stack and enables the data cache.
* Initializes architecture and PSCI state coordination.
* Restores/Initializes the peripheral drivers to the required state via
appropriate `plat_psci_ops_t` hooks
* Restores the EL3 Runtime Software context via appropriate `spd_pm_ops_t`
- Invalidates the stack and enables the data cache.
- Initializes architecture and PSCI state coordination.
- Restores/Initializes the peripheral drivers to the required state via
appropriate ``plat_psci_ops_t`` hooks
- Restores the EL3 Runtime Software context via appropriate ``spd_pm_ops_t``
callbacks.
* Restores/Initializes the non-secure context and populates the
`cpu_context_t` for the current CPU.
- Restores/Initializes the non-secure context and populates the
``cpu_context_t`` for the current CPU.
Upon the return of this function, the EL3 Runtime Software must retrieve the
non-secure `cpu_context_t` using `cm_get_context()` and program the registers
non-secure ``cpu_context_t`` using ``cm_get_context()`` and program the registers
prior to exit to the non-secure world.
5. EL3 Runtime Software dependencies
---------------------------------------
EL3 Runtime Software dependencies
---------------------------------
The PSCI Library includes supporting frameworks like context management,
cpu operations (cpu_ops) and per-cpu data framework. Other helper library
cpu operations (cpu\_ops) and per-cpu data framework. Other helper library
functions like bakery locks and spin locks are also included in the library.
The dependencies which must be fulfilled by the EL3 Runtime Software
for integration with PSCI library are described below.
### 5.1 General dependencies
General dependencies
~~~~~~~~~~~~~~~~~~~~
The PSCI library being a Multiprocessor (MP) implementation, EL3 Runtime
Software must provide an SMC handling framework capable of MP adhering to
[SMCCC] specification.
`SMCCC`_ specification.
The EL3 Runtime Software must also export cache maintenance primitives
and some helper utilities for assert, print and memory operations as listed
......@@ -316,23 +322,29 @@ these functions but the EL3 Runtime Software may use its own implementation.
These must be implemented as described in ISO C Standard.
**Function : flush_dcache_range()**
**Function : flush\_dcache\_range()**
::
Argument : uintptr_t addr, size_t size
Return : void
This function cleans and invalidates (flushes) the data cache for memory
at address `addr` (first argument) address and of size `size` (second argument).
at address ``addr`` (first argument) address and of size ``size`` (second argument).
**Function : inv\_dcache\_range()**
**Function : inv_dcache_range()**
::
Argument : uintptr_t addr, size_t size
Return : void
This function invalidates (flushes) the data cache for memory at address
`addr` (first argument) address and of size `size` (second argument).
``addr`` (first argument) address and of size ``size`` (second argument).
**Function : do\_panic()**
**Function : do_panic()**
::
Argument : void
Return : void
......@@ -340,15 +352,16 @@ This function invalidates (flushes) the data cache for memory at address
This function will be called by the PSCI library on encountering a critical
failure that cannot be recovered from. This function **must not** return.
**Function : tf_printf()**
**Function : tf\_printf()**
This is printf-compatible function, but unlike printf, it does not return any
value. The ARM Trusted Firmware source tree provides an implementation which
is optimized for stack usage and supports only a subset of format specifiers.
The details of the format specifiers supported can be found in the
`tf_printf.c` file in ARM Trusted Firmware source tree.
``tf_printf.c`` file in ARM Trusted Firmware source tree.
### 5.2 CPU Context management API
CPU Context management API
~~~~~~~~~~~~~~~~~~~~~~~~~~
The CPU context management data memory is statically allocated by PSCI library
in BSS section. The PSCI library requires the EL3 Runtime Software to implement
......@@ -357,52 +370,59 @@ demonstrates how these APIs can be implemented but the EL3 Runtime Software can
choose a more optimal implementation (like dedicating the secure TPIDRPRW
system register (in AArch32) for storing these pointers).
**Function : cm_set_context_by_index()**
**Function : cm\_set\_context\_by\_index()**
::
Argument : unsigned int cpu_idx, void *context, unsigned int security_state
Return : void
This function is called during cold boot when the `psci_setup()` PSCI library
This function is called during cold boot when the ``psci_setup()`` PSCI library
interface is called.
This function must store the pointer to the CPU context data, `context` (2nd
argument), for the specified `security_state` (3rd argument) and CPU identified
by `cpu_idx` (first argument). The `security_state` will always be non-secure
This function must store the pointer to the CPU context data, ``context`` (2nd
argument), for the specified ``security_state`` (3rd argument) and CPU identified
by ``cpu_idx`` (first argument). The ``security_state`` will always be non-secure
when called by PSCI library and this argument is retained for compatibility
with BL31. The `cpu_idx` will correspond to the index returned by the
`plat_core_pos_by_mpidr()` for `mpidr` of the CPU.
with BL31. The ``cpu_idx`` will correspond to the index returned by the
``plat_core_pos_by_mpidr()`` for ``mpidr`` of the CPU.
The actual method of storing the ``context`` pointers is implementation specific.
For example, SP-MIN stores the pointers in the array ``sp_min_cpu_ctx_ptr``
declared in ``sp_min_main.c``.
The actual method of storing the `context` pointers is implementation specific.
For example, SP-MIN stores the pointers in the array `sp_min_cpu_ctx_ptr`
declared in `sp_min_main.c`.
**Function : cm\_get\_context()**
**Function : cm_get_context()**
::
Argument : uint32_t security_state
Return : void *
This function must return the pointer to the `cpu_context_t` structure for
the specified `security_state` (first argument) for the current CPU. The caller
must ensure that `cm_set_context_by_index` is called first and the appropriate
context pointers are stored prior to invoking this API. The `security_state`
This function must return the pointer to the ``cpu_context_t`` structure for
the specified ``security_state`` (first argument) for the current CPU. The caller
must ensure that ``cm_set_context_by_index`` is called first and the appropriate
context pointers are stored prior to invoking this API. The ``security_state``
will always be non-secure when called by PSCI library and this argument
is retained for compatibility with BL31.
**Function : cm_get_context_by_index()**
**Function : cm\_get\_context\_by\_index()**
::
Argument : unsigned int cpu_idx, unsigned int security_state
Return : void *
This function must return the pointer to the `cpu_context_t` structure for
the specified `security_state` (second argument) for the CPU identified by
`cpu_idx` (first argument). The caller must ensure that
`cm_set_context_by_index` is called first and the appropriate context
pointers are stored prior to invoking this API. The `security_state` will
This function must return the pointer to the ``cpu_context_t`` structure for
the specified ``security_state`` (second argument) for the CPU identified by
``cpu_idx`` (first argument). The caller must ensure that
``cm_set_context_by_index`` is called first and the appropriate context
pointers are stored prior to invoking this API. The ``security_state`` will
always be non-secure when called by PSCI library and this argument is
retained for compatibility with BL31. The `cpu_idx` will correspond to the
index returned by the `plat_core_pos_by_mpidr()` for `mpidr` of the CPU.
retained for compatibility with BL31. The ``cpu_idx`` will correspond to the
index returned by the ``plat_core_pos_by_mpidr()`` for ``mpidr`` of the CPU.
### 5.3 Platform API
Platform API
~~~~~~~~~~~~
The platform layer abstracts the platform-specific details from the generic
PSCI library. The following platform APIs/macros must be defined by the EL3
......@@ -410,42 +430,43 @@ Runtime Software for integration with the PSCI library.
The mandatory platform APIs are:
* plat_my_core_pos
* plat_core_pos_by_mpidr
* plat_get_syscnt_freq2
* plat_get_power_domain_tree_desc
* plat_setup_psci_ops
* plat_reset_handler
* plat_panic_handler
* plat_get_my_stack
- plat\_my\_core\_pos
- plat\_core\_pos\_by\_mpidr
- plat\_get\_syscnt\_freq2
- plat\_get\_power\_domain\_tree\_desc
- plat\_setup\_psci\_ops
- plat\_reset\_handler
- plat\_panic\_handler
- plat\_get\_my\_stack
The mandatory platform macros are:
* PLATFORM_CORE_COUNT
* PLAT_MAX_PWR_LVL
* PLAT_NUM_PWR_DOMAINS
* CACHE_WRITEBACK_GRANULE
* PLAT_MAX_OFF_STATE
* PLAT_MAX_RET_STATE
* PLAT_MAX_PWR_LVL_STATES (optional)
* PLAT_PCPU_DATA_SIZE (optional)
- PLATFORM\_CORE\_COUNT
- PLAT\_MAX\_PWR\_LVL
- PLAT\_NUM\_PWR\_DOMAINS
- CACHE\_WRITEBACK\_GRANULE
- PLAT\_MAX\_OFF\_STATE
- PLAT\_MAX\_RET\_STATE
- PLAT\_MAX\_PWR\_LVL\_STATES (optional)
- PLAT\_PCPU\_DATA\_SIZE (optional)
The details of these APIs/macros can be found in [Porting Guide].
The details of these APIs/macros can be found in `Porting Guide`_.
All platform specific operations for power management are done via
`plat_psci_ops_t` callbacks registered by the platform when
`plat_setup_psci_ops()` API is called. The description of each of
the callbacks in `plat_psci_ops_t` can be found in PSCI section of the
[Porting Guide]. If any these callbacks are not registered, then the
``plat_psci_ops_t`` callbacks registered by the platform when
``plat_setup_psci_ops()`` API is called. The description of each of
the callbacks in ``plat_psci_ops_t`` can be found in PSCI section of the
`Porting Guide`_. If any these callbacks are not registered, then the
PSCI API associated with that callback will not be supported by PSCI
library.
### 5.4 Secure payload power management callback
Secure payload power management callback
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
During PSCI power management operations, the EL3 Runtime Software may
need to perform some bookkeeping, and PSCI library provides
`spd_pm_ops_t` callbacks for this purpose. These hooks must be
populated and registered by using `psci_register_spd_pm_hook()` PSCI
``spd_pm_ops_t`` callbacks for this purpose. These hooks must be
populated and registered by using ``psci_register_spd_pm_hook()`` PSCI
library interface.
Typical bookkeeping during PSCI power management calls include save/restore
......@@ -456,7 +477,8 @@ to the current CPU must be disabled or re-targeted to other running CPU prior
to power down of the current CPU. During power up, these interrupt can be
enabled/re-targeted back to the current CPU.
```
.. code:: c
typedef struct spd_pm_ops {
void (*svc_on)(u_register_t target_cpu);
int32_t (*svc_off)(u_register_t __unused);
......@@ -468,70 +490,71 @@ enabled/re-targeted back to the current CPU.
void (*svc_system_off)(void);
void (*svc_system_reset)(void);
} spd_pm_ops_t;
```
A brief description of each callback is given below:
* svc_on, svc_off, svc_on_finish
- svc\_on, svc\_off, svc\_on\_finish
The `svc_on`, `svc_off` callbacks are called during PSCI_CPU_ON,
PSCI_CPU_OFF APIs respectively. The `svc_on_finish` is called when the
target CPU of PSCI_CPU_ON API powers up and executes the
`psci_warmboot_entrypoint()` PSCI library interface.
The ``svc_on``, ``svc_off`` callbacks are called during PSCI\_CPU\_ON,
PSCI\_CPU\_OFF APIs respectively. The ``svc_on_finish`` is called when the
target CPU of PSCI\_CPU\_ON API powers up and executes the
``psci_warmboot_entrypoint()`` PSCI library interface.
* svc_suspend, svc_suspend_finish
- svc\_suspend, svc\_suspend\_finish
The `svc_suspend` callback is called during power down bu either
PSCI_SUSPEND or PSCI_SYSTEM_SUSPEND APIs. The `svc_suspend_finish` is
The ``svc_suspend`` callback is called during power down bu either
PSCI\_SUSPEND or PSCI\_SYSTEM\_SUSPEND APIs. The ``svc_suspend_finish`` is
called when the CPU wakes up from suspend and executes the
`psci_warmboot_entrypoint()` PSCI library interface. The `max_off_pwrlvl`
``psci_warmboot_entrypoint()`` PSCI library interface. The ``max_off_pwrlvl``
(first parameter) denotes the highest power domain level being powered down
to or woken up from suspend.
* svc_system_off, svc_system_reset
- svc\_system\_off, svc\_system\_reset
These callbacks are called during PSCI_SYSTEM_OFF and PSCI_SYSTEM_RESET
These callbacks are called during PSCI\_SYSTEM\_OFF and PSCI\_SYSTEM\_RESET
PSCI APIs respectively.
* svc_migrate_info
- svc\_migrate\_info
This callback is called in response to PSCI_MIGRATE_INFO_TYPE or
PSCI_MIGRATE_INFO_UP_CPU APIs. The return value of this callback must
correspond to the return value of PSCI_MIGRATE_INFO_TYPE API as described
in [PSCI spec]. If the secure payload is a Uniprocessor (UP)
This callback is called in response to PSCI\_MIGRATE\_INFO\_TYPE or
PSCI\_MIGRATE\_INFO\_UP\_CPU APIs. The return value of this callback must
correspond to the return value of PSCI\_MIGRATE\_INFO\_TYPE API as described
in `PSCI spec`_. If the secure payload is a Uniprocessor (UP)
implementation, then it must update the mpidr of the CPU it is resident in
via `resident_cpu` (first argument). The updates to `resident_cpu` is
via ``resident_cpu`` (first argument). The updates to ``resident_cpu`` is
ignored if the secure payload is a multiprocessor (MP) implementation.
* svc_migrate
- svc\_migrate
This callback is only relevant if the secure payload in EL3 Runtime
Software is a Uniprocessor (UP) implementation and supports migration from
the current CPU `from_cpu` (first argument) to another CPU `to_cpu`
(second argument). This callback is called in response to PSCI_MIGRATE
the current CPU ``from_cpu`` (first argument) to another CPU ``to_cpu``
(second argument). This callback is called in response to PSCI\_MIGRATE
API. This callback is never called if the secure payload is a
Multiprocessor (MP) implementation.
### 5.5 CPU operations
CPU operations
~~~~~~~~~~~~~~
The CPU operations (cpu_ops) framework implement power down sequence specific
to the CPU and the details of which can be found in the `CPU specific
operations framework` section of [Firmware Design]. The ARM Trusted Firmware
tree implements the `cpu_ops` for various supported CPUs and the EL3 Runtime
Software needs to include the required `cpu_ops` in its build. The start and
end of the `cpu_ops` descriptors must be exported by the EL3 Runtime Software
via the `__CPU_OPS_START__` and `__CPU_OPS_END__` linker symbols.
The CPU operations (cpu\_ops) framework implement power down sequence specific
to the CPU and the details of which can be found in the ``CPU specific operations framework`` section of `Firmware Design`_. The ARM Trusted Firmware
tree implements the ``cpu_ops`` for various supported CPUs and the EL3 Runtime
Software needs to include the required ``cpu_ops`` in its build. The start and
end of the ``cpu_ops`` descriptors must be exported by the EL3 Runtime Software
via the ``__CPU_OPS_START__`` and ``__CPU_OPS_END__`` linker symbols.
The `cpu_ops` descriptors also include reset sequences and may include errata
The ``cpu_ops`` descriptors also include reset sequences and may include errata
workarounds for the CPU. The EL3 Runtime Software can choose to call this
during cold/warm reset if it does not implement its own reset sequence/errata
workarounds.
--------------
- - - - - - - - - - - - - - - - - - - - - - - - - -
_Copyright (c) 2016, ARM Limited and Contributors. All rights reserved._
*Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.*
[PSCI spec]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf "Power State Coordination Interface PDD (ARM DEN 0022C)"
[SMCCC]: https://silver.arm.com/download/ARM_and_AMBA_Architecture/AR570-DA-80002-r0p0-00rel0/ARM_DEN0028A_SMC_Calling_Convention.pdf "SMC Calling Convention"
[Porting Guide]: porting-guide.md
[Firmware Design]: ./firmware-design.md
.. _PSCI spec: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
.. _SMCCC: https://silver.arm.com/download/ARM_and_AMBA_Architecture/AR570-DA-80002-r0p0-00rel0/ARM_DEN0028A_SMC_Calling_Convention.pdf
.. _PSCI specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
.. _PSCI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
.. _Porting Guide: porting-guide.rst
.. _Firmware Design: ./firmware-design.rst
docs/psci-pd-tree.md deleted 100644 → 0
View file @ aa5b843f
------------
Requirements
------------
1. A platform must export the `plat_get_aff_count()` and
`plat_get_aff_state()` APIs to enable the generic PSCI code to
populate a tree that describes the hierarchy of power domains in the
system. This approach is inflexible because a change to the topology
requires a change in the code.
It would be much simpler for the platform to describe its power domain tree
in a data structure.
2. The generic PSCI code generates MPIDRs in order to populate the power domain
tree. It also uses an MPIDR to find a node in the tree. The assumption that
a platform will use exactly the same MPIDRs as generated by the generic PSCI
code is not scalable. The use of an MPIDR also restricts the number of
levels in the power domain tree to four.
Therefore, there is a need to decouple allocation of MPIDRs from the
mechanism used to populate the power domain topology tree.
3. The current arrangement of the power domain tree requires a binary search
over the sibling nodes at a particular level to find a specified power
domain node. During a power management operation, the tree is traversed from
a 'start' to an 'end' power level. The binary search is required to find the
node at each level. The natural way to perform this traversal is to
start from a leaf node and follow the parent node pointer to reach the end
level.
Therefore, there is a need to define data structures that implement the tree in
a way which facilitates such a traversal.
4. The attributes of a core power domain differ from the attributes of power
domains at higher levels. For example, only a core power domain can be identified
using an MPIDR. There is no requirement to perform state coordination while
performing a power management operation on the core power domain.
Therefore, there is a need to implement the tree in a way which facilitates this
distinction between a leaf and non-leaf node and any associated
optimizations.
------
Design
------
### Describing a power domain tree
To fulfill requirement 1., the existing platform APIs
`plat_get_aff_count()` and `plat_get_aff_state()` have been
removed. A platform must define an array of unsigned chars such that:
1. The first entry in the array specifies the number of power domains at the
highest power level implemented in the platform. This caters for platforms
where the power domain tree does not have a single root node, for example,
the FVP has two cluster power domains at the highest level (1).
2. Each subsequent entry corresponds to a power domain and contains the number
of power domains that are its direct children.
3. The size of the array minus the first entry will be equal to the number of
non-leaf power domains.
4. The value in each entry in the array is used to find the number of entries
to consider at the next level. The sum of the values (number of children) of
all the entries at a level specifies the number of entries in the array for
the next level.
The following example power domain topology tree will be used to describe the
above text further. The leaf and non-leaf nodes in this tree have been numbered
separately.
```
+-+
|0|
+-+
/ \
/ \
/ \
/ \
/ \
/ \
/ \
/ \
/ \
/ \
+-+ +-+
|1| |2|
+-+ +-+
/ \ / \
/ \ / \
/ \ / \
/ \ / \
+-+ +-+ +-+ +-+
|3| |4| |5| |6|
+-+ +-+ +-+ +-+
+---+-----+ +----+----| +----+----+ +----+-----+-----+
| | | | | | | | | | | | |
| | | | | | | | | | | | |
v v v v v v v v v v v v v
+-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +--+ +--+ +--+
|0| |1| |2| |3| |4| |5| |6| |7| |8| |9| |10| |11| |12|
+-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +--+ +--+ +--+
```
This tree is defined by the platform as the array described above as follows:
```
#define PLAT_NUM_POWER_DOMAINS 20
#define PLATFORM_CORE_COUNT 13
#define PSCI_NUM_NON_CPU_PWR_DOMAINS \
(PLAT_NUM_POWER_DOMAINS - PLATFORM_CORE_COUNT)
unsigned char plat_power_domain_tree_desc[] = { 1, 2, 2, 2, 3, 3, 3, 4};
```
### Removing assumptions about MPIDRs used in a platform
To fulfill requirement 2., it is assumed that the platform assigns a
unique number (core index) between `0` and `PLAT_CORE_COUNT - 1` to each core
power domain. MPIDRs could be allocated in any manner and will not be used to
populate the tree.
`plat_core_pos_by_mpidr(mpidr)` will return the core index for the core
corresponding to the MPIDR. It will return an error (-1) if an MPIDR is passed
which is not allocated or corresponds to an absent core. The semantics of this
platform API have changed since it is required to validate the passed MPIDR. It
has been made a mandatory API as a result.
Another mandatory API, `plat_my_core_pos()` has been added to return the core
index for the calling core. This API provides a more lightweight mechanism to get
the index since there is no need to validate the MPIDR of the calling core.
The platform should assign the core indices (as illustrated in the diagram above)
such that, if the core nodes are numbered from left to right, then the index
for a core domain will be the same as the index returned by
`plat_core_pos_by_mpidr()` or `plat_my_core_pos()` for that core. This
relationship allows the core nodes to be allocated in a separate array
(requirement 4.) during `psci_setup()` in such an order that the index of the
core in the array is the same as the return value from these APIs.
#### Dealing with holes in MPIDR allocation
For platforms where the number of allocated MPIDRs is equal to the number of
core power domains, for example, Juno and FVPs, the logic to convert an MPIDR to
a core index should remain unchanged. Both Juno and FVP use a simple collision
proof hash function to do this.
It is possible that on some platforms, the allocation of MPIDRs is not
contiguous or certain cores have been disabled. This essentially means that the
MPIDRs have been sparsely allocated, that is, the size of the range of MPIDRs
used by the platform is not equal to the number of core power domains.
The platform could adopt one of the following approaches to deal with this
scenario:
1. Implement more complex logic to convert a valid MPIDR to a core index while
maintaining the relationship described earlier. This means that the power
domain tree descriptor will not describe any core power domains which are
disabled or absent. Entries will not be allocated in the tree for these
domains.
2. Treat unallocated MPIDRs and disabled cores as absent but still describe them
in the power domain descriptor, that is, the number of core nodes described
is equal to the size of the range of MPIDRs allocated. This approach will
lead to memory wastage since entries will be allocated in the tree but will
allow use of a simpler logic to convert an MPIDR to a core index.
### Traversing through and distinguishing between core and non-core power domains
To fulfill requirement 3 and 4, separate data structures have been defined
to represent leaf and non-leaf power domain nodes in the tree.
```
/*******************************************************************************
* The following two data structures implement the power domain tree. The tree
* is used to track the state of all the nodes i.e. power domain instances
* described by the platform. The tree consists of nodes that describe CPU power
* domains i.e. leaf nodes and all other power domains which are parents of a
* CPU power domain i.e. non-leaf nodes.
******************************************************************************/
typedef struct non_cpu_pwr_domain_node {
/*
* Index of the first CPU power domain node level 0 which has this node
* as its parent.
*/
unsigned int cpu_start_idx;
/*
* Number of CPU power domains which are siblings of the domain indexed
* by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
* -> cpu_start_idx + ncpus' have this node as their parent.
*/
unsigned int ncpus;
/* Index of the parent power domain node */
unsigned int parent_node;
-----
} non_cpu_pd_node_t;
typedef struct cpu_pwr_domain_node {
u_register_t mpidr;
/* Index of the parent power domain node */
unsigned int parent_node;
-----
} cpu_pd_node_t;
```
The power domain tree is implemented as a combination of the following data
structures.
```
non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS];
cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
```
### Populating the power domain tree
The `populate_power_domain_tree()` function in `psci_setup.c` implements the
algorithm to parse the power domain descriptor exported by the platform to
populate the two arrays. It is essentially a breadth-first-search. The nodes for
each level starting from the root are laid out one after another in the
`psci_non_cpu_pd_nodes` and `psci_cpu_pd_nodes` arrays as follows:
```
psci_non_cpu_pd_nodes -> [[Level 3 nodes][Level 2 nodes][Level 1 nodes]]
psci_cpu_pd_nodes -> [Level 0 nodes]
```
For the example power domain tree illustrated above, the `psci_cpu_pd_nodes`
will be populated as follows. The value in each entry is the index of the parent
node. Other fields have been ignored for simplicity.
```
+-------------+ ^
CPU0 | 3 | |
+-------------+ |
CPU1 | 3 | |
+-------------+ |
CPU2 | 3 | |
+-------------+ |
CPU3 | 4 | |
+-------------+ |
CPU4 | 4 | |
+-------------+ |
CPU5 | 4 | | PLATFORM_CORE_COUNT
+-------------+ |
CPU6 | 5 | |
+-------------+ |
CPU7 | 5 | |
+-------------+ |
CPU8 | 5 | |
+-------------+ |
CPU9 | 6 | |
+-------------+ |
CPU10 | 6 | |
+-------------+ |
CPU11 | 6 | |
+-------------+ |
CPU12 | 6 | v
+-------------+
```
The `psci_non_cpu_pd_nodes` array will be populated as follows. The value in
each entry is the index of the parent node.
```
+-------------+ ^
PD0 | -1 | |
+-------------+ |
PD1 | 0 | |
+-------------+ |
PD2 | 0 | |
+-------------+ |
PD3 | 1 | | PLAT_NUM_POWER_DOMAINS -
+-------------+ | PLATFORM_CORE_COUNT
PD4 | 1 | |
+-------------+ |
PD5 | 2 | |
+-------------+ |
PD6 | 2 | |
+-------------+ v
```
Each core can find its node in the `psci_cpu_pd_nodes` array using the
`plat_my_core_pos()` function. When a core is turned on, the normal world
provides an MPIDR. The `plat_core_pos_by_mpidr()` function is used to validate
the MPIDR before using it to find the corresponding core node. The non-core power
domain nodes do not need to be identified.
docs/psci-pd-tree.rst 0 → 100644
View file @ 7cefb56d
PSCI Library Integration guide for ARMv8-A AArch32 systems
==========================================================
.. section-numbering::
:suffix: .
.. contents::
--------------
Requirements
------------
#. A platform must export the ``plat_get_aff_count()`` and
``plat_get_aff_state()`` APIs to enable the generic PSCI code to
populate a tree that describes the hierarchy of power domains in the
system. This approach is inflexible because a change to the topology
requires a change in the code.
It would be much simpler for the platform to describe its power domain tree
in a data structure.
#. The generic PSCI code generates MPIDRs in order to populate the power domain
tree. It also uses an MPIDR to find a node in the tree. The assumption that
a platform will use exactly the same MPIDRs as generated by the generic PSCI
code is not scalable. The use of an MPIDR also restricts the number of
levels in the power domain tree to four.
Therefore, there is a need to decouple allocation of MPIDRs from the
mechanism used to populate the power domain topology tree.
#. The current arrangement of the power domain tree requires a binary search
over the sibling nodes at a particular level to find a specified power
domain node. During a power management operation, the tree is traversed from
a 'start' to an 'end' power level. The binary search is required to find the
node at each level. The natural way to perform this traversal is to
start from a leaf node and follow the parent node pointer to reach the end
level.
Therefore, there is a need to define data structures that implement the tree in
a way which facilitates such a traversal.
#. The attributes of a core power domain differ from the attributes of power
domains at higher levels. For example, only a core power domain can be identified
using an MPIDR. There is no requirement to perform state coordination while
performing a power management operation on the core power domain.
Therefore, there is a need to implement the tree in a way which facilitates this
distinction between a leaf and non-leaf node and any associated
optimizations.
--------------
Design
------
Describing a power domain tree
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
To fulfill requirement 1., the existing platform APIs
``plat_get_aff_count()`` and ``plat_get_aff_state()`` have been
removed. A platform must define an array of unsigned chars such that:
#. The first entry in the array specifies the number of power domains at the
highest power level implemented in the platform. This caters for platforms
where the power domain tree does not have a single root node, for example,
the FVP has two cluster power domains at the highest level (1).
#. Each subsequent entry corresponds to a power domain and contains the number
of power domains that are its direct children.
#. The size of the array minus the first entry will be equal to the number of
non-leaf power domains.
#. The value in each entry in the array is used to find the number of entries
to consider at the next level. The sum of the values (number of children) of
all the entries at a level specifies the number of entries in the array for
the next level.
The following example power domain topology tree will be used to describe the
above text further. The leaf and non-leaf nodes in this tree have been numbered
separately.
::
+-+
|0|
+-+
/ \
/ \
/ \
/ \
/ \
/ \
/ \
/ \
/ \
/ \
+-+ +-+
|1| |2|
+-+ +-+
/ \ / \
/ \ / \
/ \ / \
/ \ / \
+-+ +-+ +-+ +-+
|3| |4| |5| |6|
+-+ +-+ +-+ +-+
+---+-----+ +----+----| +----+----+ +----+-----+-----+
| | | | | | | | | | | | |
| | | | | | | | | | | | |
v v v v v v v v v v v v v
+-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +--+ +--+ +--+
|0| |1| |2| |3| |4| |5| |6| |7| |8| |9| |10| |11| |12|
+-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +--+ +--+ +--+
This tree is defined by the platform as the array described above as follows:
::
#define PLAT_NUM_POWER_DOMAINS 20
#define PLATFORM_CORE_COUNT 13
#define PSCI_NUM_NON_CPU_PWR_DOMAINS \
(PLAT_NUM_POWER_DOMAINS - PLATFORM_CORE_COUNT)
unsigned char plat_power_domain_tree_desc[] = { 1, 2, 2, 2, 3, 3, 3, 4};
Removing assumptions about MPIDRs used in a platform
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
To fulfill requirement 2., it is assumed that the platform assigns a
unique number (core index) between ``0`` and ``PLAT_CORE_COUNT - 1`` to each core
power domain. MPIDRs could be allocated in any manner and will not be used to
populate the tree.
``plat_core_pos_by_mpidr(mpidr)`` will return the core index for the core
corresponding to the MPIDR. It will return an error (-1) if an MPIDR is passed
which is not allocated or corresponds to an absent core. The semantics of this
platform API have changed since it is required to validate the passed MPIDR. It
has been made a mandatory API as a result.
Another mandatory API, ``plat_my_core_pos()`` has been added to return the core
index for the calling core. This API provides a more lightweight mechanism to get
the index since there is no need to validate the MPIDR of the calling core.
The platform should assign the core indices (as illustrated in the diagram above)
such that, if the core nodes are numbered from left to right, then the index
for a core domain will be the same as the index returned by
``plat_core_pos_by_mpidr()`` or ``plat_my_core_pos()`` for that core. This
relationship allows the core nodes to be allocated in a separate array
(requirement 4.) during ``psci_setup()`` in such an order that the index of the
core in the array is the same as the return value from these APIs.
Dealing with holes in MPIDR allocation
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
For platforms where the number of allocated MPIDRs is equal to the number of
core power domains, for example, Juno and FVPs, the logic to convert an MPIDR to
a core index should remain unchanged. Both Juno and FVP use a simple collision
proof hash function to do this.
It is possible that on some platforms, the allocation of MPIDRs is not
contiguous or certain cores have been disabled. This essentially means that the
MPIDRs have been sparsely allocated, that is, the size of the range of MPIDRs
used by the platform is not equal to the number of core power domains.
The platform could adopt one of the following approaches to deal with this
scenario:
#. Implement more complex logic to convert a valid MPIDR to a core index while
maintaining the relationship described earlier. This means that the power
domain tree descriptor will not describe any core power domains which are
disabled or absent. Entries will not be allocated in the tree for these
domains.
#. Treat unallocated MPIDRs and disabled cores as absent but still describe them
in the power domain descriptor, that is, the number of core nodes described
is equal to the size of the range of MPIDRs allocated. This approach will
lead to memory wastage since entries will be allocated in the tree but will
allow use of a simpler logic to convert an MPIDR to a core index.
Traversing through and distinguishing between core and non-core power domains
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
To fulfill requirement 3 and 4, separate data structures have been defined
to represent leaf and non-leaf power domain nodes in the tree.
.. code:: c
/*******************************************************************************
* The following two data structures implement the power domain tree. The tree
* is used to track the state of all the nodes i.e. power domain instances
* described by the platform. The tree consists of nodes that describe CPU power
* domains i.e. leaf nodes and all other power domains which are parents of a
* CPU power domain i.e. non-leaf nodes.
******************************************************************************/
typedef struct non_cpu_pwr_domain_node {
/*
* Index of the first CPU power domain node level 0 which has this node
* as its parent.
*/
unsigned int cpu_start_idx;
/*
* Number of CPU power domains which are siblings of the domain indexed
* by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
* -> cpu_start_idx + ncpus' have this node as their parent.
*/
unsigned int ncpus;
/* Index of the parent power domain node */
unsigned int parent_node;
-----
} non_cpu_pd_node_t;
typedef struct cpu_pwr_domain_node {
u_register_t mpidr;
/* Index of the parent power domain node */
unsigned int parent_node;
-----
} cpu_pd_node_t;
The power domain tree is implemented as a combination of the following data
structures.
::
non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS];
cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
Populating the power domain tree
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The ``populate_power_domain_tree()`` function in ``psci_setup.c`` implements the
algorithm to parse the power domain descriptor exported by the platform to
populate the two arrays. It is essentially a breadth-first-search. The nodes for
each level starting from the root are laid out one after another in the
``psci_non_cpu_pd_nodes`` and ``psci_cpu_pd_nodes`` arrays as follows:
::
psci_non_cpu_pd_nodes -> [[Level 3 nodes][Level 2 nodes][Level 1 nodes]]
psci_cpu_pd_nodes -> [Level 0 nodes]
For the example power domain tree illustrated above, the ``psci_cpu_pd_nodes``
will be populated as follows. The value in each entry is the index of the parent
node. Other fields have been ignored for simplicity.
::
+-------------+ ^
CPU0 | 3 | |
+-------------+ |
CPU1 | 3 | |
+-------------+ |
CPU2 | 3 | |
+-------------+ |
CPU3 | 4 | |
+-------------+ |
CPU4 | 4 | |
+-------------+ |
CPU5 | 4 | | PLATFORM_CORE_COUNT
+-------------+ |
CPU6 | 5 | |
+-------------+ |
CPU7 | 5 | |
+-------------+ |
CPU8 | 5 | |
+-------------+ |
CPU9 | 6 | |
+-------------+ |
CPU10 | 6 | |
+-------------+ |
CPU11 | 6 | |
+-------------+ |
CPU12 | 6 | v
+-------------+
The ``psci_non_cpu_pd_nodes`` array will be populated as follows. The value in
each entry is the index of the parent node.
::
+-------------+ ^
PD0 | -1 | |
+-------------+ |
PD1 | 0 | |
+-------------+ |
PD2 | 0 | |
+-------------+ |
PD3 | 1 | | PLAT_NUM_POWER_DOMAINS -
+-------------+ | PLATFORM_CORE_COUNT
PD4 | 1 | |
+-------------+ |
PD5 | 2 | |
+-------------+ |
PD6 | 2 | |
+-------------+ v
Each core can find its node in the ``psci_cpu_pd_nodes`` array using the
``plat_my_core_pos()`` function. When a core is turned on, the normal world
provides an MPIDR. The ``plat_core_pos_by_mpidr()`` function is used to validate
the MPIDR before using it to find the corresponding core node. The non-core power
domain nodes do not need to be identified.
--------------
*Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.*
docs/reset-design.md → docs/reset-design.rst
View file @ 7cefb56d
ARM Trusted Firmware Reset Design
=================================
1. [Introduction](#1--introduction)
2. [General reset code flow](#2--general-reset-code-flow)
3. [Programmable CPU reset address](#3--programmable-cpu-reset-address)
4. [Cold boot on a single CPU](#4--cold-boot-on-a-single-cpu)
5. [Programmable CPU reset address, Cold boot on a single CPU](#5--programmable-cpu-reset-address-cold-boot-on-a-single-cpu)
6. [Using BL31 entrypoint as the reset address](#6--using-bl31-entrypoint-as-the-reset-address)
.. section-numbering::
:suffix: .
1. Introduction
----------------
.. contents::
This document describes the high-level design of the framework to handle CPU
resets in ARM Trusted Firmware. It also describes how the platform integrator
can tailor this code to the system configuration to some extent, resulting in a
simplified and more optimised boot flow.
This document should be used in conjunction with the [Firmware Design], which
This document should be used in conjunction with the `Firmware Design`_, which
provides greater implementation details around the reset code, specifically
for the cold boot path.
2. General reset code flow
---------------------------
General reset code flow
-----------------------
The ARM Trusted Firmware (TF) reset code is implemented in BL1 by default. The
following high-level diagram illustrates this:
![Default reset code flow](diagrams/default_reset_code.png?raw=true)
|Default reset code flow|
This diagram shows the default, unoptimised reset flow. Depending on the system
configuration, some of these steps might be unnecessary. The following sections
......@@ -40,9 +34,8 @@ diagram above is still relevant, as all these operations will occur in BL31 in
this case. Please refer to section 6 "Using BL31 entrypoint as the reset
address" for more information.
3. Programmable CPU reset address
----------------------------------
Programmable CPU reset address
------------------------------
By default, the TF assumes that the CPU reset address is not programmable.
Therefore, all CPUs start at the same address (typically address 0) whenever
......@@ -50,23 +43,21 @@ they reset. Further logic is then required to identify whether it is a cold or
warm boot to direct CPUs to the right execution path.
If the reset vector address (reflected in the reset vector base address register
`RVBAR_EL3`) is programmable then it is possible to make each CPU start directly
``RVBAR_EL3``) is programmable then it is possible to make each CPU start directly
at the right address, both on a cold and warm reset. Therefore, the boot type
detection can be skipped, resulting in the following boot flow:
![Reset code flow with programmable reset address](
diagrams/reset_code_no_boot_type_check.png?raw=true)
|Reset code flow with programmable reset address|
To enable this boot flow, compile the TF with `PROGRAMMABLE_RESET_ADDRESS=1`.
To enable this boot flow, compile the TF with ``PROGRAMMABLE_RESET_ADDRESS=1``.
This option only affects the TF reset image, which is BL1 by default or BL31 if
`RESET_TO_BL31=1`.
``RESET_TO_BL31=1``.
On both the FVP and Juno platforms, the reset vector address is not programmable
so both ports use `PROGRAMMABLE_RESET_ADDRESS=0`.
so both ports use ``PROGRAMMABLE_RESET_ADDRESS=0``.
4. Cold boot on a single CPU
-----------------------------
Cold boot on a single CPU
-------------------------
By default, the TF assumes that several CPUs may be released out of reset.
Therefore, the cold boot code has to arbitrate access to hardware resources
......@@ -78,35 +69,32 @@ If the platform guarantees that only a single CPU will ever be brought up then
no arbitration is required. The notion of primary/secondary CPU itself no longer
applies. This results in the following boot flow:
![Reset code flow with single CPU released out of reset](
diagrams/reset_code_no_cpu_check.png?raw=true)
|Reset code flow with single CPU released out of reset|
To enable this boot flow, compile the TF with `COLD_BOOT_SINGLE_CPU=1`. This
To enable this boot flow, compile the TF with ``COLD_BOOT_SINGLE_CPU=1``. This
option only affects the TF reset image, which is BL1 by default or BL31 if
`RESET_TO_BL31=1`.
``RESET_TO_BL31=1``.
On both the FVP and Juno platforms, although only one core is powered up by
default, there are platform-specific ways to release any number of cores out of
reset. Therefore, both platform ports use `COLD_BOOT_SINGLE_CPU=0`.
reset. Therefore, both platform ports use ``COLD_BOOT_SINGLE_CPU=0``.
5. Programmable CPU reset address, Cold boot on a single CPU
-------------------------------------------------------------
Programmable CPU reset address, Cold boot on a single CPU
---------------------------------------------------------
It is obviously possible to combine both optimisations on platforms that have
a programmable CPU reset address and which release a single CPU out of reset.
This results in the following boot flow:
![Reset code flow with programmable reset address and single CPU released out of
reset](diagrams/reset_code_no_checks.png?raw=true)
To enable this boot flow, compile the TF with both `COLD_BOOT_SINGLE_CPU=1`
and `PROGRAMMABLE_RESET_ADDRESS=1`. These options only affect the TF reset
image, which is BL1 by default or BL31 if `RESET_TO_BL31=1`.
|Reset code flow with programmable reset address and single CPU released out of reset|
To enable this boot flow, compile the TF with both ``COLD_BOOT_SINGLE_CPU=1``
and ``PROGRAMMABLE_RESET_ADDRESS=1``. These options only affect the TF reset
image, which is BL1 by default or BL31 if ``RESET_TO_BL31=1``.
6. Using BL31 entrypoint as the reset address
----------------------------------------------
Using BL31 entrypoint as the reset address
------------------------------------------
On some platforms the runtime firmware (BL3x images) for the application
processors are loaded by some firmware running on a secure system processor
......@@ -114,11 +102,11 @@ on the SoC, rather than by BL1 and BL2 running on the primary application
processor. For this type of SoC it is desirable for the application processor
to always reset to BL31 which eliminates the need for BL1 and BL2.
TF provides a build-time option `RESET_TO_BL31` that includes some additional
TF provides a build-time option ``RESET_TO_BL31`` that includes some additional
logic in the BL31 entry point to support this use case.
In this configuration, the platform's Trusted Boot Firmware must ensure that
BL31 is loaded to its runtime address, which must match the CPU's `RVBAR_EL3`
BL31 is loaded to its runtime address, which must match the CPU's ``RVBAR_EL3``
reset vector base address, before the application processor is powered on.
Additionally, platform software is responsible for loading the other BL3x images
required and providing entry point information for them to BL31. Loading these
......@@ -126,24 +114,25 @@ images might be done by the Trusted Boot Firmware or by platform code in BL31.
Although the ARM FVP platform does not support programming the reset base
address dynamically at run-time, it is possible to set the initial value of the
`RVBAR_EL3` register at start-up. This feature is provided on the Base FVP only.
It allows the ARM FVP port to support the `RESET_TO_BL31` configuration, in
which case the `bl31.bin` image must be loaded to its run address in Trusted
SRAM and all CPU reset vectors be changed from the default `0x0` to this run
address. See the [User Guide] for details of running the FVP models in this way.
``RVBAR_EL3`` register at start-up. This feature is provided on the Base FVP only.
It allows the ARM FVP port to support the ``RESET_TO_BL31`` configuration, in
which case the ``bl31.bin`` image must be loaded to its run address in Trusted
SRAM and all CPU reset vectors be changed from the default ``0x0`` to this run
address. See the `User Guide`_ for details of running the FVP models in this way.
Although technically it would be possible to program the reset base address with
the right support in the SCP firmware, this is currently not implemented so the
Juno port doesn't support the `RESET_TO_BL31` configuration.
Juno port doesn't support the ``RESET_TO_BL31`` configuration.
The `RESET_TO_BL31` configuration requires some additions and changes in the
The ``RESET_TO_BL31`` configuration requires some additions and changes in the
BL31 functionality:
#### Determination of boot path
Determination of boot path
~~~~~~~~~~~~~~~~~~~~~~~~~~
In this configuration, BL31 uses the same reset framework and code as the one
described for BL1 above. Therefore, it is affected by the
`PROGRAMMABLE_RESET_ADDRESS` and `COLD_BOOT_SINGLE_CPU` build options in the
``PROGRAMMABLE_RESET_ADDRESS`` and ``COLD_BOOT_SINGLE_CPU`` build options in the
same way.
In the default, unoptimised BL31 reset flow, on a warm boot a CPU is directed
......@@ -151,22 +140,27 @@ to the PSCI implementation via a platform defined mechanism. On a cold boot,
the platform must place any secondary CPUs into a safe state while the primary
CPU executes a modified BL31 initialization, as described below.
#### Platform initialization
Platform initialization
~~~~~~~~~~~~~~~~~~~~~~~
In this configuration, when the CPU resets to BL31 there are no parameters that
can be passed in registers by previous boot stages. Instead, the platform code
in BL31 needs to know, or be able to determine, the location of the BL32 (if
required) and BL33 images and provide this information in response to the
`bl31_plat_get_next_image_ep_info()` function.
``bl31_plat_get_next_image_ep_info()`` function.
Additionally, platform software is responsible for carrying out any security
initialisation, for example programming a TrustZone address space controller.
This might be done by the Trusted Boot Firmware or by platform code in BL31.
- - - - - - - - - - - - - - - - - - - - - - - - - -
--------------
_Copyright (c) 2015, ARM Limited and Contributors. All rights reserved._
*Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.*
.. _Firmware Design: firmware-design.rst
.. _User Guide: user-guide.rst
[User Guide]: user-guide.md
[Firmware Design]: firmware-design.md
.. |Default reset code flow| image:: diagrams/default_reset_code.png?raw=true
.. |Reset code flow with programmable reset address| image:: diagrams/reset_code_no_boot_type_check.png?raw=true
.. |Reset code flow with single CPU released out of reset| image:: diagrams/reset_code_no_cpu_check.png?raw=true
.. |Reset code flow with programmable reset address and single CPU released out of reset| image:: diagrams/reset_code_no_checks.png?raw=true
docs/rt-svc-writers-guide.md → docs/rt-svc-writers-guide.rst
View file @ 7cefb56d
EL3 Runtime Service Writers Guide for ARM Trusted Firmware
==========================================================
Contents
--------
1. [Introduction](#1--introduction)
2. [Owning Entities, Call Types and Function IDs](#2--owning-entities-call-types-and-function-ids)
3. [Getting started](#3--getting-started)
4. [Registering a runtime service](#4--registering-a-runtime-service)
5. [Initializing a runtime service](#5-initializing-a-runtime-service)
6. [Handling runtime service requests](#6--handling-runtime-service-requests)
7. [Services that contain multiple sub-services](#7--services-that-contain-multiple-sub-services)
8. [Secure-EL1 Payload Dispatcher service (SPD)](#8--secure-el1-payload-dispatcher-service-spd)
.. section-numbering::
:suffix: .
- - - - - - - - - - - - - - - - - -
.. contents::
1. Introduction
----------------
--------------
Introduction
------------
This document describes how to add a runtime service to the EL3 Runtime
Firmware component of ARM Trusted Firmware (BL31).
......@@ -24,38 +18,39 @@ Firmware component of ARM Trusted Firmware (BL31).
Software executing in the normal world and in the trusted world at exception
levels lower than EL3 will request runtime services using the Secure Monitor
Call (SMC) instruction. These requests will follow the convention described in
the SMC Calling Convention PDD ([SMCCC]). The [SMCCC] assigns function
the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function
identifiers to each SMC request and describes how arguments are passed and
results are returned.
SMC Functions are grouped together based on the implementor of the service, for
example a subset of the Function IDs are designated as "OEM Calls" (see [SMCCC]
example a subset of the Function IDs are designated as "OEM Calls" (see `SMCCC`_
for full details). The EL3 runtime services framework in BL31 enables the
independent implementation of services for each group, which are then compiled
into the BL31 image. This simplifies the integration of common software from
ARM to support [PSCI], Secure Monitor for a Trusted OS and SoC specific
ARM to support `PSCI`_, Secure Monitor for a Trusted OS and SoC specific
software. The common runtime services framework ensures that SMC Functions are
dispatched to their respective service implementation - the [Firmware Design]
dispatched to their respective service implementation - the `Firmware Design`_
provides details of how this is achieved.
The interface and operation of the runtime services depends heavily on the
concepts and definitions described in the [SMCCC], in particular SMC Function
concepts and definitions described in the `SMCCC`_, in particular SMC Function
IDs, Owning Entity Numbers (OEN), Fast and Standard calls, and the SMC32 and
SMC64 calling conventions. Please refer to that document for a full explanation
of these terms.
2. Owning Entities, Call Types and Function IDs
------------------------------------------------
Owning Entities, Call Types and Function IDs
--------------------------------------------
The SMC Function Identifier includes a OEN field. These values and their
meaning are described in [SMCCC] and summarized in table 1 below. Some entities
meaning are described in `SMCCC`_ and summarized in table 1 below. Some entities
are allocated a range of of OENs. The OEN must be interpreted in conjunction
with the SMC call type, which is either _Fast_ or _Yielding_. Fast calls are
with the SMC call type, which is either *Fast* or *Yielding*. Fast calls are
uninterruptible whereas Yielding calls can be pre-empted. The majority of
Owning Entities only have allocated ranges for Fast calls: Yielding calls are
reserved exclusively for Trusted OS providers or for interoperability with
legacy 32-bit software that predates the [SMCCC].
legacy 32-bit software that predates the `SMCCC`_.
::
Type OEN Service
Fast 0 ARM Architecture calls
......@@ -70,14 +65,14 @@ legacy 32-bit software that predates the [SMCCC].
Yielding 0- 1 Reserved for existing ARMv7 calls
Yielding 2-63 Trusted OS Standard Calls
_Table 1: Service types and their corresponding Owning Entity Numbers_
*Table 1: Service types and their corresponding Owning Entity Numbers*
Each individual entity can allocate the valid identifiers within the entity
range as they need - it is not necessary to coordinate with other entities of
the same type. For example, two SoC providers can use the same Function ID
within the SiP Service calls OEN range to mean different things - as these
calls should be specific to the SoC. The Standard Runtime Calls OEN is used for
services defined by ARM standards, such as [PSCI].
services defined by ARM standards, such as `PSCI`_.
The SMC Function ID also indicates whether the call has followed the SMC32
calling convention, where all parameters are 32-bit, or the SMC64 calling
......@@ -89,39 +84,43 @@ The EL3 runtime services framework uses the call type and OEN to identify a
specific handler for each SMC call, but it is expected that an individual
handler will be responsible for all SMC Functions within a given service type.
Getting started
---------------
3. Getting started
-------------------
ARM Trusted Firmware has a [`services`] directory in the source tree under which
ARM Trusted Firmware has a `services`_ directory in the source tree under which
each owning entity can place the implementation of its runtime service. The
[PSCI] implementation is located here in the [`lib/psci`] directory.
`PSCI`_ implementation is located here in the `lib/psci`_ directory.
Runtime service sources will need to include the [`runtime_svc.h`] header file.
Runtime service sources will need to include the `runtime\_svc.h`_ header file.
Registering a runtime service
-----------------------------
4. Registering a runtime service
---------------------------------
A runtime service is registered using the `DECLARE_RT_SVC()` macro, specifying
A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying
the name of the service, the range of OENs covered, the type of service and
initialization and call handler functions.
::
#define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch)
* `_name` is used to identify the data structure declared by this macro, and
- ``_name`` is used to identify the data structure declared by this macro, and
is also used for diagnostic purposes
* `_start` and `_end` values must be based on the `OEN_*` values defined in
[`smcc.h`]
- ``_start`` and ``_end`` values must be based on the ``OEN_*`` values defined in
`smcc.h`_
* `_type` must be one of `SMC_TYPE_FAST` or `SMC_TYPE_YIELD`
- ``_type`` must be one of ``SMC_TYPE_FAST`` or ``SMC_TYPE_YIELD``
* `_setup` is the initialization function with the `rt_svc_init` signature:
- ``_setup`` is the initialization function with the ``rt_svc_init`` signature:
.. code:: c
typedef int32_t (*rt_svc_init)(void);
* `_smch` is the SMC handler function with the `rt_svc_handle` signature:
- ``_smch`` is the SMC handler function with the ``rt_svc_handle`` signature:
.. code:: c
typedef uintptr_t (*rt_svc_handle_t)(uint32_t smc_fid,
u_register_t x1, u_register_t x2,
......@@ -136,12 +135,14 @@ the following sections.
During initialization the services framework validates each declared service
to ensure that the following conditions are met:
1. The `_start` OEN is not greater than the `_end` OEN
2. The `_end` OEN does not exceed the maximum OEN value (63)
3. The `_type` is one of `SMC_TYPE_FAST` or `SMC_TYPE_YIELD`
4. `_setup` and `_smch` routines have been specified
#. The ``_start`` OEN is not greater than the ``_end`` OEN
#. The ``_end`` OEN does not exceed the maximum OEN value (63)
#. The ``_type`` is one of ``SMC_TYPE_FAST`` or ``SMC_TYPE_YIELD``
#. ``_setup`` and ``_smch`` routines have been specified
`std\_svc\_setup.c`_ provides an example of registering a runtime service:
[`std_svc_setup.c`] provides an example of registering a runtime service:
.. code:: c
/* Register Standard Service Calls as runtime service */
DECLARE_RT_SVC(
......@@ -153,25 +154,26 @@ to ensure that the following conditions are met:
std_svc_smc_handler
);
5. Initializing a runtime service
---------------------------------
Initializing a runtime service
------------------------------
Runtime services are initialized once, during cold boot, by the primary CPU
after platform and architectural initialization is complete. The framework
performs basic validation of the declared service before calling
the service initialization function (`_setup` in the declaration). This
the service initialization function (``_setup`` in the declaration). This
function must carry out any essential EL3 initialization prior to receiving a
SMC Function call via the handler function.
On success, the initialization function must return `0`. Any other return value
On success, the initialization function must return ``0``. Any other return value
will cause the framework to issue a diagnostic:
::
Error initializing runtime service <name of the service>
and then ignore the service - the system will continue to boot but SMC calls
will not be passed to the service handler and instead return the _Unknown SMC
Function ID_ result `0xFFFFFFFF`.
will not be passed to the service handler and instead return the *Unknown SMC
Function ID* result ``0xFFFFFFFF``.
If the system must not be allowed to proceed without the service, the
initialization function must itself cause the firmware boot to be halted.
......@@ -180,14 +182,15 @@ If the service uses per-CPU data this must either be initialized for all CPUs
during this call, or be done lazily when a CPU first issues an SMC call to that
service.
6. Handling runtime service requests
-------------------------------------
Handling runtime service requests
---------------------------------
SMC calls for a service are forwarded by the framework to the service's SMC
handler function (`_smch` in the service declaration). This function must have
handler function (``_smch`` in the service declaration). This function must have
the following signature:
.. code:: c
typedef uintptr_t (*rt_svc_handle_t)(uint32_t smc_fid,
u_register_t x1, u_register_t x2,
u_register_t x3, u_register_t x4,
......@@ -197,27 +200,33 @@ the following signature:
The handler is responsible for:
1. Determining that `smc_fid` is a valid and supported SMC Function ID,
otherwise completing the request with the _Unknown SMC Function ID_:
#. Determining that ``smc_fid`` is a valid and supported SMC Function ID,
otherwise completing the request with the *Unknown SMC Function ID*:
.. code:: c
SMC_RET1(handle, SMC_UNK);
2. Determining if the requested function is valid for the calling security
#. Determining if the requested function is valid for the calling security
state. SMC Calls can be made from both the normal and trusted worlds and
the framework will forward all calls to the service handler.
The `flags` parameter to this function indicates the caller security state
in bit[0], where a value of `1` indicates a non-secure caller. The
`is_caller_secure(flags)` and `is_caller_non_secure(flags)` can be used to
The ``flags`` parameter to this function indicates the caller security state
in bit[0], where a value of ``1`` indicates a non-secure caller. The
``is_caller_secure(flags)`` and ``is_caller_non_secure(flags)`` can be used to
test this condition.
If invalid, the request should be completed with:
.. code:: c
SMC_RET1(handle, SMC_UNK);
3. Truncating parameters for calls made using the SMC32 calling convention.
#. Truncating parameters for calls made using the SMC32 calling convention.
Such calls can be determined by checking the CC field in bit[30] of the
`smc_fid` parameter, for example by using:
``smc_fid`` parameter, for example by using:
::
if (GET_SMC_CC(smc_fid) == SMC_32) ...
......@@ -227,47 +236,50 @@ The handler is responsible for:
integer type before use, for example by ensuring that functions defined
to handle individual SMC Functions use appropriate 32-bit parameters.
4. Providing the service requested by the SMC Function, utilizing the
#. Providing the service requested by the SMC Function, utilizing the
immediate parameters x1-x4 and/or the additional saved parameters X5-X7.
The latter can be retrieved using the `SMC_GET_GP(handle, ref)` function,
supplying the appropriate `CTX_GPREG_Xn` reference, e.g.
The latter can be retrieved using the ``SMC_GET_GP(handle, ref)`` function,
supplying the appropriate ``CTX_GPREG_Xn`` reference, e.g.
.. code:: c
uint64_t x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
5. Implementing the standard SMC32 Functions that provide information about
#. Implementing the standard SMC32 Functions that provide information about
the implementation of the service. These are the Call Count, Implementor
UID and Revision Details for each service documented in section 6 of the
[SMCCC].
`SMCCC`_.
The ARM Trusted Firmware expects owning entities to follow this
recommendation.
5. Returning the result to the caller. The [SMCCC] allows for up to 256 bits
#. Returning the result to the caller. The `SMCCC`_ allows for up to 256 bits
of return value in SMC64 using X0-X3 and 128 bits in SMC32 using W0-W3. The
framework provides a family of macros to set the multi-register return
value and complete the handler:
.. code:: c
SMC_RET1(handle, x0);
SMC_RET2(handle, x0, x1);
SMC_RET3(handle, x0, x1, x2);
SMC_RET4(handle, x0, x1, x2, x3);
The `cookie` parameter to the handler is reserved for future use and can be
ignored. The `handle` is returned by the SMC handler - completion of the
handler function must always be via one of the `SMC_RETn()` macros.
The ``cookie`` parameter to the handler is reserved for future use and can be
ignored. The ``handle`` is returned by the SMC handler - completion of the
handler function must always be via one of the ``SMC_RETn()`` macros.
NOTE: The PSCI and Test Secure-EL1 Payload Dispatcher services do not follow
all of the above requirements yet.
7. Services that contain multiple sub-services
-----------------------------------------------
Services that contain multiple sub-services
-------------------------------------------
It is possible that a single owning entity implements multiple sub-services. For
example, the Standard calls service handles `0x84000000`-`0x8400FFFF` and
`0xC4000000`-`0xC400FFFF` functions. Within that range, the [PSCI] service
handles the `0x84000000`-`0x8400001F` and `0xC4000000`-`0xC400001F` functions.
In that respect, [PSCI] is a 'sub-service' of the Standard calls service. In
example, the Standard calls service handles ``0x84000000``-``0x8400FFFF`` and
``0xC4000000``-``0xC400FFFF`` functions. Within that range, the `PSCI`_ service
handles the ``0x84000000``-``0x8400001F`` and ``0xC4000000``-``0xC400001F`` functions.
In that respect, `PSCI`_ is a 'sub-service' of the Standard calls service. In
future, there could be additional such sub-services in the Standard calls
service which perform independent functions.
......@@ -277,13 +289,12 @@ very similar to the current runtime services framework, but using a different
part of the SMC Function ID to identify the sub-service. Trusted Firmware does
not provide such a framework at present.
8. Secure-EL1 Payload Dispatcher service (SPD)
-----------------------------------------------
Secure-EL1 Payload Dispatcher service (SPD)
-------------------------------------------
Services that handle SMC Functions targeting a Trusted OS, Trusted Application,
or other Secure-EL1 Payload are special. These services need to manage the
Secure-EL1 context, provide the _Secure Monitor_ functionality of switching
Secure-EL1 context, provide the *Secure Monitor* functionality of switching
between the normal and secure worlds, deliver SMC Calls through to Secure-EL1
and generally manage the Secure-EL1 Payload through CPU power-state transitions.
......@@ -291,17 +302,15 @@ TODO: Provide details of the additional work required to implement a SPD and
the BL31 support for these services. Or a reference to the document that will
provide this information....
--------------
- - - - - - - - - - - - - - - - - - - - - - - - - -
_Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved._
*Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.*
[Firmware Design]: ./firmware-design.md
[`services`]: ../services
[`lib/psci`]: ../lib/psci
[`std_svc_setup.c`]: ../services/std_svc/std_svc_setup.c
[`runtime_svc.h`]: ../include/common/runtime_svc.h
[`smcc.h`]: ../include/lib/smcc.h
[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf "Power State Coordination Interface PDD (ARM DEN 0022C)"
[SMCCC]: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html "SMC Calling Convention PDD (ARM DEN 0028A)"
.. _SMCCC: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
.. _Firmware Design: ./firmware-design.rst
.. _services: ../services
.. _lib/psci: ../lib/psci
.. _runtime\_svc.h: ../include/common/runtime_svc.h
.. _smcc.h: ../include/lib/smcc.h
.. _std\_svc\_setup.c: ../services/std_svc/std_svc_setup.c
docs/spd/optee-dispatcher.md deleted 100644 → 0
View file @ aa5b843f
OP-TEE Dispatcher
=================
[OP-TEE OS] is a Trusted OS running as Secure EL1.
To build and execute [OP-TEE OS] follow the instructions at
[ARM Trusted Firmware with OP-TEE] [OP-TEE OS]
- - - - - - - - - - - - - - - - - - - - - - - - - -
_Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._
[OP-TEE OS]: http://github.com/OP-TEE/optee_os/tree/master/documentation/arm_trusted_firmware.md
docs/spd/optee-dispatcher.rst 0 → 100644
View file @ 7cefb56d
OP-TEE Dispatcher
=================
`OP-TEE OS`_ is a Trusted OS running as Secure EL1.
To build and execute OP-TEE follow the instructions at
`OP-TEE build.git`_
--------------
*Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.*
.. _OP-TEE OS: https://github.com/OP-TEE/build
.. _OP-TEE build.git: https://github.com/OP-TEE/build
docs/spd/tlk-dispatcher.md → docs/spd/tlk-dispatcher.rst
View file @ 7cefb56d
Trusted Little Kernel (TLK) Dispatcher
=======================================
======================================
TLK dispatcher adds support for NVIDIA's Trusted Little Kernel (TLK) to work
with the Trusted Firmware. TLK-D can be compiled by including it in the
platform's makefile. TLK is primarily meant to work with Tegra SoCs, so until
......@@ -15,6 +16,7 @@ to the build command.
Trusted Little Kernel (TLK)
===========================
TLK is a Trusted OS running as Secure EL1. It is a Free Open Source Software
(FOSS) release of the NVIDIA® Trusted Little Kernel (TLK) technology, which
extends technology made available with the development of the Little Kernel (LK).
......@@ -47,24 +49,28 @@ NVIDIA extensions to Little Kernel (LK) include:
• Debugging support over UART (USB planned)
TLK is hosted by NVIDIA on http://nv-tegra.nvidia.com under the
3rdparty/ote_partner/tlk.git repository. Detailed information about
TLK and OTE can be found in the Tegra_BSP_for_Android_TLK_FOSS_Reference.pdf
manual located under the "documentation" directory_.
3rdparty/ote\_partner/tlk.git repository. Detailed information about
TLK and OTE can be found in the Tegra\_BSP\_for\_Android\_TLK\_FOSS\_Reference.pdf
manual located under the "documentation" directory\_.
Build TLK
=========
To build and execute TLK, follow the instructions from "Building a TLK Device"
section from Tegra_BSP_for_Android_TLK_FOSS_Reference.pdf manual.
section from Tegra\_BSP\_for\_Android\_TLK\_FOSS\_Reference.pdf manual.
Input parameters to TLK
=======================
TLK expects the TZDRAM size and a structure containing the boot arguments. BL2
passes this information to the EL3 software as members of the bl32_ep_info
struct, where bl32_ep_info is part of bl31_params_t (passed by BL2 in X0)
passes this information to the EL3 software as members of the bl32\_ep\_info
struct, where bl32\_ep\_info is part of bl31\_params\_t (passed by BL2 in X0)
Example:
--------
::
bl32_ep_info->args.arg0 = TZDRAM size available for BL32
bl32_ep_info->args.arg1 = unused (used only on ARMv7)
bl32_ep_info->args.arg2 = pointer to boot args
docs/spd/trusty-dispatcher.md → docs/spd/trusty-dispatcher.rst
View file @ 7cefb56d
Trusty Dispatcher
=================
Trusty is a a set of software components, supporting a Trusted Execution
Environment (TEE) on mobile devices, published and maintained by Google.
......@@ -9,7 +10,6 @@ https://source.android.com/security/trusty
Supported platforms
===================
Out of all the platforms supported by the ARM Trusted Firmware, Trusty is
verified and supported by NVIDIA's Tegra SoCs.
docs/trusted-board-boot.md → docs/trusted-board-boot.rst
View file @ 7cefb56d
Trusted Board Boot Design Guide
===============================
Contents :
1. [Introduction](#1--introduction)
2. [Chain of Trust](#2--chain-of-trust)
3. [Trusted Board Boot Sequence](#3--trusted-board-boot-sequence)
4. [Authentication Framework](#4--authentication-framework)
5. [Certificate Generation Tool](#5--certificate-generation-tool)
.. section-numbering::
:suffix: .
1. Introduction
----------------
.. contents::
The Trusted Board Boot (TBB) feature prevents malicious firmware from running on
the platform by authenticating all firmware images up to and including the
......@@ -20,24 +14,23 @@ Public-Key-Cryptography Standards (PKCS).
This document describes the design of ARM Trusted Firmware TBB, which is an
implementation of the Trusted Board Boot Requirements (TBBR) specification,
ARM DEN0006C-1. It should be used in conjunction with the [Firmware Update]
ARM DEN0006C-1. It should be used in conjunction with the `Firmware Update`_
design document, which implements a specific aspect of the TBBR.
2. Chain of Trust
------------------
Chain of Trust
--------------
A Chain of Trust (CoT) starts with a set of implicitly trusted components. On
the ARM development platforms, these components are:
* A SHA-256 hash of the Root of Trust Public Key (ROTPK). It is stored in the
- A SHA-256 hash of the Root of Trust Public Key (ROTPK). It is stored in the
trusted root-key storage registers.
* The BL1 image, on the assumption that it resides in ROM so cannot be
- The BL1 image, on the assumption that it resides in ROM so cannot be
tampered with.
The remaining components in the CoT are either certificates or boot loader
images. The certificates follow the [X.509 v3] standard. This standard
images. The certificates follow the `X.509 v3`_ standard. This standard
enables adding custom extensions to the certificates, which are used to store
essential information to establish the CoT.
......@@ -54,103 +47,102 @@ certificates. Content certificates are used to store the hash of a boot loader
image. An image can be authenticated by calculating its hash and matching it
with the hash extracted from the content certificate. The SHA-256 function is
used to calculate all hashes. The public keys and hashes are included as
non-standard extension fields in the [X.509 v3] certificates.
non-standard extension fields in the `X.509 v3`_ certificates.
The keys used to establish the CoT are:
* **Root of trust key**
- **Root of trust key**
The private part of this key is used to sign the BL2 content certificate and
the trusted key certificate. The public part is the ROTPK.
* **Trusted world key**
- **Trusted world key**
The private part is used to sign the key certificates corresponding to the
secure world images (SCP_BL2, BL31 and BL32). The public part is stored in
secure world images (SCP\_BL2, BL31 and BL32). The public part is stored in
one of the extension fields in the trusted world certificate.
* **Non-trusted world key**
- **Non-trusted world key**
The private part is used to sign the key certificate corresponding to the
non secure world image (BL33). The public part is stored in one of the
extension fields in the trusted world certificate.
* **BL3-X keys**
- **BL3-X keys**
For each of SCP_BL2, BL31, BL32 and BL33, the private part is used to
For each of SCP\_BL2, BL31, BL32 and BL33, the private part is used to
sign the content certificate for the BL3-X image. The public part is stored
in one of the extension fields in the corresponding key certificate.
The following images are included in the CoT:
* BL1
* BL2
* SCP_BL2 (optional)
* BL31
* BL33
* BL32 (optional)
- BL1
- BL2
- SCP\_BL2 (optional)
- BL31
- BL33
- BL32 (optional)
The following certificates are used to authenticate the images.
* **BL2 content certificate**
- **BL2 content certificate**
It is self-signed with the private part of the ROT key. It contains a hash
of the BL2 image.
* **Trusted key certificate**
- **Trusted key certificate**
It is self-signed with the private part of the ROT key. It contains the
public part of the trusted world key and the public part of the non-trusted
world key.
* **SCP_BL2 key certificate**
- **SCP\_BL2 key certificate**
It is self-signed with the trusted world key. It contains the public part of
the SCP_BL2 key.
the SCP\_BL2 key.
* **SCP_BL2 content certificate**
- **SCP\_BL2 content certificate**
It is self-signed with the SCP_BL2 key. It contains a hash of the SCP_BL2
It is self-signed with the SCP\_BL2 key. It contains a hash of the SCP\_BL2
image.
* **BL31 key certificate**
- **BL31 key certificate**
It is self-signed with the trusted world key. It contains the public part of
the BL31 key.
* **BL31 content certificate**
- **BL31 content certificate**
It is self-signed with the BL31 key. It contains a hash of the BL31 image.
* **BL32 key certificate**
- **BL32 key certificate**
It is self-signed with the trusted world key. It contains the public part of
the BL32 key.
* **BL32 content certificate**
- **BL32 content certificate**
It is self-signed with the BL32 key. It contains a hash of the BL32 image.
* **BL33 key certificate**
- **BL33 key certificate**
It is self-signed with the non-trusted world key. It contains the public
part of the BL33 key.
* **BL33 content certificate**
- **BL33 content certificate**
It is self-signed with the BL33 key. It contains a hash of the BL33 image.
The SCP_BL2 and BL32 certificates are optional, but they must be present if the
corresponding SCP_BL2 or BL32 images are present.
The SCP\_BL2 and BL32 certificates are optional, but they must be present if the
corresponding SCP\_BL2 or BL32 images are present.
3. Trusted Board Boot Sequence
-------------------------------
Trusted Board Boot Sequence
---------------------------
The CoT is verified through the following sequence of steps. The system panics
if any of the steps fail.
* BL1 loads and verifies the BL2 content certificate. The issuer public key is
- BL1 loads and verifies the BL2 content certificate. The issuer public key is
read from the verified certificate. A hash of that key is calculated and
compared with the hash of the ROTPK read from the trusted root-key storage
registers. If they match, the BL2 hash is read from the certificate.
......@@ -158,48 +150,48 @@ if any of the steps fail.
Note: the matching operation is platform specific and is currently
unimplemented on the ARM development platforms.
* BL1 loads the BL2 image. Its hash is calculated and compared with the hash
- BL1 loads the BL2 image. Its hash is calculated and compared with the hash
read from the certificate. Control is transferred to the BL2 image if all
the comparisons succeed.
* BL2 loads and verifies the trusted key certificate. The issuer public key is
- BL2 loads and verifies the trusted key certificate. The issuer public key is
read from the verified certificate. A hash of that key is calculated and
compared with the hash of the ROTPK read from the trusted root-key storage
registers. If the comparison succeeds, BL2 reads and saves the trusted and
non-trusted world public keys from the verified certificate.
The next two steps are executed for each of the SCP_BL2, BL31 & BL32 images.
The steps for the optional SCP_BL2 and BL32 images are skipped if these images
The next two steps are executed for each of the SCP\_BL2, BL31 & BL32 images.
The steps for the optional SCP\_BL2 and BL32 images are skipped if these images
are not present.
* BL2 loads and verifies the BL3x key certificate. The certificate signature
- BL2 loads and verifies the BL3x key certificate. The certificate signature
is verified using the trusted world public key. If the signature
verification succeeds, BL2 reads and saves the BL3x public key from the
certificate.
* BL2 loads and verifies the BL3x content certificate. The signature is
- BL2 loads and verifies the BL3x content certificate. The signature is
verified using the BL3x public key. If the signature verification succeeds,
BL2 reads and saves the BL3x image hash from the certificate.
The next two steps are executed only for the BL33 image.
* BL2 loads and verifies the BL33 key certificate. If the signature
- BL2 loads and verifies the BL33 key certificate. If the signature
verification succeeds, BL2 reads and saves the BL33 public key from the
certificate.
* BL2 loads and verifies the BL33 content certificate. If the signature
- BL2 loads and verifies the BL33 content certificate. If the signature
verification succeeds, BL2 reads and saves the BL33 image hash from the
certificate.
The next step is executed for all the boot loader images.
* BL2 calculates the hash of each image. It compares it with the hash obtained
- BL2 calculates the hash of each image. It compares it with the hash obtained
from the corresponding content certificate. The image authentication succeeds
if the hashes match.
The Trusted Board Boot implementation spans both generic and platform-specific
BL1 and BL2 code, and in tool code on the host build machine. The feature is
enabled through use of specific build flags as described in the [User Guide].
enabled through use of specific build flags as described in the `User Guide`_.
On the host machine, a tool generates the certificates, which are included in
the FIP along with the boot loader images. These certificates are loaded in
......@@ -209,43 +201,38 @@ Authentication module included in the Trusted Firmware.
The mechanism used for generating the FIP and the Authentication module are
described in the following sections.
4. Authentication Framework
----------------------------
Authentication Framework
------------------------
The authentication framework included in the Trusted Firmware provides support
to implement the desired trusted boot sequence. ARM platforms use this framework
to implement the boot requirements specified in the TBBR-client document.
More information about the authentication framework can be found in the
[Auth Framework] document.
`Auth Framework`_ document.
Certificate Generation Tool
---------------------------
5. Certificate Generation Tool
-------------------------------
The `cert_create` tool is built and runs on the host machine as part of the
Trusted Firmware build process when `GENERATE_COT=1`. It takes the boot loader
The ``cert_create`` tool is built and runs on the host machine as part of the
Trusted Firmware build process when ``GENERATE_COT=1``. It takes the boot loader
images and keys as inputs (keys must be in PEM format) and generates the
certificates (in DER format) required to establish the CoT. New keys can be
generated by the tool in case they are not provided. The certificates are then
passed as inputs to the `fiptool` utility for creating the FIP.
passed as inputs to the ``fiptool`` utility for creating the FIP.
The certificates are also stored individually in the in the output build
directory.
The tool resides in the `tools/cert_create` directory. It uses OpenSSL SSL
The tool resides in the ``tools/cert_create`` directory. It uses OpenSSL SSL
library version 1.0.1 or later to generate the X.509 certificates. Instructions
for building and using the tool can be found in the [User Guide].
- - - - - - - - - - - - - - - - - - - - - - - - - -
for building and using the tool can be found in the `User Guide`_.
_Copyright (c) 2015, ARM Limited and Contributors. All rights reserved._
--------------
*Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.*
[X.509 v3]: http://www.ietf.org/rfc/rfc5280.txt
[X.690]: http://www.itu.int/ITU-T/studygroups/com17/languages/X.690-0207.pdf
[Auth Framework]: auth-framework.md
[User Guide]: user-guide.md
[Firmware Update]: firmware-update.md
.. _Firmware Update: firmware-update.rst
.. _X.509 v3: http://www.ietf.org/rfc/rfc5280.txt
.. _User Guide: user-guide.rst
.. _Auth Framework: auth-framework.rst
docs/user-guide.md → docs/user-guide.rst
View file @ 7cefb56d
ARM Trusted Firmware User Guide
===============================
Contents :
1. [Introduction](#1--introduction)
2. [Host machine requirements](#2--host-machine-requirements)
3. [Tools](#3--tools)
4. [Getting the Trusted Firmware source code](#4--getting-the-trusted-firmware-source-code)
5. [Building the Trusted Firmware](#5--building-the-trusted-firmware)
6. [Building a FIP for Juno and FVP](#6--building-a-fip-for-juno-and-fvp)
7. [EL3 payloads alternative boot flow](#7--el3-payloads-alternative-boot-flow)
8. [Preloaded BL33 alternative boot flow](#8--preloaded-bl33-alternative-boot-flow)
9. [Running the software on FVP](#9--running-the-software-on-fvp)
10. [Running the software on Juno](#10--running-the-software-on-juno)
.. section-numbering::
:suffix: .
1. Introduction
----------------
.. contents::
This document describes how to build ARM Trusted Firmware (TF) and run it with a
tested set of other software components using defined configurations on the Juno
......@@ -26,16 +15,15 @@ is outside the scope of this document.
This document assumes that the reader has previous experience running a fully
bootable Linux software stack on Juno or FVP using the prebuilt binaries and
filesystems provided by [Linaro][Linaro Release Notes]. Further information may
be found in the [Instructions for using the Linaro software deliverables]
[Linaro SW Instructions]. It also assumes that the user understands the role of
filesystems provided by `Linaro`_. Further information may
be found in the `Instructions for using the Linaro software deliverables`_. It also assumes that the user understands the role of
the different software components required to boot a Linux system:
* Specific firmware images required by the platform (e.g. SCP firmware on Juno)
* Normal world bootloader (e.g. UEFI or U-Boot)
* Device tree
* Linux kernel image
* Root filesystem
- Specific firmware images required by the platform (e.g. SCP firmware on Juno)
- Normal world bootloader (e.g. UEFI or U-Boot)
- Device tree
- Linux kernel image
- Root filesystem
Note: the ARM TF v1.3 release was tested with Linaro Release 16.06, and the
latest version of ARM TF is tested with Linaro Release 17.01.
......@@ -43,11 +31,10 @@ latest version of ARM TF is tested with Linaro Release 17.01.
This document also assumes that the user is familiar with the FVP models and
the different command line options available to launch the model.
This document should be used in conjunction with the [Firmware Design].
This document should be used in conjunction with the `Firmware Design`_.
2. Host machine requirements
-----------------------------
Host machine requirements
-------------------------
The minimum recommended machine specification for building the software and
running the FVP models is a dual-core processor running at 2GHz with 12GB of
......@@ -61,133 +48,151 @@ specified.
The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
Cygwin, and Msys (MinGW) shells, using version 4.9.1 of the GNU toolchain.
3. Tools
---------
Tools
-----
Install the required packages to build Trusted Firmware with the following
command:
::
sudo apt-get install build-essential gcc make git libssl-dev
Download and install the AArch32 or AArch64 little-endian GCC cross compiler.
The [Linaro Release Notes][Linaro Release Notes] documents which version of the
The `Linaro Release Notes`_ documents which version of the
compiler to use for a given Linaro Release. Also, these
[Linaro instructions][Linaro SW Instructions] provide further guidance.
`Linaro instructions`_ provide further guidance.
Optionally, Trusted Firmware can be built using clang or ARM Compiler 6.
See instructions below on how to switch the default compiler.
In addition, the following optional packages and tools may be needed:
* `device-tree-compiler` package if you need to rebuild the Flattened Device
Tree (FDT) source files (`.dts` files) provided with this software.
* For debugging, ARM [Development Studio 5 (DS-5)][DS-5].
- ``device-tree-compiler`` package if you need to rebuild the Flattened Device
Tree (FDT) source files (``.dts`` files) provided with this software.
- For debugging, ARM `Development Studio 5 (DS-5)`_.
4. Getting the Trusted Firmware source code
--------------------------------------------
Getting the Trusted Firmware source code
----------------------------------------
Download the Trusted Firmware source code from Github:
git clone https://github.com/ARM-software/arm-trusted-firmware.git
::
git clone https://github.com/ARM-software/arm-trusted-firmware.git
5. Building the Trusted Firmware
---------------------------------
Building the Trusted Firmware
-----------------------------
* Before building Trusted Firmware, the environment variable `CROSS_COMPILE`
- Before building Trusted Firmware, the environment variable ``CROSS_COMPILE``
must point to the Linaro cross compiler.
For AArch64:
::
export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
For AArch32:
::
export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
It is possible to build Trusted Firmware using clang or ARM Compiler 6.
To do so `CC` needs to point to the clang or armclang binary. Only the
To do so ``CC`` needs to point to the clang or armclang binary. Only the
compiler is switched; the assembler and linker need to be provided by
the GNU toolchain, thus `CROSS_COMPILE` should be set as described above.
the GNU toolchain, thus ``CROSS_COMPILE`` should be set as described above.
ARM Compiler 6 will be selected when the base name of the path assigned
to `CC` matches the string 'armclang'.
to ``CC`` matches the string 'armclang'.
For AArch64 using ARM Compiler 6:
::
export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
Clang will be selected when the base name of the path assigned to `CC`
Clang will be selected when the base name of the path assigned to ``CC``
contains the string 'clang'. This is to allow both clang and clang-X.Y
to work.
For AArch64 using clang:
::
export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
make CC=<path-to-clang>/bin/clang PLAT=<platform> all
* Change to the root directory of the Trusted Firmware source tree and build.
- Change to the root directory of the Trusted Firmware source tree and build.
For AArch64:
::
make PLAT=<platform> all
For AArch32:
make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
::
make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
Notes:
* If `PLAT` is not specified, `fvp` is assumed by default. See the
"Summary of build options" for more information on available build
- If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
`Summary of build options`_ for more information on available build
options.
* (AArch32 only) Currently only `PLAT=fvp` is supported.
- (AArch32 only) Currently only ``PLAT=fvp`` is supported.
* (AArch32 only) `AARCH32_SP` is the AArch32 EL3 Runtime Software and it
corresponds to the BL32 image. A minimal `AARCH32_SP`, sp_min, is
- (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp\_min, is
provided by ARM Trusted Firmware to demonstrate how PSCI Library can
be integrated with an AArch32 EL3 Runtime Software. Some AArch32 EL3
Runtime Software may include other runtime services, for example
Trusted OS services. A guide to integrate PSCI library with AArch32
EL3 Runtime Software can be found [here][PSCI Lib Integration].
EL3 Runtime Software can be found `here`_.
* (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
image, is not compiled in by default. Refer to the "Building the Test
Secure Payload" section below.
- (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
image, is not compiled in by default. Refer to the
`Building the Test Secure Payload`_ section below.
* By default this produces a release version of the build. To produce a
- By default this produces a release version of the build. To produce a
debug version instead, refer to the "Debugging options" section below.
* The build process creates products in a `build` directory tree, building
- The build process creates products in a ``build`` directory tree, building
the objects and binaries for each boot loader stage in separate
sub-directories. The following boot loader binary files are created
from the corresponding ELF files:
* `build/<platform>/<build-type>/bl1.bin`
* `build/<platform>/<build-type>/bl2.bin`
* `build/<platform>/<build-type>/bl31.bin` (AArch64 only)
* `build/<platform>/<build-type>/bl32.bin` (mandatory for AArch32)
- ``build/<platform>/<build-type>/bl1.bin``
- ``build/<platform>/<build-type>/bl2.bin``
- ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
- ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
where `<platform>` is the name of the chosen platform and `<build-type>`
is either `debug` or `release`. The actual number of images might differ
where ``<platform>`` is the name of the chosen platform and ``<build-type>``
is either ``debug`` or ``release``. The actual number of images might differ
depending on the platform.
* Build products for a specific build variant can be removed using:
- Build products for a specific build variant can be removed using:
::
make DEBUG=<D> PLAT=<platform> clean
... where `<D>` is `0` or `1`, as specified when building.
... where ``<D>`` is ``0`` or ``1``, as specified when building.
The build tree can be removed completely using:
::
make realclean
### Summary of build options
Summary of build options
~~~~~~~~~~~~~~~~~~~~~~~~
ARM Trusted Firmware build system supports the following build options. Unless
mentioned otherwise, these options are expected to be specified at the build
......@@ -196,183 +201,184 @@ the build system doesn't track dependency for build options. Therefore, if any
of the build options are changed from a previous build, a clean build must be
performed.
#### Common build options
Common build options
^^^^^^^^^^^^^^^^^^^^
* `AARCH32_SP` : Choose the AArch32 Secure Payload component to be built as
as the BL32 image when `ARCH=aarch32`. The value should be the path to the
directory containing the SP source, relative to the `bl32/`; the directory
is expected to contain a makefile called `<aarch32_sp-value>.mk`.
- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
directory containing the SP source, relative to the ``bl32/``; the directory
is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
* `ARCH` : Choose the target build architecture for ARM Trusted Firmware.
It can take either `aarch64` or `aarch32` as values. By default, it is
defined to `aarch64`.
- ``ARCH`` : Choose the target build architecture for ARM Trusted Firmware.
It can take either ``aarch64`` or ``aarch32`` as values. By default, it is
defined to ``aarch64``.
* `ARM_CCI_PRODUCT_ID`: Choice of ARM CCI product used by the platform. This
- ``ARM_CCI_PRODUCT_ID``: Choice of ARM CCI product used by the platform. This
is used to determine the number of valid slave interfaces available in the
ARM CCI driver. Default is 400 (that is, CCI-400).
* `ARM_ARCH_MAJOR`: The major version of ARM Architecture to target when
- ``ARM_ARCH_MAJOR``: The major version of ARM Architecture to target when
compiling ARM Trusted Firmware. Its value must be numeric, and defaults to
8. See also, _ARMv8 Architecture Extensions_ in [Firmware Design].
8 . See also, *ARMv8 Architecture Extensions* in `Firmware Design`_.
* `ARM_ARCH_MINOR`: The minor version of ARM Architecture to target when
- ``ARM_ARCH_MINOR``: The minor version of ARM Architecture to target when
compiling ARM Trusted Firmware. Its value must be a numeric, and defaults
to 0. See also, _ARMv8 Architecture Extensions_ in [Firmware Design].
to 0. See also, *ARMv8 Architecture Extensions* in `Firmware Design`_.
* `ARM_GIC_ARCH`: Choice of ARM GIC architecture version used by the ARM
- ``ARM_GIC_ARCH``: Choice of ARM GIC architecture version used by the ARM
Legacy GIC driver for implementing the platform GIC API. This API is used
by the interrupt management framework. Default is 2 (that is, version 2.0).
This build option is deprecated.
* `ARM_PLAT_MT`: This flag determines whether the ARM platform layer has to
cater for the multi-threading `MT` bit when accessing MPIDR. When this
flag is set, the functions which deal with MPIDR assume that the `MT` bit
- ``ARM_PLAT_MT``: This flag determines whether the ARM platform layer has to
cater for the multi-threading ``MT`` bit when accessing MPIDR. When this
flag is set, the functions which deal with MPIDR assume that the ``MT`` bit
in MPIDR is set and access the bit-fields in MPIDR accordingly. Default
value of this flag is 0.
* `BL2`: This is an optional build option which specifies the path to BL2
image for the `fip` target. In this case, the BL2 in the ARM Trusted
- ``BL2``: This is an optional build option which specifies the path to BL2
image for the ``fip`` target. In this case, the BL2 in the ARM Trusted
Firmware will not be built.
* `BL2U`: This is an optional build option which specifies the path to
- ``BL2U``: This is an optional build option which specifies the path to
BL2U image. In this case, the BL2U in the ARM Trusted Firmware will not
be built.
* `BL31`: This is an optional build option which specifies the path to
BL31 image for the `fip` target. In this case, the BL31 in the ARM
- ``BL31``: This is an optional build option which specifies the path to
BL31 image for the ``fip`` target. In this case, the BL31 in the ARM
Trusted Firmware will not be built.
* `BL31_KEY`: This option is used when `GENERATE_COT=1`. It specifies the
file that contains the BL31 private key in PEM format. If `SAVE_KEYS=1`,
- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
this file name will be used to save the key.
* `BL32`: This is an optional build option which specifies the path to
BL32 image for the `fip` target. In this case, the BL32 in the ARM
- ``BL32``: This is an optional build option which specifies the path to
BL32 image for the ``fip`` target. In this case, the BL32 in the ARM
Trusted Firmware will not be built.
* `BL32_KEY`: This option is used when `GENERATE_COT=1`. It specifies the
file that contains the BL32 private key in PEM format. If `SAVE_KEYS=1`,
- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
this file name will be used to save the key.
* `BL33`: Path to BL33 image in the host file system. This is mandatory for
`fip` target in case the BL2 from ARM Trusted Firmware is used.
- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
``fip`` target in case the BL2 from ARM Trusted Firmware is used.
* `BL33_KEY`: This option is used when `GENERATE_COT=1`. It specifies the
file that contains the BL33 private key in PEM format. If `SAVE_KEYS=1`,
- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
this file name will be used to save the key.
* `BUILD_MESSAGE_TIMESTAMP`: String used to identify the time and date of the
- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
compilation of each build. It must be set to a C string (including quotes
where applicable). Defaults to a string that contains the time and date of
the compilation.
* `BUILD_STRING`: Input string for VERSION_STRING, which allows the TF build
- ``BUILD_STRING``: Input string for VERSION\_STRING, which allows the TF build
to be uniquely identified. Defaults to the current git commit id.
* `CFLAGS`: Extra user options appended on the compiler's command line in
- ``CFLAGS``: Extra user options appended on the compiler's command line in
addition to the options set by the build system.
* `COLD_BOOT_SINGLE_CPU`: This option indicates whether the platform may
- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
release several CPUs out of reset. It can take either 0 (several CPUs may be
brought up) or 1 (only one CPU will ever be brought up during cold reset).
Default is 0. If the platform always brings up a single CPU, there is no
need to distinguish between primary and secondary CPUs and the boot path can
be optimised. The `plat_is_my_cpu_primary()` and
`plat_secondary_cold_boot_setup()` platform porting interfaces do not need
be optimised. The ``plat_is_my_cpu_primary()`` and
``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
to be implemented in this case.
* `CRASH_REPORTING`: A non-zero value enables a console dump of processor
- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
register state when an unexpected exception occurs during execution of
BL31. This option defaults to the value of `DEBUG` - i.e. by default
BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
this is only enabled for a debug build of the firmware.
* `CREATE_KEYS`: This option is used when `GENERATE_COT=1`. It tells the
- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
certificate generation tool to create new keys in case no valid keys are
present or specified. Allowed options are '0' or '1'. Default is '1'.
* `CTX_INCLUDE_AARCH32_REGS` : Boolean option that, when set to 1, will cause
- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
the AArch32 system registers to be included when saving and restoring the
CPU context. The option must be set to 0 for AArch64-only platforms (that
is on hardware that does not implement AArch32, or at least not at EL1 and
higher ELs). Default value is 1.
* `CTX_INCLUDE_FPREGS`: Boolean option that, when set to 1, will cause the FP
- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
registers to be included when saving and restoring the CPU context. Default
is 0.
* `DEBUG`: Chooses between a debug and release build. It can take either 0
- ``DEBUG``: Chooses between a debug and release build. It can take either 0
(release) or 1 (debug) as values. 0 is the default.
* `EL3_PAYLOAD_BASE`: This option enables booting an EL3 payload instead of
- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
the normal boot flow. It must specify the entry point address of the EL3
payload. Please refer to the "Booting an EL3 payload" section for more
details.
* `ENABLE_ASSERTIONS`: This option controls whether or not calls to `assert()`
- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
are compiled out. For debug builds, this option defaults to 1, and calls to
`assert()` are left in place. For release builds, this option defaults to 0
and calls to `assert()` function are compiled out. This option can be set
independently of `DEBUG`. It can also be used to hide any auxiliary code
``assert()`` are left in place. For release builds, this option defaults to 0
and calls to ``assert()`` function are compiled out. This option can be set
independently of ``DEBUG``. It can also be used to hide any auxiliary code
that is only required for the assertion and does not fit in the assertion
itself.
* `ENABLE_PMF`: Boolean option to enable support for optional Performance
- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
Measurement Framework(PMF). Default is 0.
* `ENABLE_PSCI_STAT`: Boolean option to enable support for optional PSCI
functions `PSCI_STAT_RESIDENCY` and `PSCI_STAT_COUNT`. Default is 0.
In the absence of an alternate stat collection backend, `ENABLE_PMF` must
be enabled. If `ENABLE_PMF` is set, the residency statistics are tracked in
- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
software.
* `ENABLE_RUNTIME_INSTRUMENTATION`: Boolean option to enable runtime
- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
instrumentation which injects timestamp collection points into
Trusted Firmware to allow runtime performance to be measured.
Currently, only PSCI is instrumented. Enabling this option enables
the `ENABLE_PMF` build option as well. Default is 0.
the ``ENABLE_PMF`` build option as well. Default is 0.
* `ENABLE_STACK_PROTECTOR`: String option to enable the stack protection
- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
checks in GCC. Allowed values are "all", "strong" and "0" (default).
"strong" is the recommended stack protection level if this feature is
desired. 0 disables the stack protection. For all values other than 0, the
`plat_get_stack_protector_canary()` platform hook needs to be implemented.
``plat_get_stack_protector_canary()`` platform hook needs to be implemented.
The value is passed as the last component of the option
`-fstack-protector-$ENABLE_STACK_PROTECTOR`.
``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
* `ERROR_DEPRECATED`: This option decides whether to treat the usage of
- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
deprecated platform APIs, helper functions or drivers within Trusted
Firmware as error. It can take the value 1 (flag the use of deprecated
APIs as error) or 0. The default is 0.
* `FIP_NAME`: This is an optional build option which specifies the FIP
filename for the `fip` target. Default is `fip.bin`.
- ``FIP_NAME``: This is an optional build option which specifies the FIP
filename for the ``fip`` target. Default is ``fip.bin``.
* `FWU_FIP_NAME`: This is an optional build option which specifies the FWU
FIP filename for the `fwu_fip` target. Default is `fwu_fip.bin`.
- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
* `GENERATE_COT`: Boolean flag used to build and execute the `cert_create`
- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
tool to create certificates as per the Chain of Trust described in
[Trusted Board Boot]. The build system then calls `fiptool` to
include the certificates in the FIP and FWU_FIP. Default value is '0'.
`Trusted Board Boot`_. The build system then calls ``fiptool`` to
include the certificates in the FIP and FWU\_FIP. Default value is '0'.
Specify both `TRUSTED_BOARD_BOOT=1` and `GENERATE_COT=1` to include support
Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
the corresponding certificates, and to include those certificates in the
FIP and FWU_FIP.
FIP and FWU\_FIP.
Note that if `TRUSTED_BOARD_BOOT=0` and `GENERATE_COT=1`, the BL1 and BL2
Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
images will not include support for Trusted Board Boot. The FIP will still
include the corresponding certificates. This FIP can be used to verify the
Chain of Trust on the host machine through other mechanisms.
Note that if `TRUSTED_BOARD_BOOT=1` and `GENERATE_COT=0`, the BL1 and BL2
images will include support for Trusted Board Boot, but the FIP and FWU_FIP
Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
images will include support for Trusted Board Boot, but the FIP and FWU\_FIP
will not include the corresponding certificates, causing a boot failure.
* `HANDLE_EA_EL3_FIRST`: When defined External Aborts and SError Interrupts
- ``HANDLE_EA_EL3_FIRST``: When defined External Aborts and SError Interrupts
will be always trapped in EL3 i.e. in BL31 at runtime.
* `HW_ASSISTED_COHERENCY`: On most ARM systems to-date, platform-specific
- ``HW_ASSISTED_COHERENCY``: On most ARM systems to-date, platform-specific
software operations are required for CPUs to enter and exit coherency.
However, there exists newer systems where CPUs' entry to and exit from
coherency is managed in hardware. Such systems require software to only
......@@ -380,26 +386,28 @@ performed.
active software management. In such systems, this boolean option enables ARM
Trusted Firmware to carry out build and run-time optimizations during boot
and power management operations. This option defaults to 0 and if it is
enabled, then it implies `WARMBOOT_ENABLE_DCACHE_EARLY` is also enabled.
enabled, then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
* `JUNO_AARCH32_EL3_RUNTIME`: This build flag enables you to execute EL3
- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
runtime software in AArch32 mode, which is required to run AArch32 on Juno.
By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
AArch64 and facilitates the loading of `SP_MIN` and BL33 as AArch32 executable
AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
images.
* `LDFLAGS`: Extra user options appended to the linkers' command line in
- ``LDFLAGS``: Extra user options appended to the linkers' command line in
addition to the one set by the build system.
* `LOAD_IMAGE_V2`: Boolean option to enable support for new version (v2) of
- ``LOAD_IMAGE_V2``: Boolean option to enable support for new version (v2) of
image loading, which provides more flexibility and scalability around what
images are loaded and executed during boot. Default is 0.
Note: `TRUSTED_BOARD_BOOT` is currently only supported for AArch64 when
`LOAD_IMAGE_V2` is enabled.
Note: ``TRUSTED_BOARD_BOOT`` is currently only supported for AArch64 when
``LOAD_IMAGE_V2`` is enabled.
* `LOG_LEVEL`: Chooses the log level, which controls the amount of console log
- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
output compiled into the build. This should be one of the following:
::
0 (LOG_LEVEL_NONE)
10 (LOG_LEVEL_NOTICE)
20 (LOG_LEVEL_ERROR)
......@@ -410,124 +418,124 @@ performed.
All log output up to and including the log level is compiled into the build.
The default value is 40 in debug builds and 20 in release builds.
* `NON_TRUSTED_WORLD_KEY`: This option is used when `GENERATE_COT=1`. It
- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
specifies the file that contains the Non-Trusted World private key in PEM
format. If `SAVE_KEYS=1`, this file name will be used to save the key.
format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
* `NS_BL2U`: Path to NS_BL2U image in the host file system. This image is
- ``NS_BL2U``: Path to NS\_BL2U image in the host file system. This image is
optional. It is only needed if the platform makefile specifies that it
is required in order to build the `fwu_fip` target.
is required in order to build the ``fwu_fip`` target.
* `NS_TIMER_SWITCH`: Enable save and restore for non-secure timer register
- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
contents upon world switch. It can take either 0 (don't save and restore) or
1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
wants the timer registers to be saved and restored.
* `PL011_GENERIC_UART`: Boolean option to indicate the PL011 driver that
- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
the underlying hardware is not a full PL011 UART but a minimally compliant
generic UART, which is a subset of the PL011. The driver will not access
any register that is not part of the SBSA generic UART specification.
Default value is 0 (a full PL011 compliant UART is present).
* `PLAT`: Choose a platform to build ARM Trusted Firmware for. The chosen
platform name must be subdirectory of any depth under `plat/`, and must
contain a platform makefile named `platform.mk`.
- ``PLAT``: Choose a platform to build ARM Trusted Firmware for. The chosen
platform name must be subdirectory of any depth under ``plat/``, and must
contain a platform makefile named ``platform.mk``.
* `PRELOADED_BL33_BASE`: This option enables booting a preloaded BL33 image
- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
instead of the normal boot flow. When defined, it must specify the entry
point address for the preloaded BL33 image. This option is incompatible with
`EL3_PAYLOAD_BASE`. If both are defined, `EL3_PAYLOAD_BASE` has priority
over `PRELOADED_BL33_BASE`.
``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
over ``PRELOADED_BL33_BASE``.
* `PROGRAMMABLE_RESET_ADDRESS`: This option indicates whether the reset
- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
vector address can be programmed or is fixed on the platform. It can take
either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
programmable reset address, it is expected that a CPU will start executing
code directly at the right address, both on a cold and warm reset. In this
case, there is no need to identify the entrypoint on boot and the boot path
can be optimised. The `plat_get_my_entrypoint()` platform porting interface
can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
does not need to be implemented in this case.
* `PSCI_EXTENDED_STATE_ID`: As per PSCI1.0 Specification, there are 2 formats
- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
possible for the PSCI power-state parameter viz original and extended
State-ID formats. This flag if set to 1, configures the generic PSCI layer
to use the extended format. The default value of this flag is 0, which
means by default the original power-state format is used by the PSCI
implementation. This flag should be specified by the platform makefile
and it governs the return value of PSCI_FEATURES API for CPU_SUSPEND
and it governs the return value of PSCI\_FEATURES API for CPU\_SUSPEND
smc function id. When this option is enabled on ARM platforms, the
option `ARM_RECOM_STATE_ID_ENC` needs to be set to 1 as well.
option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well.
* `RESET_TO_BL31`: Enable BL31 entrypoint as the CPU reset vector instead
- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
entrypoint) or 1 (CPU reset to BL31 entrypoint).
The default value is 0.
* `RESET_TO_SP_MIN`: SP_MIN is the minimal AArch32 Secure Payload provided in
ARM Trusted Firmware. This flag configures SP_MIN entrypoint as the CPU
- ``RESET_TO_SP_MIN``: SP\_MIN is the minimal AArch32 Secure Payload provided in
ARM Trusted Firmware. This flag configures SP\_MIN entrypoint as the CPU
reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU
reset to BL1 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default
reset to BL1 entrypoint) or 1 (CPU reset to SP\_MIN entrypoint). The default
value is 0.
* `ROT_KEY`: This option is used when `GENERATE_COT=1`. It specifies the
file that contains the ROT private key in PEM format. If `SAVE_KEYS=1`, this
- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
file name will be used to save the key.
* `SAVE_KEYS`: This option is used when `GENERATE_COT=1`. It tells the
- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
certificate generation tool to save the keys used to establish the Chain of
Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
* `SCP_BL2`: Path to SCP_BL2 image in the host file system. This image is optional.
If a SCP_BL2 image is present then this option must be passed for the `fip`
- ``SCP_BL2``: Path to SCP\_BL2 image in the host file system. This image is optional.
If a SCP\_BL2 image is present then this option must be passed for the ``fip``
target.
* `SCP_BL2_KEY`: This option is used when `GENERATE_COT=1`. It specifies the
file that contains the SCP_BL2 private key in PEM format. If `SAVE_KEYS=1`,
- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
file that contains the SCP\_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
this file name will be used to save the key.
* `SCP_BL2U`: Path to SCP_BL2U image in the host file system. This image is
- ``SCP_BL2U``: Path to SCP\_BL2U image in the host file system. This image is
optional. It is only needed if the platform makefile specifies that it
is required in order to build the `fwu_fip` target.
is required in order to build the ``fwu_fip`` target.
* `SEPARATE_CODE_AND_RODATA`: Whether code and read-only data should be
- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
isolated on separate memory pages. This is a trade-off between security and
memory usage. See "Isolating code and read-only data on separate memory
pages" section in [Firmware Design]. This flag is disabled by default and
pages" section in `Firmware Design`_. This flag is disabled by default and
affects all BL images.
* `SPD`: Choose a Secure Payload Dispatcher component to be built into the
Trusted Firmware. This build option is only valid if `ARCH=aarch64`. The
- ``SPD``: Choose a Secure Payload Dispatcher component to be built into the
Trusted Firmware. This build option is only valid if ``ARCH=aarch64``. The
value should be the path to the directory containing the SPD source,
relative to `services/spd/`; the directory is expected to
contain a makefile called `<spd-value>.mk`.
relative to ``services/spd/``; the directory is expected to
contain a makefile called ``<spd-value>.mk``.
* `SPIN_ON_BL1_EXIT`: This option introduces an infinite loop in BL1. It can
- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
execution in BL1 just before handing over to BL31. At this point, all
firmware images have been loaded in memory, and the MMU and caches are
turned off. Refer to the "Debugging options" section for more details.
* `TRUSTED_BOARD_BOOT`: Boolean flag to include support for the Trusted Board
- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
Boot feature. When set to '1', BL1 and BL2 images include support to load
and verify the certificates and images in a FIP, and BL1 includes support
for the Firmware Update. The default value is '0'. Generation and inclusion
of certificates in the FIP and FWU_FIP depends upon the value of the
`GENERATE_COT` option.
of certificates in the FIP and FWU\_FIP depends upon the value of the
``GENERATE_COT`` option.
Note: This option depends on `CREATE_KEYS` to be enabled. If the keys
Note: This option depends on ``CREATE_KEYS`` to be enabled. If the keys
already exist in disk, they will be overwritten without further notice.
* `TRUSTED_WORLD_KEY`: This option is used when `GENERATE_COT=1`. It
- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
specifies the file that contains the Trusted World private key in PEM
format. If `SAVE_KEYS=1`, this file name will be used to save the key.
format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
* `TSP_INIT_ASYNC`: Choose BL32 initialization method as asynchronous or
synchronous, (see "Initializing a BL32 Image" section in [Firmware
Design]). It can take the value 0 (BL32 is initialized using
- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
synchronous, (see "Initializing a BL32 Image" section in
`Firmware Design`_). It can take the value 0 (BL32 is initialized using
synchronous method) or 1 (BL32 is initialized using asynchronous method).
Default is 0.
* `TSP_NS_INTR_ASYNC_PREEMPT`: A non zero value enables the interrupt
- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
routing model which routes non-secure interrupts asynchronously from TSP
to EL3 causing immediate preemption of TSP. The EL3 is responsible
for saving and restoring the TSP context in this routing model. The
......@@ -535,39 +543,40 @@ performed.
interrupts to TSP allowing it to save its context and hand over
synchronously to EL3 via an SMC.
* `USE_COHERENT_MEM`: This flag determines whether to include the coherent
- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
memory region in the BL memory map or not (see "Use of Coherent memory in
Trusted Firmware" section in [Firmware Design]). It can take the value 1
Trusted Firmware" section in `Firmware Design`_). It can take the value 1
(Coherent memory region is included) or 0 (Coherent memory region is
excluded). Default is 1.
* `V`: Verbose build. If assigned anything other than 0, the build commands
- ``V``: Verbose build. If assigned anything other than 0, the build commands
are printed. Default is 0.
* `VERSION_STRING`: String used in the log output for each TF image. Defaults
- ``VERSION_STRING``: String used in the log output for each TF image. Defaults
to a string formed by concatenating the version number, build type and build
string.
* `WARMBOOT_ENABLE_DCACHE_EARLY` : Boolean option to enable D-cache early on
- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
the CPU after warm boot. This is applicable for platforms which do not
require interconnect programming to enable cache coherency (eg: single
cluster platforms). If this option is enabled, then warm boot path
enables D-caches immediately after enabling MMU. This option defaults to 0.
* `ENABLE_SPE_FOR_LOWER_ELS` : Boolean option to enable Statistical Profiling
- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
extensions. This is an optional architectural feature available only for
AArch64 8.2 onwards. This option defaults to 1 but is automatically
disabled when the target architecture is AArch32 or AArch64 8.0/8.1.
#### ARM development platform specific build options
ARM development platform specific build options
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
* `ARM_BL31_IN_DRAM`: Boolean option to select loading of BL31 in TZC secured
- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
BL31 in TZC secured DRAM. If TSP is present, then setting this option also
sets the TSP location to DRAM and ignores the `ARM_TSP_RAM_LOCATION` build
sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
flag.
* `ARM_BOARD_OPTIMISE_MEM`: Boolean option to enable or disable optimisation
- ``ARM_BOARD_OPTIMISE_MEM``: Boolean option to enable or disable optimisation
of the memory reserved for each image. This affects the maximum size of each
BL image as well as the number of allocated memory regions and translation
tables. By default this flag is 0, which means it uses the default
......@@ -575,13 +584,13 @@ performed.
optimise memory usage need to set this flag to 1 and must override the
related macros.
* `ARM_CONFIG_CNTACR`: boolean option to unlock access to the CNTBase<N>
frame registers by setting the CNTCTLBase.CNTACR<N> register bits. The
frame number <N> is defined by `PLAT_ARM_NSTIMER_FRAME_ID`, which should
- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
match the frame used by the Non-Secure image (normally the Linux kernel).
Default is true (access to the frame is allowed).
* `ARM_DISABLE_TRUSTED_WDOG`: boolean option to disable the Trusted Watchdog.
- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
By default, ARM platforms use a watchdog to trigger a system reset in case
an error is encountered during the boot process (for example, when an image
could not be loaded or authenticated). The watchdog is enabled in the early
......@@ -589,7 +598,7 @@ performed.
Trusted Watchdog may be disabled at build time for testing or development
purposes.
* `ARM_RECOM_STATE_ID_ENC`: The PSCI1.0 specification recommends an encoding
- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
for the construction of composite state-ID in the power-state parameter.
The existing PSCI clients currently do not support this encoding of
State-ID yet. Hence this flag is used to configure whether to use the
......@@ -597,120 +606,132 @@ performed.
in which case the platform is configured to expect NULL in the State-ID
field of power-state parameter.
* `ARM_ROTPK_LOCATION`: used when `TRUSTED_BOARD_BOOT=1`. It specifies the
location of the ROTPK hash returned by the function `plat_get_rotpk_info()`
- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
for ARM platforms. Depending on the selected option, the proper private key
must be specified using the `ROT_KEY` option when building the Trusted
must be specified using the ``ROT_KEY`` option when building the Trusted
Firmware. This private key will be used by the certificate generation tool
to sign the BL2 and Trusted Key certificates. Available options for
`ARM_ROTPK_LOCATION` are:
``ARM_ROTPK_LOCATION`` are:
- `regs` : return the ROTPK hash stored in the Trusted root-key storage
- ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
registers. The private key corresponding to this ROTPK hash is not
currently available.
- `devel_rsa` : return a development public key hash embedded in the BL1
- ``devel_rsa`` : return a development public key hash embedded in the BL1
and BL2 binaries. This hash has been obtained from the RSA public key
`arm_rotpk_rsa.der`, located in `plat/arm/board/common/rotpk`. To use
this option, `arm_rotprivk_rsa.pem` must be specified as `ROT_KEY` when
``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
creating the certificates.
* `ARM_TSP_RAM_LOCATION`: location of the TSP binary. Options:
- `tsram` : Trusted SRAM (default option)
- `tdram` : Trusted DRAM (if available)
- `dram` : Secure region in DRAM (configured by the TrustZone controller)
- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
- ``tsram`` : Trusted SRAM (default option)
- ``tdram`` : Trusted DRAM (if available)
- ``dram`` : Secure region in DRAM (configured by the TrustZone controller)
* `ARM_XLAT_TABLES_LIB_V1`: boolean option to compile the Trusted Firmware
- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile the Trusted Firmware
with version 1 of the translation tables library instead of version 2. It is
set to 0 by default, which selects version 2.
* `ARM_CRYPTOCELL_INTEG` : bool option to enable Trusted Firmware to invoke
- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable Trusted Firmware to invoke
ARM® TrustZone® CryptoCell functionality for Trusted Board Boot on capable
ARM platforms. If this option is specified, then the path to the CryptoCell
SBROM library must be specified via `CCSBROM_LIB_PATH` flag.
SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
For a better understanding of these options, the ARM development platform memory
map is explained in the [Firmware Design].
map is explained in the `Firmware Design`_.
#### ARM CSS platform specific build options
ARM CSS platform specific build options
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
* `CSS_DETECT_PRE_1_7_0_SCP`: Boolean flag to detect SCP version
- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
compatible change to the MTL protocol, used for AP/SCP communication.
Trusted Firmware no longer supports earlier SCP versions. If this option is
set to 1 then Trusted Firmware will detect if an earlier version is in use.
Default is 1.
* `CSS_LOAD_SCP_IMAGES`: Boolean flag, which when set, adds SCP_BL2 and
SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded
- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP\_BL2 and
SCP\_BL2U to the FIP and FWU\_FIP respectively, and enables them to be loaded
during boot. Default is 1.
* `CSS_USE_SCMI_DRIVER`: Boolean flag which selects SCMI driver instead of
- ``CSS_USE_SCMI_DRIVER``: Boolean flag which selects SCMI driver instead of
SCPI driver for communicating with the SCP during power management operations.
If this option is set to 1, then SCMI driver will be used. Default is 0.
#### ARM FVP platform specific build options
ARM FVP platform specific build options
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
* `FVP_CLUSTER_COUNT` : Configures the cluster count to be used to
- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
build the topology tree within Trusted Firmware. By default the
Trusted Firmware is configured for dual cluster topology and this option
can be used to override the default value.
* `FVP_INTERCONNECT_DRIVER`: Selects the interconnect driver to be built. The
default interconnect driver depends on the value of `FVP_CLUSTER_COUNT` as
- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
explained in the options below:
- `FVP_CCI` : The CCI driver is selected. This is the default
if 0 < `FVP_CLUSTER_COUNT` <= 2.
- `FVP_CCN` : The CCN driver is selected. This is the default
if `FVP_CLUSTER_COUNT` > 2.
* `FVP_USE_GIC_DRIVER` : Selects the GIC driver to be built. Options:
- `FVP_GIC600` : The GIC600 implementation of GICv3 is selected
- `FVP_GICV2` : The GICv2 only driver is selected
- `FVP_GICV3` : The GICv3 only driver is selected (default option)
- `FVP_GICV3_LEGACY`: The Legacy GICv3 driver is selected (deprecated)
- ``FVP_CCI`` : The CCI driver is selected. This is the default
if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
- ``FVP_CCN`` : The CCN driver is selected. This is the default
if ``FVP_CLUSTER_COUNT`` > 2.
- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
- ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
- ``FVP_GICV2`` : The GICv2 only driver is selected
- ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
- ``FVP_GICV3_LEGACY``: The Legacy GICv3 driver is selected (deprecated)
Note: If Trusted Firmware is compiled with this option on FVPs with
GICv3 hardware, then it configures the hardware to run in GICv2
emulation mode
* `FVP_USE_SP804_TIMER` : Use the SP804 timer instead of the Generic Timer
- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
for functions that wait for an arbitrary time length (udelay and mdelay).
The default value is 0.
### Debugging options
Debugging options
~~~~~~~~~~~~~~~~~
To compile a debug version and make the build more verbose use
::
make PLAT=<platform> DEBUG=1 V=1 all
AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
example DS-5) might not support this and may need an older version of DWARF
symbols to be emitted by GCC. This can be achieved by using the
`-gdwarf-<version>` flag, with the version being set to 2 or 3. Setting the
``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
version to 2 is recommended for DS-5 versions older than 5.16.
When debugging logic problems it might also be useful to disable all compiler
optimizations by using `-O0`.
optimizations by using ``-O0``.
NOTE: Using `-O0` could cause output images to be larger and base addresses
NOTE: Using ``-O0`` could cause output images to be larger and base addresses
might need to be recalculated (see the **Memory layout on ARM development
platforms** section in the [Firmware Design]).
platforms** section in the `Firmware Design`_).
Extra debug options can be passed to the build system by setting ``CFLAGS`` or
``LDFLAGS``:
Extra debug options can be passed to the build system by setting `CFLAGS` or
`LDFLAGS`:
.. code:: makefile
CFLAGS='-O0 -gdwarf-2' \
make PLAT=<platform> DEBUG=1 V=1 all
Note that using `-Wl,` style compilation driver options in `CFLAGS` will be
Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
ignored as the linker is called directly.
It is also possible to introduce an infinite loop to help in debugging the
post-BL2 phase of the Trusted Firmware. This can be done by rebuilding BL1 with
the `SPIN_ON_BL1_EXIT=1` build flag. Refer to the "Summary of build options"
the ``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
section. In this case, the developer may take control of the target using a
debugger when indicated by the console output. When using DS-5, the following
commands can be used:
::
# Stop target execution
interrupt
......@@ -724,47 +745,56 @@ commands can be used:
# Resume execution
continue
### Building the Test Secure Payload
Building the Test Secure Payload
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The TSP is coupled with a companion runtime service in the BL31 firmware,
called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
must be recompiled as well. For more information on SPs and SPDs, see the
"Secure-EL1 Payloads and Dispatchers" section in the [Firmware Design].
`Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
First clean the Trusted Firmware build directory to get rid of any previous
BL31 binary. Then to build the TSP image use:
::
make PLAT=<platform> SPD=tspd all
An additional boot loader binary file is created in the `build` directory:
An additional boot loader binary file is created in the ``build`` directory:
::
build/<platform>/<build-type>/bl32.bin
### Checking source code style
Checking source code style
~~~~~~~~~~~~~~~~~~~~~~~~~~
When making changes to the source for submission to the project, the source
must be in compliance with the Linux style guide, and to assist with this check
the project Makefile contains two targets, which both utilise the
`checkpatch.pl` script that ships with the Linux source tree.
``checkpatch.pl`` script that ships with the Linux source tree.
To check the entire source tree, you must first download a copy of
`checkpatch.pl` (or the full Linux source), set the `CHECKPATCH` environment
``checkpatch.pl`` (or the full Linux source), set the ``CHECKPATCH`` environment
variable to point to the script and build the target checkcodebase:
::
make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
To just check the style on the files that differ between your local branch and
the remote master, use:
::
make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
If you wish to check your patch against something other than the remote master,
set the `BASE_COMMIT` variable to your desired branch. By default, `BASE_COMMIT`
is set to `origin/master`.
set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
is set to ``origin/master``.
### Building and using the FIP tool
Building and using the FIP tool
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Firmware Image Package (FIP) is a packaging format used by the Trusted Firmware
project to package firmware images in a single binary. The number and type of
......@@ -773,17 +803,21 @@ images and other firmware images required by the platform. For example, most
platforms require a BL33 image which corresponds to the normal world bootloader
(e.g. UEFI or U-Boot).
The TF build system provides the make target `fip` to create a FIP file for the
The TF build system provides the make target ``fip`` to create a FIP file for the
specified platform using the FIP creation tool included in the TF project.
Examples below show how to build a FIP file for FVP, packaging TF images and a
BL33 image.
For AArch64:
::
make PLAT=fvp BL33=<path/to/bl33.bin> fip
For AArch32:
::
make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path/to/bl33.bin> fip
Note that AArch32 support for Normal world boot loader (BL33), like U-boot or
......@@ -793,6 +827,8 @@ allow Linux boot on FVP. These instructions assume such a custom boot loader
The resulting FIP may be found in:
::
build/fvp/<build-type>/fip.bin
For advanced operations on FIP files, it is also possible to independently build
......@@ -801,20 +837,28 @@ steps:
It is recommended to remove old artifacts before building the tool:
::
make -C tools/fiptool clean
Build the tool:
::
make [DEBUG=1] [V=1] fiptool
The tool binary can be located in:
::
./tools/fiptool/fiptool
Invoking the tool with `--help` will print a help message with all available
Invoking the tool with ``--help`` will print a help message with all available
options.
Example 1: create a new Firmware package `fip.bin` that contains BL2 and BL31:
Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
::
./tools/fiptool/fiptool create \
--tb-fw build/<platform>/<build-type>/bl2.bin \
......@@ -823,10 +867,14 @@ Example 1: create a new Firmware package `fip.bin` that contains BL2 and BL31:
Example 2: view the contents of an existing Firmware package:
::
./tools/fiptool/fiptool info <path-to>/fip.bin
Example 3: update the entries of an existing Firmware package:
::
# Change the BL2 from Debug to Release version
./tools/fiptool/fiptool update \
--tb-fw build/<platform>/release/bl2.bin \
......@@ -834,11 +882,15 @@ Example 3: update the entries of an existing Firmware package:
Example 4: unpack all entries from an existing Firmware package:
::
# Images will be unpacked to the working directory
./tools/fiptool/fiptool unpack <path-to>/fip.bin
Example 5: remove an entry from an existing Firmware package:
::
./tools/fiptool/fiptool remove \
--tb-fw build/<platform>/debug/fip.bin
......@@ -848,71 +900,74 @@ remove operations will automatically overwrite it.
The unpack operation will fail if the images already exist at the
destination. In that case, use -f or --force to continue.
More information about FIP can be found in the [Firmware Design document]
[Firmware Design].
More information about FIP can be found in the `Firmware Design`_ document.
#### Migrating from fip_create to fiptool
Migrating from fip\_create to fiptool
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The previous version of fiptool was called fip_create. A compatibility script
that emulates the basic functionality of the previous fip_create is provided.
The previous version of fiptool was called fip\_create. A compatibility script
that emulates the basic functionality of the previous fip\_create is provided.
However, users are strongly encouraged to migrate to fiptool.
* To create a new FIP file, replace "fip_create" with "fiptool create".
* To update a FIP file, replace "fip_create" with "fiptool update".
* To dump the contents of a FIP file, replace "fip_create --dump"
- To create a new FIP file, replace "fip\_create" with "fiptool create".
- To update a FIP file, replace "fip\_create" with "fiptool update".
- To dump the contents of a FIP file, replace "fip\_create --dump"
with "fiptool info".
### Building FIP images with support for Trusted Board Boot
Building FIP images with support for Trusted Board Boot
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Trusted Board Boot primarily consists of the following two features:
* Image Authentication, described in [Trusted Board Boot], and
* Firmware Update, described in [Firmware Update]
- Image Authentication, described in `Trusted Board Boot`_, and
- Firmware Update, described in `Firmware Update`_
The following steps should be followed to build FIP and (optionally) FWU_FIP
The following steps should be followed to build FIP and (optionally) FWU\_FIP
images with support for these features:
1. Fulfill the dependencies of the `mbedtls` cryptographic and image parser
modules by checking out a recent version of the [mbed TLS Repository]. It
#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
modules by checking out a recent version of the `mbed TLS Repository`_. It
is important to use a version that is compatible with TF and fixes any
known security vulnerabilities. See [mbed TLS Security Center] for more
information. The latest version of TF is tested with tag `mbedtls-2.4.2`.
known security vulnerabilities. See `mbed TLS Security Center`_ for more
information. The latest version of TF is tested with tag ``mbedtls-2.4.2``.
The `drivers/auth/mbedtls/mbedtls_*.mk` files contain the list of mbed TLS
The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
source files the modules depend upon.
`include/drivers/auth/mbedtls/mbedtls_config.h` contains the configuration
``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
options required to build the mbed TLS sources.
Note that the mbed TLS library is licensed under the Apache version 2.0
license. Using mbed TLS source code will affect the licensing of
Trusted Firmware binaries that are built using this library.
2. To build the FIP image, ensure the following command line variables are set
while invoking `make` to build Trusted Firmware:
#. To build the FIP image, ensure the following command line variables are set
while invoking ``make`` to build Trusted Firmware:
* `MBEDTLS_DIR=<path of the directory containing mbed TLS sources>`
* `TRUSTED_BOARD_BOOT=1`
* `GENERATE_COT=1`
- ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
- ``TRUSTED_BOARD_BOOT=1``
- ``GENERATE_COT=1``
In the case of ARM platforms, the location of the ROTPK hash must also be
specified at build time. Two locations are currently supported (see
`ARM_ROTPK_LOCATION` build option):
``ARM_ROTPK_LOCATION`` build option):
* `ARM_ROTPK_LOCATION=regs`: the ROTPK hash is obtained from the Trusted
- ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
root-key storage registers present in the platform. On Juno, this
registers are read-only. On FVP Base and Cortex models, the registers
are read-only, but the value can be specified using the command line
option `bp.trusted_key_storage.public_key` when launching the model.
option ``bp.trusted_key_storage.public_key`` when launching the model.
On both Juno and FVP models, the default value corresponds to an
ECDSA-SECP256R1 public key hash, whose private part is not currently
available.
* `ARM_ROTPK_LOCATION=devel_rsa`: use the ROTPK hash that is hardcoded
- ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
in the ARM platform port. The private/public RSA key pair may be
found in `plat/arm/board/common/rotpk`.
found in ``plat/arm/board/common/rotpk``.
Example of command line using RSA development keys:
::
MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
ARM_ROTPK_LOCATION=devel_rsa \
......@@ -925,17 +980,19 @@ images with support for these features:
described in the TBBR-client document. These certificates can also be found
in the output build directory.
3. The optional FWU_FIP contains any additional images to be loaded from
Non-Volatile storage during the [Firmware Update] process. To build the
FWU_FIP, any FWU images required by the platform must be specified on the
#. The optional FWU\_FIP contains any additional images to be loaded from
Non-Volatile storage during the `Firmware Update`_ process. To build the
FWU\_FIP, any FWU images required by the platform must be specified on the
command line. On ARM development platforms like Juno, these are:
* NS_BL2U. The AP non-secure Firmware Updater image.
* SCP_BL2U. The SCP Firmware Update Configuration image.
- NS\_BL2U. The AP non-secure Firmware Updater image.
- SCP\_BL2U. The SCP Firmware Update Configuration image.
Example of Juno command line for generating both `fwu` and `fwu_fip`
Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
targets using RSA development:
::
MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
ARM_ROTPK_LOCATION=devel_rsa \
......@@ -946,44 +1003,49 @@ images with support for these features:
NS_BL2U=<path-to>/<ns_bl2u_image> \
all fip fwu_fip
Note: The BL2U image will be built by default and added to the FWU_FIP.
The user may override this by adding `BL2U=<path-to>/<bl2u_image>`
Note: The BL2U image will be built by default and added to the FWU\_FIP.
The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
to the command line above.
Note: Building and installing the non-secure and SCP FWU images (NS_BL1U,
NS_BL2U and SCP_BL2U) is outside the scope of this document.
Note: Building and installing the non-secure and SCP FWU images (NS\_BL1U,
NS\_BL2U and SCP\_BL2U) is outside the scope of this document.
The result of this build will be bl1.bin, fip.bin and fwu_fip.bin binaries.
Both the FIP and FWU_FIP will include the certificates corresponding to the
The result of this build will be bl1.bin, fip.bin and fwu\_fip.bin binaries.
Both the FIP and FWU\_FIP will include the certificates corresponding to the
Chain of Trust described in the TBBR-client document. These certificates
can also be found in the output build directory.
Building the Certificate Generation Tool
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
### Building the Certificate Generation Tool
The `cert_create` tool is built as part of the TF build process when the `fip`
The ``cert_create`` tool is built as part of the TF build process when the ``fip``
make target is specified and TBB is enabled (as described in the previous
section), but it can also be built separately with the following command:
::
make PLAT=<platform> [DEBUG=1] [V=1] certtool
For platforms that do not require their own IDs in certificate files,
the generic 'cert_create' tool can be built with the following command:
the generic 'cert\_create' tool can be built with the following command:
::
make USE_TBBR_DEFS=1 [DEBUG=1] [V=1] certtool
`DEBUG=1` builds the tool in debug mode. `V=1` makes the build process more
``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
verbose. The following command should be used to obtain help about the tool:
./tools/cert_create/cert_create -h
::
./tools/cert_create/cert_create -h
6. Building a FIP for Juno and FVP
-----------------------------------
Building a FIP for Juno and FVP
-------------------------------
This section provides Juno and FVP specific instructions to build Trusted
Firmware, obtain the additional required firmware, and pack it all together in
a single FIP binary. It assumes that a [Linaro Release][Linaro Release Notes]
a single FIP binary. It assumes that a `Linaro Release`_
has been installed.
Note: Linaro Release 16.06 only includes pre-built binaries for AArch64. For
......@@ -993,15 +1055,19 @@ Note: follow the full instructions for one platform before switching to a
different one. Mixing instructions for different platforms may result in
corrupted binaries.
1. Clean the working directory
#. Clean the working directory
::
make realclean
2. Obtain SCP_BL2 (Juno) and BL33 (all platforms)
#. Obtain SCP\_BL2 (Juno) and BL33 (all platforms)
Use the fiptool to extract the SCP_BL2 and BL33 images from the FIP
Use the fiptool to extract the SCP\_BL2 and BL33 images from the FIP
package included in the Linaro release:
::
# Build the fiptool
make [DEBUG=1] [V=1] fiptool
......@@ -1010,17 +1076,19 @@ corrupted binaries.
<path/to/linaro/release>/fip.bin
The unpack operation will result in a set of binary images extracted to the
working directory. The SCP_BL2 image corresponds to `scp-fw.bin` and BL33
corresponds to `nt-fw.bin`.
working directory. The SCP\_BL2 image corresponds to ``scp-fw.bin`` and BL33
corresponds to ``nt-fw.bin``.
Note: the fiptool will complain if the images to be unpacked already
exist in the current directory. If that is the case, either delete those
files or use the `--force` option to overwrite.
files or use the ``--force`` option to overwrite.
Note for AArch32, the instructions below assume that nt-fw.bin is a custom
Normal world boot loader that supports AArch32.
3. Build TF images and create a new FIP for FVP
#. Build TF images and create a new FIP for FVP
::
# AArch64
make PLAT=fvp BL33=nt-fw.bin all fip
......@@ -1028,13 +1096,15 @@ corrupted binaries.
# AArch32
make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
4. Build TF images and create a new FIP for Juno
#. Build TF images and create a new FIP for Juno
For AArch64:
Building for AArch64 on Juno simply requires the addition of `SCP_BL2`
Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
as a build parameter.
::
make PLAT=juno all fip \
BL33=<path-to-juno-oe-uboot>/SOFTWARE/bl33-uboot.bin \
SCP_BL2=<path-to-juno-busybox-uboot>/SOFTWARE/scp_bl2.bin
......@@ -1045,24 +1115,32 @@ corrupted binaries.
therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
separately for AArch32.
* Before building BL32, the environment variable `CROSS_COMPILE` must point
- Before building BL32, the environment variable ``CROSS_COMPILE`` must point
to the AArch32 Linaro cross compiler.
::
export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
* Build BL32 in AArch32.
- Build BL32 in AArch32.
::
make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
* Before building BL1 and BL2, the environment variable `CROSS_COMPILE`
- Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
must point to the AArch64 Linaro cross compiler.
::
export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
* The following parameters should be used to build BL1 and BL2 in AArch64
- The following parameters should be used to build BL1 and BL2 in AArch64
and point to the BL32 file.
::
make ARCH=aarch64 PLAT=juno LOAD_IMAGE_V2=1 JUNO_AARCH32_EL3_RUNTIME=1 \
BL33=<path-to-juno32-oe-uboot>/SOFTWARE/bl33-uboot.bin \
SCP_BL2=<path-to-juno32-oe-uboot>/SOFTWARE/scp_bl2.bin SPD=tspd \
......@@ -1070,6 +1148,8 @@ corrupted binaries.
The resulting BL1 and FIP images may be found in:
::
# Juno
./build/juno/release/bl1.bin
./build/juno/release/fip.bin
......@@ -1078,9 +1158,8 @@ The resulting BL1 and FIP images may be found in:
./build/fvp/release/bl1.bin
./build/fvp/release/fip.bin
7. EL3 payloads alternative boot flow
--------------------------------------
EL3 payloads alternative boot flow
----------------------------------
On a pre-production system, the ability to execute arbitrary, bare-metal code at
the highest exception level is required. It allows full, direct access to the
......@@ -1091,14 +1170,14 @@ scratch, this is a complex task on some platforms, depending on the level of
configuration required to put the system in the expected state.
Rather than booting a baremetal application, a possible compromise is to boot
`EL3 payloads` through the Trusted Firmware instead. This is implemented as an
``EL3 payloads`` through the Trusted Firmware instead. This is implemented as an
alternative boot flow, where a modified BL2 boots an EL3 payload, instead of
loading the other BL images and passing control to BL31. It reduces the
complexity of developing EL3 baremetal code by:
* putting the system into a known architectural state;
* taking care of platform secure world initialization;
* loading the SCP_BL2 image if required by the platform.
- putting the system into a known architectural state;
- taking care of platform secure world initialization;
- loading the SCP\_BL2 image if required by the platform.
When booting an EL3 payload on ARM standard platforms, the configuration of the
TrustZone controller is simplified such that only region 0 is enabled and is
......@@ -1108,26 +1187,27 @@ DRAM to the EL3 payload.
The system is left in the same state as when entering BL31 in the default boot
flow. In particular:
* Running in EL3;
* Current state is AArch64;
* Little-endian data access;
* All exceptions disabled;
* MMU disabled;
* Caches disabled.
- Running in EL3;
- Current state is AArch64;
- Little-endian data access;
- All exceptions disabled;
- MMU disabled;
- Caches disabled.
### Booting an EL3 payload
Booting an EL3 payload
~~~~~~~~~~~~~~~~~~~~~~
The EL3 payload image is a standalone image and is not part of the FIP. It is
not loaded by the Trusted Firmware. Therefore, there are 2 possible scenarios:
* The EL3 payload may reside in non-volatile memory (NVM) and execute in
- The EL3 payload may reside in non-volatile memory (NVM) and execute in
place. In this case, booting it is just a matter of specifying the right
address in NVM through `EL3_PAYLOAD_BASE` when building the TF.
address in NVM through ``EL3_PAYLOAD_BASE`` when building the TF.
* The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
- The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
run-time.
To help in the latter scenario, the `SPIN_ON_BL1_EXIT=1` build option can be
To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
used. The infinite loop that it introduces in BL1 stops execution at the right
moment for a debugger to take control of the target and load the payload (for
example, over JTAG).
......@@ -1136,7 +1216,8 @@ It is expected that this loading method will work in most cases, as a debugger
connection is usually available in a pre-production system. The user is free to
use any other platform-specific mechanism to load the EL3 payload, though.
#### Booting an EL3 payload on FVP
Booting an EL3 payload on FVP
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
the secondary CPUs holding pen to work properly. Unfortunately, its reset value
......@@ -1147,55 +1228,65 @@ clear the mailbox at start-up.
One way to do that is to create an 8-byte file containing all zero bytes using
the following command:
::
dd if=/dev/zero of=mailbox.dat bs=1 count=8
and pre-load it into the FVP memory at the mailbox address (i.e. `0x04000000`)
and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
using the following model parameters:
::
--data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
--data=mailbox.dat@0x04000000 [Foundation FVP]
To provide the model with the EL3 payload image, the following methods may be
used:
1. If the EL3 payload is able to execute in place, it may be programmed into
#. If the EL3 payload is able to execute in place, it may be programmed into
flash memory. On Base Cortex and AEM FVPs, the following model parameter
loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
used for the FIP):
::
-C bp.flashloader1.fname="/path/to/el3-payload"
On Foundation FVP, there is no flash loader component and the EL3 payload
may be programmed anywhere in flash using method 3 below.
2. When using the `SPIN_ON_BL1_EXIT=1` loading method, the following DS-5
#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
command may be used to load the EL3 payload ELF image over JTAG:
::
load /path/to/el3-payload.elf
3. The EL3 payload may be pre-loaded in volatile memory using the following
#. The EL3 payload may be pre-loaded in volatile memory using the following
model parameters:
::
--data cluster0.cpu0="/path/to/el3-payload"@address [Base FVPs]
--data="/path/to/el3-payload"@address [Foundation FVP]
The address provided to the FVP must match the `EL3_PAYLOAD_BASE` address
The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
used when building the Trusted Firmware.
#### Booting an EL3 payload on Juno
Booting an EL3 payload on Juno
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
If the EL3 payload is able to execute in place, it may be programmed in flash
memory by adding an entry in the `SITE1/HBI0262x/images.txt` configuration file
on the Juno SD card (where `x` depends on the revision of the Juno board).
Refer to the [Juno Getting Started Guide], section 2.3 "Flash memory
memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
on the Juno SD card (where ``x`` depends on the revision of the Juno board).
Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
programming" for more information.
Alternatively, the same DS-5 command mentioned in the FVP section above can
be used to load the EL3 payload's ELF file over JTAG on Juno.
8. Preloaded BL33 alternative boot flow
----------------------------------------
Preloaded BL33 alternative boot flow
------------------------------------
Some platforms have the ability to preload BL33 into memory instead of relying
on Trusted Firmware to load it. This may simplify packaging of the normal world
......@@ -1203,72 +1294,79 @@ code and improve performance in a development environment. When secure world
cold boot is complete, Trusted Firmware simply jumps to a BL33 base address
provided at build time.
For this option to be used, the `PRELOADED_BL33_BASE` build option has to be
For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
used when compiling the Trusted Firmware. For example, the following command
will create a FIP without a BL33 and prepare to jump to a BL33 image loaded at
address 0x80000000:
::
make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
#### Boot of a preloaded bootwrapped kernel image on Base FVP
Boot of a preloaded bootwrapped kernel image on Base FVP
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The following example uses the AArch64 boot wrapper. This simplifies normal
world booting while also making use of TF features. It can be obtained from its
repository with:
::
git clone git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git
After compiling it, an ELF file is generated. It can be loaded with the
following command:
::
<path-to>/FVP_Base_AEMv8A-AEMv8A \
-C bp.secureflashloader.fname=bl1.bin \
-C bp.flashloader0.fname=fip.bin \
-a cluster0.cpu0=<bootwrapped-kernel.elf> \
--start cluster0.cpu0=0x0
The `-a cluster0.cpu0=<bootwrapped-kernel.elf>` option loads the ELF file. It
The ``-a cluster0.cpu0=<bootwrapped-kernel.elf>`` option loads the ELF file. It
also sets the PC register to the ELF entry point address, which is not the
desired behaviour, so the `--start cluster0.cpu0=0x0` option forces the PC back
to 0x0 (the BL1 entry point address) on CPU #0. The `PRELOADED_BL33_BASE` define
desired behaviour, so the ``--start cluster0.cpu0=0x0`` option forces the PC back
to 0x0 (the BL1 entry point address) on CPU #0. The ``PRELOADED_BL33_BASE`` define
used when compiling the FIP must match the ELF entry point.
#### Boot of a preloaded bootwrapped kernel image on Juno
Boot of a preloaded bootwrapped kernel image on Juno
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The procedure to obtain and compile the boot wrapper is very similar to the case
of the FVP. The execution must be stopped at the end of bl2_main(), and the
of the FVP. The execution must be stopped at the end of bl2\_main(), and the
loading method explained above in the EL3 payload boot flow section may be used
to load the ELF file over JTAG on Juno.
9. Running the software on FVP
-------------------------------
Running the software on FVP
---------------------------
The latest version of the AArch64 build of ARM Trusted Firmware has been tested
on the following ARM FVPs (64-bit host machine only).
* `Foundation_Platform` (Version 10.2, Build 10.2.20)
* `FVP_Base_AEMv8A-AEMv8A` (Version 8.4, Build 0.8.8402)
* `FVP_Base_Cortex-A57x4-A53x4` (Version 8.4, Build 0.8.8402)
- ``Foundation_Platform`` (Version 10.2, Build 10.2.20)
- ``FVP_Base_AEMv8A-AEMv8A`` (Version 8.4, Build 0.8.8402)
- ``FVP_Base_Cortex-A57x4-A53x4`` (Version 8.4, Build 0.8.8402)
The latest version of the AArch32 build of ARM Trusted Firmware has been tested
on the following ARM FVPs (64-bit host machine only).
* `FVP_Base_AEMv8A-AEMv8A` (Version 8.4, Build 0.8.8402)
* `FVP_Base_Cortex-A32x4` (Version 10.1, Build 10.1.32)
- ``FVP_Base_AEMv8A-AEMv8A`` (Version 8.4, Build 0.8.8402)
- ``FVP_Base_Cortex-A32x4`` (Version 10.1, Build 10.1.32)
NOTE: The build numbers quoted above are those reported by launching the FVP
with the `--version` parameter.
with the ``--version`` parameter.
NOTE: The software will not work on Version 1.0 of the Foundation FVP.
The commands below would report an `unhandled argument` error in this case.
The commands below would report an ``unhandled argument`` error in this case.
NOTE: FVPs can be launched with `--cadi-server` option such that a
NOTE: FVPs can be launched with ``--cadi-server`` option such that a
CADI-compliant debugger (for example, ARM DS-5) can connect to and control its
execution.
The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
downloaded for free from [ARM's website][ARM FVP website].
downloaded for free from `ARM's website`_.
Please refer to the FVP documentation for a detailed description of the model
parameter options. A brief description of the important ones that affect the ARM
......@@ -1277,51 +1375,55 @@ Trusted Firmware and normal world software behavior is provided below.
Note the instructions in the following sections assume that Linaro Release 16.06
is being used.
### Obtaining the Flattened Device Trees
Obtaining the Flattened Device Trees
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Depending on the FVP configuration and Linux configuration used, different
FDT files are required. FDTs for the Foundation and Base FVPs can be found in
the Trusted Firmware source directory under `fdts/`. The Foundation FVP has a
the Trusted Firmware source directory under ``fdts/``. The Foundation FVP has a
subset of the Base FVP components. For example, the Foundation FVP lacks CLCD
and MMC support, and has only one CPU cluster.
Note: It is not recommended to use the FDTs built along the kernel because not
all FDTs are available from there.
* `fvp-base-gicv2-psci.dtb`
- ``fvp-base-gicv2-psci.dtb``
For use with both AEMv8 and Cortex-A57-A53 Base FVPs with
Base memory map configuration.
* `fvp-base-gicv2-psci-aarch32.dtb`
- ``fvp-base-gicv2-psci-aarch32.dtb``
For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state
with Base memory map configuration.
* `fvp-base-gicv3-psci.dtb`
- ``fvp-base-gicv3-psci.dtb``
(Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base
memory map configuration and Linux GICv3 support.
* `fvp-base-gicv3-psci-aarch32.dtb`
- ``fvp-base-gicv3-psci-aarch32.dtb``
For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state
with Base memory map configuration and Linux GICv3 support.
* `fvp-foundation-gicv2-psci.dtb`
- ``fvp-foundation-gicv2-psci.dtb``
For use with Foundation FVP with Base memory map configuration.
* `fvp-foundation-gicv3-psci.dtb`
- ``fvp-foundation-gicv3-psci.dtb``
(Default) For use with Foundation FVP with Base memory map configuration
and Linux GICv3 support.
### Running on the Foundation FVP with reset to BL1 entrypoint
Running on the Foundation FVP with reset to BL1 entrypoint
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The following `Foundation_Platform` parameters should be used to boot Linux with
The following ``Foundation_Platform`` parameters should be used to boot Linux with
4 CPUs using the AArch64 build of ARM Trusted Firmware.
::
<path-to>/Foundation_Platform \
--cores=4 \
--secure-memory \
......@@ -1334,19 +1436,23 @@ The following `Foundation_Platform` parameters should be used to boot Linux with
--block-device="<path-to>/<file-system-image>"
Notes:
* BL1 is loaded at the start of the Trusted ROM.
* The Firmware Image Package is loaded at the start of NOR FLASH0.
* The Linux kernel image and device tree are loaded in DRAM.
* The default use-case for the Foundation FVP is to use the `--gicv3` option
- BL1 is loaded at the start of the Trusted ROM.
- The Firmware Image Package is loaded at the start of NOR FLASH0.
- The Linux kernel image and device tree are loaded in DRAM.
- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
and enable the GICv3 device in the model. Note that without this option,
the Foundation FVP defaults to legacy (Versatile Express) memory map which
is not supported by ARM Trusted Firmware.
### Running on the AEMv8 Base FVP with reset to BL1 entrypoint
Running on the AEMv8 Base FVP with reset to BL1 entrypoint
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux
The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
::
<path-to>/FVP_Base_AEMv8A-AEMv8A \
-C pctl.startup=0.0.0.0 \
-C bp.secure_memory=1 \
......@@ -1360,11 +1466,14 @@ with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
### Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux
The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
with 8 CPUs using the AArch32 build of ARM Trusted Firmware.
::
<path-to>/FVP_Base_AEMv8A-AEMv8A \
-C pctl.startup=0.0.0.0 \
-C bp.secure_memory=1 \
......@@ -1386,11 +1495,14 @@ with 8 CPUs using the AArch32 build of ARM Trusted Firmware.
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
### Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The following `FVP_Base_Cortex-A57x4-A53x4` model parameters should be used to
The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
::
<path-to>/FVP_Base_Cortex-A57x4-A53x4 \
-C pctl.startup=0.0.0.0 \
-C bp.secure_memory=1 \
......@@ -1402,11 +1514,14 @@ boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
### Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The following `FVP_Base_Cortex-A32x4` model parameters should be used to
The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware.
::
<path-to>/FVP_Base_Cortex-A32x4 \
-C pctl.startup=0.0.0.0 \
-C bp.secure_memory=1 \
......@@ -1418,11 +1533,14 @@ boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware.
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
### Running on the AEMv8 Base FVP with reset to BL31 entrypoint
Running on the AEMv8 Base FVP with reset to BL31 entrypoint
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux
The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
::
<path-to>/FVP_Base_AEMv8A-AEMv8A \
-C pctl.startup=0.0.0.0 \
-C bp.secure_memory=1 \
......@@ -1447,26 +1565,29 @@ with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
Notes:
* Since a FIP is not loaded when using BL31 as reset entrypoint, the
`--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>`
- Since a FIP is not loaded when using BL31 as reset entrypoint, the
``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
parameter is needed to load the individual bootloader images in memory.
BL32 image is only needed if BL31 has been built to expect a Secure-EL1
Payload.
* The `-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>` parameter, where
- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
X and Y are the cluster and CPU numbers respectively, is used to set the
reset vector for each core.
* Changing the default value of `ARM_TSP_RAM_LOCATION` will also require
- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
changing the value of
`--data="<path-to><bl32-binary>"@<base-address-of-bl32>` to the new value of
`BL32_BASE`.
``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
``BL32_BASE``.
### Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
Running on the AEMv8 Base FVP (AArch32) with reset to SP\_MIN entrypoint
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux
The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
with 8 CPUs using the AArch32 build of ARM Trusted Firmware.
::
<path-to>/FVP_Base_AEMv8A-AEMv8A \
-C pctl.startup=0.0.0.0 \
-C bp.secure_memory=1 \
......@@ -1496,14 +1617,17 @@ with 8 CPUs using the AArch32 build of ARM Trusted Firmware.
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
Note: The load address of `<bl32-binary>` depends on the value `BL32_BASE`.
Note: The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
It should match the address programmed into the RVBAR register as well.
### Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The following `FVP_Base_Cortex-A57x4-A53x4` model parameters should be used to
The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
::
<path-to>/FVP_Base_Cortex-A57x4-A53x4 \
-C pctl.startup=0.0.0.0 \
-C bp.secure_memory=1 \
......@@ -1524,11 +1648,14 @@ boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
### Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
Running on the Cortex-A32 Base FVP (AArch32) with reset to SP\_MIN entrypoint
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The following `FVP_Base_Cortex-A32x4` model parameters should be used to
The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware.
::
<path-to>/FVP_Base_Cortex-A32x4 \
-C pctl.startup=0.0.0.0 \
-C bp.secure_memory=1 \
......@@ -1544,58 +1671,65 @@ boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware.
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
10. Running the software on Juno
---------------------------------
Running the software on Juno
----------------------------
This version of the ARM Trusted Firmware has been tested on Juno r0 and Juno r1.
To execute the software stack on Juno, the version of the Juno board recovery
image indicated in the [Linaro Release Notes] must be installed. If you have an
image indicated in the `Linaro Release Notes`_ must be installed. If you have an
earlier version installed or are unsure which version is installed, please
re-install the recovery image by following the [Instructions for using Linaro's
deliverables on Juno][Juno Instructions].
re-install the recovery image by following the
`Instructions for using Linaro's deliverables on Juno`_.
### Preparing Trusted Firmware images
Preparing Trusted Firmware images
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
After building Trusted Firmware, the files `bl1.bin` and `fip.bin` need copying
to the `SOFTWARE/` directory of the Juno SD card.
After building Trusted Firmware, the files ``bl1.bin`` and ``fip.bin`` need copying
to the ``SOFTWARE/`` directory of the Juno SD card.
### Other Juno software information
Other Juno software information
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Please visit the [ARM Platforms Portal] to get support and obtain any other Juno
software information. Please also refer to the [Juno Getting Started Guide] to
Please visit the `ARM Platforms Portal`_ to get support and obtain any other Juno
software information. Please also refer to the `Juno Getting Started Guide`_ to
get more detailed information about the Juno ARM development platform and how to
configure it.
### Testing SYSTEM SUSPEND on Juno
Testing SYSTEM SUSPEND on Juno
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
to RAM. For more details refer to section 5.16 of [PSCI]. To test system suspend
to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
on Juno, at the linux shell prompt, issue the following command:
::
echo +10 > /sys/class/rtc/rtc0/wakealarm
echo -n mem > /sys/power/state
The Juno board should suspend to RAM and then wakeup after 10 seconds due to
wakeup interrupt from RTC.
- - - - - - - - - - - - - - - - - - - - - - - - - -
_Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved._
[Firmware Design]: firmware-design.md
[ARM FVP website]: https://developer.arm.com/products/system-design/fixed-virtual-platforms
[Linaro Release Notes]: https://community.arm.com/tools/dev-platforms/b/documents/posts/linaro-release-notes-deprecated
[ARM Platforms Portal]: https://community.arm.com/groups/arm-development-platforms
[Linaro SW Instructions]: https://community.arm.com/dev-platforms/b/documents/posts/instructions-for-using-the-linaro-software-deliverables
[Juno Instructions]: https://community.arm.com/dev-platforms/b/documents/posts/using-linaros-deliverables-on-juno
[Juno Getting Started Guide]: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
[DS-5]: http://www.arm.com/products/tools/software-tools/ds-5/index.php
[mbed TLS Repository]: https://github.com/ARMmbed/mbedtls.git
[mbed TLS Security Center]: https://tls.mbed.org/security
[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf "Power State Coordination Interface PDD (ARM DEN 0022C)"
[Trusted Board Boot]: trusted-board-boot.md
[Firmware Update]: ./firmware-update.md
[PSCI Lib Integration]: ./psci-lib-integration-guide.md
--------------
*Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.*
.. _Linaro: https://community.arm.com/tools/dev-platforms/b/documents/posts/linaro-release-notes-deprecated
.. _Instructions for using the Linaro software deliverables: https://community.arm.com/dev-platforms/b/documents/posts/instructions-for-using-the-linaro-software-deliverables
.. _Firmware Design: firmware-design.rst
.. _Linaro Release Notes: https://community.arm.com/tools/dev-platforms/b/documents/posts/linaro-release-notes-deprecated
.. _Linaro instructions: https://community.arm.com/dev-platforms/b/documents/posts/instructions-for-using-the-linaro-software-deliverables
.. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php
.. _here: ./psci-lib-integration-guide.rst
.. _Trusted Board Boot: trusted-board-boot.rst
.. _Secure-EL1 Payloads and Dispatchers: firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
.. _Firmware Update: ./firmware-update.rst
.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
.. _mbed TLS Security Center: https://tls.mbed.org/security
.. _Linaro Release: https://community.arm.com/tools/dev-platforms/b/documents/posts/linaro-release-notes-deprecated
.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
.. _ARM's website: https://developer.arm.com/products/system-design/fixed-virtual-platforms
.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/b/documents/posts/using-linaros-deliverables-on-juno
.. _ARM Platforms Portal: https://community.arm.com/groups/arm-development-platforms
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
license.md → license.rst
View file @ 7cefb56d
......@@ -3,14 +3,14 @@ Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
- Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
- Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of ARM nor the names of its contributors may be used to
- Neither the name of ARM nor the names of its contributors may be used to
endorse or promote products derived from this software without specific prior
written permission.
......@@ -25,10 +25,13 @@ ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------
--------------
Note:
Individual files contain the following tag instead of the full license text.
::
SPDX-License-Identifier: BSD-3-Clause
This enables machine processing of license information based on the SPDX
......
maintainers.md deleted 100644 → 0
View file @ aa5b843f
ARM Trusted Firmware Maintainers
================================
ARM Trusted Firmware is an ARM maintained project. All contributions are
ultimately merged by the maintainers listed below. Technical ownership of some
parts of the codebase is delegated to the sub-maintainers listed below. An
acknowledgement from these sub-maintainers may be required before the
maintainers merge a contribution.
## Maintainers
Dan Handley (dan.handley@arm.com, [danh-arm](https://github.com/danh-arm))
David Cunado (david.cunado@arm.com, [davidcunado-arm](https://github.com/davidcunado-arm))
## OPTEE and QEMU platform sub-maintainer
Jens Wiklander (jens.wiklander@linaro.org, [jenswi-linaro](https://github.com/jenswi-linaro))
Files:
* docs/spd/optee-dispatcher.md
* docs/plat/qemu.md
* services/spd/opteed/*
* plat/qemu/*
## TLK/Trusty SPDs and NVidia platforms sub-maintainer
Varun Wadekar (vwadekar@nvidia.com, [vwadekar](https://github.com/vwadekar))
Files:
* docs/spd/tlk-dispatcher.md
* docs/spd/trusty-dispatcher.md
* include/bl32/payloads/tlk.h
* include/lib/cpus/aarch64/denver.h
* lib/cpus/aarch64/denver.S
* services/spd/tlkd/*
* services/spd/trusty/*
* plat/nvidia/*
## eMMC/UFS drivers and HiSilicon platform sub-maintainer
Haojian Zhuang (haojian.zhuang@linaro.org, [hzhuang1](https://github.com/hzhuang1))
Files:
* docs/plat/hikey.md
* docs/plat/hikey960.md
* drivers/emmc/*
* drivers/partition/*
* drivers/synopsys/emmc/*
* drivers/synopsys/ufs/*
* drivers/ufs/*
* include/drivers/dw_ufs.h
* include/drivers/emmc.h
* include/drivers/ufs.h
* include/drivers/synopsys/dw_mmc.h
* plat/hisilicon/*
## MediaTek platform sub-maintainer
Yidi Lin (林以廸 yidi.lin@mediatek.com, [mtk09422](https://github.com/mtk09422))
Files:
* plat/mediatek/*
## RockChip platform sub-maintainer
Tony Xie (tony.xie@rock-chips.com, [TonyXie06](https://github.com/TonyXie06)
or [rkchrome](https://github.com/rkchrome))
Files:
* plat/rockchip/*
## Xilinx platform sub-maintainer
Sören Brinkmann (soren.brinkmann@xilinx.com, [sorenb-xlnx](https://github.com/sorenb-xlnx))
Files:
* docs/plat/xilinx-zynqmp.md
* plat/xilinx/*
maintainers.rst 0 → 100644
View file @ 7cefb56d
ARM Trusted Firmware Maintainers
================================
ARM Trusted Firmware is an ARM maintained project. All contributions are
ultimately merged by the maintainers listed below. Technical ownership of some
parts of the codebase is delegated to the sub-maintainers listed below. An
acknowledgement from these sub-maintainers may be required before the
maintainers merge a contribution.
Maintainers
-----------
Dan Handley (dan.handley@arm.com, `danh-arm`_)
David Cunado (david.cunado@arm.com, `davidcunado-arm`_)
OPTEE and QEMU platform sub-maintainer
--------------------------------------
Jens Wiklander (jens.wiklander@linaro.org, `jenswi-linaro`_)
Files:
- docs/spd/optee-dispatcher.md
- docs/plat/qemu.md
- services/spd/opteed/\*
- plat/qemu/\*
TLK/Trusty SPDs and NVidia platforms sub-maintainer
---------------------------------------------------
Varun Wadekar (vwadekar@nvidia.com, `vwadekar`_)
Files:
- docs/spd/tlk-dispatcher.md
- docs/spd/trusty-dispatcher.md
- include/bl32/payloads/tlk.h
- include/lib/cpus/aarch64/denver.h
- lib/cpus/aarch64/denver.S
- services/spd/tlkd/\*
- services/spd/trusty/\*
- plat/nvidia/\*
eMMC/UFS drivers and HiSilicon platform sub-maintainer
------------------------------------------------------
Haojian Zhuang (haojian.zhuang@linaro.org, `hzhuang1`_)
Files:
- docs/plat/hikey.md
- docs/plat/hikey960.md
- drivers/emmc/\*
- drivers/partition/\*
- drivers/synopsys/emmc/\*
- drivers/synopsys/ufs/\*
- drivers/ufs/\*
- include/drivers/dw\_ufs.h
- include/drivers/emmc.h
- include/drivers/ufs.h
- include/drivers/synopsys/dw\_mmc.h
- plat/hisilicon/\*
MediaTek platform sub-maintainer
--------------------------------
Yidi Lin (林以廸 yidi.lin@mediatek.com, `mtk09422`_)
Files:
- plat/mediatek/\*
RockChip platform sub-maintainer
--------------------------------
Tony Xie (tony.xie@rock-chips.com, `TonyXie06`_
or `rkchrome`_)
Files:
- plat/rockchip/\*
Xilinx platform sub-maintainer
------------------------------
Sören Brinkmann (soren.brinkmann@xilinx.com, `sorenb-xlnx`_)
Files:
- docs/plat/xilinx-zynqmp.md
- plat/xilinx/\*
.. _danh-arm: https://github.com/danh-arm
.. _davidcunado-arm: https://github.com/davidcunado-arm
.. _jenswi-linaro: https://github.com/jenswi-linaro
.. _vwadekar: https://github.com/vwadekar
.. _hzhuang1: https://github.com/hzhuang1
.. _mtk09422: https://github.com/mtk09422
.. _TonyXie06: https://github.com/TonyXie06
.. _rkchrome: https://github.com/rkchrome
.. _sorenb-xlnx: https://github.com/sorenb-xlnx
readme.md deleted 100644 → 0
View file @ aa5b843f
ARM Trusted Firmware - version 1.3
==================================
ARM Trusted Firmware provides a reference implementation of secure world
software for [ARMv8-A], including a [Secure Monitor] [TEE-SMC] executing at
Exception Level 3 (EL3). It implements various ARM interface standards, such as
the Power State Coordination Interface ([PSCI]), Trusted Board Boot Requirements
(TBBR, ARM DEN0006C-1) and [SMC Calling Convention][SMCCC]. As far as possible
the code is designed for reuse or porting to other ARMv8-A model and hardware
platforms.
ARM will continue development in collaboration with interested parties to
provide a full reference implementation of PSCI, TBBR and Secure Monitor code
to the benefit of all developers working with ARMv8-A TrustZone technology.
License
-------
The software is provided under a BSD-3-Clause [license]. Contributions to this
project are accepted under the same license with developer sign-off as
described in the [Contributing Guidelines].
This project contains code from other projects as listed below. The original
license text is included in those source files.
* The stdlib source code is derived from FreeBSD code.
* The libfdt source code is dual licensed. It is used by this project under
the terms of the BSD-2-Clause license.
This Release
------------
This release provides a suitable starting point for productization of secure
world boot and runtime firmware, executing in either the AArch32 or AArch64
execution state.
Users are encouraged to do their own security validation, including penetration
testing, on any secure world code derived from ARM Trusted Firmware.
### Functionality
* Initialization of the secure world (for example, exception vectors, control
registers, interrupt controller and interrupts for the platform), before
transitioning into the normal world at the Exception Level and Register
Width specified by the platform.
* Library support for CPU specific reset and power down sequences. This
includes support for errata workarounds.
* Drivers for both versions 2.0 and 3.0 of the ARM Generic Interrupt
Controller specifications (GICv2 and GICv3). The latter also enables GICv3
hardware systems that do not contain legacy GICv2 support.
* Drivers to enable standard initialization of ARM System IP, for example
Cache Coherent Interconnect (CCI), Cache Coherent Network (CCN), Network
Interconnect (NIC) and TrustZone Controller (TZC).
* SMC (Secure Monitor Call) handling, conforming to the [SMC Calling
Convention][SMCCC] using an EL3 runtime services framework.
* [PSCI] library support for the Secondary CPU Boot, CPU Hotplug, CPU Idle
and System Shutdown/Reset/Suspend use-cases.
This library is pre-integrated with the provided AArch64 EL3 Runtime
Software, and is also suitable for integration into other EL3 Runtime
Software.
* A minimal AArch32 Secure Payload to demonstrate [PSCI] library integration
on platforms with AArch32 EL3 Runtime Software.
* Secure Monitor library code such as world switching, EL1 context management
and interrupt routing.
When using the provided AArch64 EL3 Runtime Software, this must be
integrated with a Secure-EL1 Payload Dispatcher (SPD) component to
customize the interaction with a Secure-EL1 Payload (SP), for example a
Secure OS.
* A Test Secure-EL1 Payload and Dispatcher to demonstrate AArch64 Secure
Monitor functionality and Secure-EL1 interaction with PSCI.
* AArch64 SPDs for the [OP-TEE Secure OS] and [NVidia Trusted Little Kernel]
[NVidia TLK].
* A Trusted Board Boot implementation, conforming to all mandatory TBBR
requirements. This includes image authentication using certificates, a
Firmware Update (or recovery mode) boot flow, and packaging of the various
firmware images into a Firmware Image Package (FIP) to be loaded from
non-volatile storage.
The TBBR implementation is currently only supported in the AArch64 build.
* Support for alternative boot flows. Some platforms have their own boot
firmware and only require the AArch64 EL3 Runtime Software provided by this
project. Other platforms require minimal initialization before booting
into an arbitrary EL3 payload.
For a full description of functionality and implementation details, please
see the [Firmware Design] and supporting documentation. The [Change Log]
provides details of changes made since the last release.
### Platforms
The AArch64 build of this release has been tested on variants r0, r1 and r2
of the [Juno ARM Development Platform] [Juno] with [Linaro Release 16.06].
The AArch64 build of this release has been tested on the following ARM
[FVP]s (64-bit host machine only, with [Linaro Release 16.06]):
* `Foundation_Platform` (Version 10.1, Build 10.1.32)
* `FVP_Base_AEMv8A-AEMv8A` (Version 7.7, Build 0.8.7701)
* `FVP_Base_Cortex-A57x4-A53x4` (Version 7.7, Build 0.8.7701)
* `FVP_Base_Cortex-A57x1-A53x1` (Version 7.7, Build 0.8.7701)
* `FVP_Base_Cortex-A57x2-A53x4` (Version 7.7, Build 0.8.7701)
The AArch32 build of this release has been tested on the following ARM
[FVP]s (64-bit host machine only, with [Linaro Release 16.06]):
* `FVP_Base_AEMv8A-AEMv8A` (Version 7.7, Build 0.8.7701)
* `FVP_Base_Cortex-A32x4` (Version 10.1, Build 10.1.32)
The Foundation FVP can be downloaded free of charge. The Base FVPs can be
licensed from ARM: see [www.arm.com/fvp] [FVP].
This release also contains the following platform support:
* MediaTek MT6795 and MT8173 SoCs
* NVidia T210 and T132 SoCs
* QEMU emulator
* RockChip RK3368 and RK3399 SoCs
* Xilinx Zynq UltraScale + MPSoC
### Still to Come
* AArch32 TBBR support and ongoing TBBR alignment.
* More platform support.
* Ongoing support for new architectural features, CPUs and System IP.
* Ongoing [PSCI] alignment and feature support.
* Ongoing security hardening, optimization and quality improvements.
For a full list of detailed issues in the current code, please see the [Change
Log] and the [GitHub issue tracker].
Getting Started
---------------
Get the Trusted Firmware source code from
[GitHub](https://www.github.com/ARM-software/arm-trusted-firmware).
See the [User Guide] for instructions on how to install, build and use
the Trusted Firmware with the ARM [FVP]s.
See the [Firmware Design] for information on how the ARM Trusted Firmware works.
See the [Porting Guide] as well for information about how to use this
software on another ARMv8-A platform.
See the [Contributing Guidelines] for information on how to contribute to this
project and the [Acknowledgments] file for a list of contributors to the
project.
### Feedback and support
ARM welcomes any feedback on the Trusted Firmware. Please send feedback using
the [GitHub issue tracker].
ARM licensees may contact ARM directly via their partner managers.
- - - - - - - - - - - - - - - - - - - - - - - - - -
_Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved._
[License]: ./license.md "BSD license for ARM Trusted Firmware"
[Contributing Guidelines]: ./contributing.md "Guidelines for contributors"
[Acknowledgments]: ./acknowledgements.md "Contributor acknowledgments"
[Change Log]: ./docs/change-log.md
[User Guide]: ./docs/user-guide.md
[Firmware Design]: ./docs/firmware-design.md
[Porting Guide]: ./docs/porting-guide.md
[ARMv8-A]: http://www.arm.com/products/processors/armv8-architecture.php "ARMv8-A Architecture"
[FVP]: http://www.arm.com/fvp "ARM's Fixed Virtual Platforms"
[Juno]: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php "Juno ARM Development Platform"
[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf "Power State Coordination Interface PDD (ARM DEN 0022C)"
[SMCCC]: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html "SMC Calling Convention PDD (ARM DEN 0028A)"
[TEE-SMC]: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php "Secure Monitor and TEEs"
[GitHub issue tracker]: https://github.com/ARM-software/tf-issues/issues
[OP-TEE Secure OS]: https://github.com/OP-TEE/optee_os
[NVidia TLK]: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
[Linaro Release 16.06]: https://community.arm.com/docs/DOC-10952#jive_content_id_Linaro_Release_1606
readme.rst 0 → 100644
View file @ 7cefb56d
ARM Trusted Firmware - version 1.3
==================================
ARM Trusted Firmware provides a reference implementation of secure world
software for `ARMv8-A`_, including a `Secure Monitor`_ executing at
Exception Level 3 (EL3). It implements various ARM interface standards, such as
the Power State Coordination Interface (`PSCI`_), Trusted Board Boot Requirements
(TBBR, ARM DEN0006C-1) and `SMC Calling Convention`_. As far as possible
the code is designed for reuse or porting to other ARMv8-A model and hardware
platforms.
ARM will continue development in collaboration with interested parties to
provide a full reference implementation of PSCI, TBBR and Secure Monitor code
to the benefit of all developers working with ARMv8-A TrustZone technology.
License
-------
The software is provided under a BSD-3-Clause `license`_. Contributions to this
project are accepted under the same license with developer sign-off as
described in the `Contributing Guidelines`_.
This project contains code from other projects as listed below. The original
license text is included in those source files.
- The stdlib source code is derived from FreeBSD code.
- The libfdt source code is dual licensed. It is used by this project under
the terms of the BSD-2-Clause license.
This Release
------------
This release provides a suitable starting point for productization of secure
world boot and runtime firmware, executing in either the AArch32 or AArch64
execution state.
Users are encouraged to do their own security validation, including penetration
testing, on any secure world code derived from ARM Trusted Firmware.
Functionality
~~~~~~~~~~~~~
- Initialization of the secure world (for example, exception vectors, control
registers, interrupt controller and interrupts for the platform), before
transitioning into the normal world at the Exception Level and Register
Width specified by the platform.
- Library support for CPU specific reset and power down sequences. This
includes support for errata workarounds.
- Drivers for both versions 2.0 and 3.0 of the ARM Generic Interrupt
Controller specifications (GICv2 and GICv3). The latter also enables GICv3
hardware systems that do not contain legacy GICv2 support.
- Drivers to enable standard initialization of ARM System IP, for example
Cache Coherent Interconnect (CCI), Cache Coherent Network (CCN), Network
Interconnect (NIC) and TrustZone Controller (TZC).
- SMC (Secure Monitor Call) handling, conforming to the
`SMC Calling Convention`_ using an EL3 runtime services framework.
- `PSCI`_ library support for the Secondary CPU Boot, CPU Hotplug, CPU Idle
and System Shutdown/Reset/Suspend use-cases.
This library is pre-integrated with the provided AArch64 EL3 Runtime
Software, and is also suitable for integration into other EL3 Runtime
Software.
- A minimal AArch32 Secure Payload to demonstrate `PSCI`_ library integration
on platforms with AArch32 EL3 Runtime Software.
- Secure Monitor library code such as world switching, EL1 context management
and interrupt routing.
When using the provided AArch64 EL3 Runtime Software, this must be
integrated with a Secure-EL1 Payload Dispatcher (SPD) component to
customize the interaction with a Secure-EL1 Payload (SP), for example a
Secure OS.
- A Test Secure-EL1 Payload and Dispatcher to demonstrate AArch64 Secure
Monitor functionality and Secure-EL1 interaction with PSCI.
- AArch64 SPDs for the `OP-TEE Secure OS`_ and `NVidia Trusted Little Kernel`_.
- A Trusted Board Boot implementation, conforming to all mandatory TBBR
requirements. This includes image authentication using certificates, a
Firmware Update (or recovery mode) boot flow, and packaging of the various
firmware images into a Firmware Image Package (FIP) to be loaded from
non-volatile storage.
The TBBR implementation is currently only supported in the AArch64 build.
- Support for alternative boot flows. Some platforms have their own boot
firmware and only require the AArch64 EL3 Runtime Software provided by this
project. Other platforms require minimal initialization before booting
into an arbitrary EL3 payload.
For a full description of functionality and implementation details, please
see the `Firmware Design`_ and supporting documentation. The `Change Log`_
provides details of changes made since the last release.
Platforms
~~~~~~~~~
The AArch64 build of this release has been tested on variants r0, r1 and r2
of the `Juno ARM Development Platform`_ with `Linaro Release 16.06`_.
The AArch64 build of this release has been tested on the following ARM
`FVP`_\ s (64-bit host machine only, with `Linaro Release 16.06`_):
- ``Foundation_Platform`` (Version 10.1, Build 10.1.32)
- ``FVP_Base_AEMv8A-AEMv8A`` (Version 7.7, Build 0.8.7701)
- ``FVP_Base_Cortex-A57x4-A53x4`` (Version 7.7, Build 0.8.7701)
- ``FVP_Base_Cortex-A57x1-A53x1`` (Version 7.7, Build 0.8.7701)
- ``FVP_Base_Cortex-A57x2-A53x4`` (Version 7.7, Build 0.8.7701)
The AArch32 build of this release has been tested on the following ARM
`FVP`_\ s (64-bit host machine only, with `Linaro Release 16.06`_):
- ``FVP_Base_AEMv8A-AEMv8A`` (Version 7.7, Build 0.8.7701)
- ``FVP_Base_Cortex-A32x4`` (Version 10.1, Build 10.1.32)
The Foundation FVP can be downloaded free of charge. The Base FVPs can be
licensed from ARM: see `www.arm.com/fvp`_.
This release also contains the following platform support:
- MediaTek MT6795 and MT8173 SoCs
- NVidia T210 and T132 SoCs
- QEMU emulator
- RockChip RK3368 and RK3399 SoCs
- Xilinx Zynq UltraScale + MPSoC
Still to Come
~~~~~~~~~~~~~
- AArch32 TBBR support and ongoing TBBR alignment.
- More platform support.
- Ongoing support for new architectural features, CPUs and System IP.
- Ongoing `PSCI`_ alignment and feature support.
- Ongoing security hardening, optimization and quality improvements.
For a full list of detailed issues in the current code, please see the
`Change Log`_ and the `GitHub issue tracker`_.
Getting Started
---------------
Get the Trusted Firmware source code from
`GitHub`_.
See the `User Guide`_ for instructions on how to install, build and use
the Trusted Firmware with the ARM `FVP`_\ s.
See the `Firmware Design`_ for information on how the ARM Trusted Firmware works.
See the `Porting Guide`_ as well for information about how to use this
software on another ARMv8-A platform.
See the `Contributing Guidelines`_ for information on how to contribute to this
project and the `Acknowledgments`_ file for a list of contributors to the
project.
Feedback and support
~~~~~~~~~~~~~~~~~~~~
ARM welcomes any feedback on the Trusted Firmware. Please send feedback using
the `GitHub issue tracker`_.
ARM licensees may contact ARM directly via their partner managers.
--------------
*Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.*
.. _ARMv8-A: http://www.arm.com/products/processors/armv8-architecture.php
.. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
.. _license: ./license.rst
.. _Contributing Guidelines: ./contributing.rst
.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os
.. _NVidia Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
.. _Firmware Design: ./docs/firmware-design.rst
.. _Change Log: ./docs/change-log.rst
.. _Juno ARM Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php
.. _Linaro Release 16.06: https://community.arm.com/docs/DOC-10952#jive_content_id_Linaro_Release_1606
.. _FVP: http://www.arm.com/fvp
.. _www.arm.com/fvp: http://www.arm.com/fvp
.. _GitHub issue tracker: https://github.com/ARM-software/tf-issues/issues
.. _GitHub: https://www.github.com/ARM-software/arm-trusted-firmware
.. _User Guide: ./docs/user-guide.rst
.. _Porting Guide: ./docs/porting-guide.rst
.. _Acknowledgments: ./acknowledgements.rst
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment