diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
index 12b4b77da85629088bd86e9255bdfa6601908d91..cb57c9b6160f4d057755b48053ddb72194b5f311 100644
--- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
@@ -21,27 +21,27 @@ extern uint32_t tegra186_system_powerdn_state;
 /*******************************************************************************
  * Tegra186 SiP SMCs
  ******************************************************************************/
-#define TEGRA_SIP_NEW_VIDEOMEM_REGION			0x82000003
-#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE			0x82FFFE01
-#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE			0x82FFFF00
-#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO		0x82FFFF01
-#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME		0x82FFFF02
-#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS		0x82FFFF03
-#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS		0x82FFFF04
-#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED		0x82FFFF05
-#define TEGRA_SIP_MCE_CMD_ONLINE_CORE			0x82FFFF06
-#define TEGRA_SIP_MCE_CMD_CC3_CTRL			0x82FFFF07
-#define TEGRA_SIP_MCE_CMD_ECHO_DATA			0x82FFFF08
-#define TEGRA_SIP_MCE_CMD_READ_VERSIONS			0x82FFFF09
-#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES			0x82FFFF0A
-#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS	0x82FFFF0B
-#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA			0x82FFFF0C
-#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA		0x82FFFF0D
-#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE		0x82FFFF0E
-#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE		0x82FFFF0F
-#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC			0x82FFFF10
-#define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ		0x82FFFF11
-#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX			0x82FFFF12
+#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE			0xC2FFFE01
+#define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS		0xC2FFFE02
+#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE			0xC2FFFF00
+#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO		0xC2FFFF01
+#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME		0xC2FFFF02
+#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS		0xC2FFFF03
+#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS		0xC2FFFF04
+#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED		0xC2FFFF05
+#define TEGRA_SIP_MCE_CMD_ONLINE_CORE			0xC2FFFF06
+#define TEGRA_SIP_MCE_CMD_CC3_CTRL			0xC2FFFF07
+#define TEGRA_SIP_MCE_CMD_ECHO_DATA			0xC2FFFF08
+#define TEGRA_SIP_MCE_CMD_READ_VERSIONS			0xC2FFFF09
+#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES			0xC2FFFF0A
+#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS	0xC2FFFF0B
+#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA			0xC2FFFF0C
+#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA		0xC2FFFF0D
+#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE		0xC2FFFF0E
+#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE		0xC2FFFF0F
+#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC			0xC2FFFF10
+#define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ		0xC2FFFF11
+#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX			0xC2FFFF12
 
 /*******************************************************************************
  * This function is responsible for handling all T186 SiP calls
@@ -57,6 +57,12 @@ int plat_sip_handler(uint32_t smc_fid,
 {
 	int mce_ret;
 
+	/*
+	 * Convert SMC FID to SMC64 until the linux driver uses
+	 * SMC64 encoding.
+	 */
+	smc_fid |= (SMC_64 << FUNCID_CC_SHIFT);
+
 	switch (smc_fid) {
 
 	/*