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Commit 7fa35d06 authored by Manish Pandey's avatar Manish Pandey Committed by TrustedFirmware Code Review
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Merge changes Ib8502f9b,I388fd231,I7bd37912,I3a186ed7 into integration 

* changes:
  feat(plat/mediatek/mt8195): add SPM suspend driver
  feat(plat/mediatek/mt8195): support MCUSYS off when system suspend
  feat(plat/mediatek/mt8195): add support for PTP3
  fix(plat/mediatek/mt8195): extend MMU region size
parents 05f47b77 859e346b
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plat/mediatek/mt8195/drivers/spm/mt_spm_constraint.h 0 → 100644
View file @ 7fa35d06
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_CONSTRAINT_H
#define MT_SPM_CONSTRAINT_H
#include <mt_lp_rm.h>
#define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF (1U << 0)
#define MT_RM_CONSTRAINT_ALLOW_DRAM_S0 (1U << 1)
#define MT_RM_CONSTRAINT_ALLOW_DRAM_S1 (1U << 2)
#define MT_RM_CONSTRAINT_ALLOW_VCORE_LP (1U << 3)
#define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN (1U << 4)
#define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF (1U << 5)
#define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND (1U << 6)
#define MT_RM_CONSTRAINT_ALLOW_BBLPM (1U << 7)
#define MT_RM_CONSTRAINT_ALLOW_XO_UFS (1U << 8)
#define MT_RM_CONSTRAINT_ALLOW_GPS_STATE (1U << 9)
#define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE (1U << 10)
#define MT_SPM_RC_INVALID 0x0
#define MT_SPM_RC_VALID_SW (1U << 0)
#define MT_SPM_RC_VALID_FW (1U << 1)
#define MT_SPM_RC_VALID_RESIDNECY (1U << 2)
#define MT_SPM_RC_VALID_COND_CHECK (1U << 3)
#define MT_SPM_RC_VALID_COND_LATCH (1U << 4)
#define MT_SPM_RC_VALID_UFS_H8 (1U << 5)
#define MT_SPM_RC_VALID_FLIGHTMODE (1U << 6)
#define MT_SPM_RC_VALID_XSOC_BBLPM (1U << 7)
#define MT_SPM_RC_VALID_TRACE_EVENT (1U << 8)
#define MT_SPM_RC_VALID (MT_SPM_RC_VALID_SW)
#define IS_MT_RM_RC_READY(status) \
((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID)
#define MT_SPM_RC_BBLPM_MODE \
(MT_SPM_RC_VALID_UFS_H8 | \
MT_SPM_RC_VALID_FLIGHTMODE | \
MT_SPM_RC_VALID_XSOC_BBLPM)
#define IS_MT_SPM_RC_BBLPM_MODE(st) \
((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE)
struct constraint_status {
uint16_t id;
uint16_t valid;
uint32_t cond_block;
uint32_t enter_cnt;
struct mt_spm_cond_tables *cond_res;
};
enum MT_SPM_RM_RC_TYPE {
MT_RM_CONSTRAINT_ID_BUS26M,
MT_RM_CONSTRAINT_ID_SYSPLL,
MT_RM_CONSTRAINT_ID_DRAM,
MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO,
MT_RM_CONSTRAINT_ID_ALL,
};
#endif /* MT_SPM_CONSTRAINT_H */
plat/mediatek/mt8195/drivers/spm/mt_spm_idle.c 0 → 100644
View file @ 7fa35d06
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <lib/mmio.h>
#include <mt_spm.h>
#include <mt_spm_conservation.h>
#include <mt_spm_idle.h>
#include <mt_spm_internal.h>
#include <mt_spm_reg.h>
#include <mt_spm_resource_req.h>
#include <plat_pm.h>
#define __WAKE_SRC_FOR_IDLE_COMMON__ \
(R12_PCM_TIMER | \
R12_KP_IRQ_B | \
R12_APWDT_EVENT_B | \
R12_APXGPT1_EVENT_B | \
R12_CONN2AP_SPM_WAKEUP_B | \
R12_EINT_EVENT_B | \
R12_CONN_WDT_IRQ_B | \
R12_CCIF0_EVENT_B | \
R12_SSPM2SPM_WAKEUP_B | \
R12_SCP2SPM_WAKEUP_B | \
R12_ADSP2SPM_WAKEUP_B | \
R12_USBX_CDSC_B | \
R12_USBX_POWERDWN_B | \
R12_SYS_TIMER_EVENT_B | \
R12_EINT_EVENT_SECURE_B | \
R12_AFE_IRQ_MCU_B | \
R12_SYS_CIRQ_IRQ_B | \
R12_MD2AP_PEER_EVENT_B | \
R12_MD1_WDT_B | \
R12_CLDMA_EVENT_B | \
R12_REG_CPU_WAKEUP | \
R12_APUSYS_WAKE_HOST_B)
#if defined(CFG_MICROTRUST_TEE_SUPPORT)
#define WAKE_SRC_FOR_IDLE (__WAKE_SRC_FOR_IDLE_COMMON__)
#else
#define WAKE_SRC_FOR_IDLE \
(__WAKE_SRC_FOR_IDLE_COMMON__ | \
R12_SEJ_EVENT_B)
#endif
static struct pwr_ctrl idle_spm_pwr = {
.wake_src = WAKE_SRC_FOR_IDLE,
/* SPM_AP_STANDBY_CON */
/* [0] */
.reg_wfi_op = 0,
/* [1] */
.reg_wfi_type = 0,
/* [2] */
.reg_mp0_cputop_idle_mask = 0,
/* [3] */
.reg_mp1_cputop_idle_mask = 0,
/* [4] */
.reg_mcusys_idle_mask = 0,
/* [25] */
.reg_md_apsrc_1_sel = 0,
/* [26] */
.reg_md_apsrc_0_sel = 0,
/* [29] */
.reg_conn_apsrc_sel = 0,
/* SPM_SRC_REQ */
/* [0] */
.reg_spm_apsrc_req = 0,
/* [1] */
.reg_spm_f26m_req = 1,
/* [3] */
.reg_spm_infra_req = 1,
/* [4] */
.reg_spm_vrf18_req = 0,
/* [7] FIXME: default disable HW Auto S1 */
.reg_spm_ddr_en_req = 1,
/* [8] */
.reg_spm_dvfs_req = 0,
/* [9] */
.reg_spm_sw_mailbox_req = 0,
/* [10] */
.reg_spm_sspm_mailbox_req = 0,
/* [11] */
.reg_spm_adsp_mailbox_req = 0,
/* [12] */
.reg_spm_scp_mailbox_req = 0,
/* SPM_SRC_MASK */
/* [0] */
.reg_sspm_srcclkena_0_mask_b = 1,
/* [1] */
.reg_sspm_infra_req_0_mask_b = 1,
/* [2] */
.reg_sspm_apsrc_req_0_mask_b = 1,
/* [3] */
.reg_sspm_vrf18_req_0_mask_b = 1,
/* [4] */
.reg_sspm_ddr_en_0_mask_b = 1,
/* [5] */
.reg_scp_srcclkena_mask_b = 1,
/* [6] */
.reg_scp_infra_req_mask_b = 1,
/* [7] */
.reg_scp_apsrc_req_mask_b = 1,
/* [8] */
.reg_scp_vrf18_req_mask_b = 1,
/* [9] */
.reg_scp_ddr_en_mask_b = 1,
/* [10] */
.reg_audio_dsp_srcclkena_mask_b = 1,
/* [11] */
.reg_audio_dsp_infra_req_mask_b = 1,
/* [12] */
.reg_audio_dsp_apsrc_req_mask_b = 1,
/* [13] */
.reg_audio_dsp_vrf18_req_mask_b = 1,
/* [14] */
.reg_audio_dsp_ddr_en_mask_b = 1,
/* [15] */
.reg_apu_srcclkena_mask_b = 1,
/* [16] */
.reg_apu_infra_req_mask_b = 1,
/* [17] */
.reg_apu_apsrc_req_mask_b = 1,
/* [18] */
.reg_apu_vrf18_req_mask_b = 1,
/* [19] */
.reg_apu_ddr_en_mask_b = 1,
/* [20] */
.reg_cpueb_srcclkena_mask_b = 1,
/* [21] */
.reg_cpueb_infra_req_mask_b = 1,
/* [22] */
.reg_cpueb_apsrc_req_mask_b = 1,
/* [23] */
.reg_cpueb_vrf18_req_mask_b = 1,
/* [24] */
.reg_cpueb_ddr_en_mask_b = 1,
/* [25] */
.reg_bak_psri_srcclkena_mask_b = 0,
/* [26] */
.reg_bak_psri_infra_req_mask_b = 0,
/* [27] */
.reg_bak_psri_apsrc_req_mask_b = 0,
/* [28] */
.reg_bak_psri_vrf18_req_mask_b = 0,
/* [29] */
.reg_bak_psri_ddr_en_mask_b = 0,
/* SPM_SRC2_MASK */
/* [0] */
.reg_msdc0_srcclkena_mask_b = 1,
/* [1] */
.reg_msdc0_infra_req_mask_b = 1,
/* [2] */
.reg_msdc0_apsrc_req_mask_b = 1,
/* [3] */
.reg_msdc0_vrf18_req_mask_b = 1,
/* [4] */
.reg_msdc0_ddr_en_mask_b = 1,
/* [5] */
.reg_msdc1_srcclkena_mask_b = 1,
/* [6] */
.reg_msdc1_infra_req_mask_b = 1,
/* [7] */
.reg_msdc1_apsrc_req_mask_b = 1,
/* [8] */
.reg_msdc1_vrf18_req_mask_b = 1,
/* [9] */
.reg_msdc1_ddr_en_mask_b = 1,
/* [10] */
.reg_msdc2_srcclkena_mask_b = 1,
/* [11] */
.reg_msdc2_infra_req_mask_b = 1,
/* [12] */
.reg_msdc2_apsrc_req_mask_b = 1,
/* [13] */
.reg_msdc2_vrf18_req_mask_b = 1,
/* [14] */
.reg_msdc2_ddr_en_mask_b = 1,
/* [15] */
.reg_ufs_srcclkena_mask_b = 1,
/* [16] */
.reg_ufs_infra_req_mask_b = 1,
/* [17] */
.reg_ufs_apsrc_req_mask_b = 1,
/* [18] */
.reg_ufs_vrf18_req_mask_b = 1,
/* [19] */
.reg_ufs_ddr_en_mask_b = 1,
/* [20] */
.reg_usb_srcclkena_mask_b = 1,
/* [21] */
.reg_usb_infra_req_mask_b = 1,
/* [22] */
.reg_usb_apsrc_req_mask_b = 1,
/* [23] */
.reg_usb_vrf18_req_mask_b = 1,
/* [24] */
.reg_usb_ddr_en_mask_b = 1,
/* [25] */
.reg_pextp_p0_srcclkena_mask_b = 1,
/* [26] */
.reg_pextp_p0_infra_req_mask_b = 1,
/* [27] */
.reg_pextp_p0_apsrc_req_mask_b = 1,
/* [28] */
.reg_pextp_p0_vrf18_req_mask_b = 1,
/* [29] */
.reg_pextp_p0_ddr_en_mask_b = 1,
/* SPM_SRC3_MASK */
/* [0] */
.reg_pextp_p1_srcclkena_mask_b = 1,
/* [1] */
.reg_pextp_p1_infra_req_mask_b = 1,
/* [2] */
.reg_pextp_p1_apsrc_req_mask_b = 1,
/* [3] */
.reg_pextp_p1_vrf18_req_mask_b = 1,
/* [4] */
.reg_pextp_p1_ddr_en_mask_b = 1,
/* [5] */
.reg_gce0_infra_req_mask_b = 1,
/* [6] */
.reg_gce0_apsrc_req_mask_b = 1,
/* [7] */
.reg_gce0_vrf18_req_mask_b = 1,
/* [8] */
.reg_gce0_ddr_en_mask_b = 1,
/* [9] */
.reg_gce1_infra_req_mask_b = 1,
/* [10] */
.reg_gce1_apsrc_req_mask_b = 1,
/* [11] */
.reg_gce1_vrf18_req_mask_b = 1,
/* [12] */
.reg_gce1_ddr_en_mask_b = 1,
/* [13] */
.reg_spm_srcclkena_reserved_mask_b = 1,
/* [14] */
.reg_spm_infra_req_reserved_mask_b = 1,
/* [15] */
.reg_spm_apsrc_req_reserved_mask_b = 1,
/* [16] */
.reg_spm_vrf18_req_reserved_mask_b = 1,
/* [17] */
.reg_spm_ddr_en_reserved_mask_b = 1,
/* [18] */
.reg_disp0_apsrc_req_mask_b = 1,
/* [19] */
.reg_disp0_ddr_en_mask_b = 1,
/* [20] */
.reg_disp1_apsrc_req_mask_b = 1,
/* [21] */
.reg_disp1_ddr_en_mask_b = 1,
/* [22] */
.reg_disp2_apsrc_req_mask_b = 1,
/* [23] */
.reg_disp2_ddr_en_mask_b = 1,
/* [24] */
.reg_disp3_apsrc_req_mask_b = 1,
/* [25] */
.reg_disp3_ddr_en_mask_b = 1,
/* [26] */
.reg_infrasys_apsrc_req_mask_b = 0,
/* [27] */
.reg_infrasys_ddr_en_mask_b = 1,
/* [28] */
.reg_cg_check_srcclkena_mask_b = 1,
/* [29] */
.reg_cg_check_apsrc_req_mask_b = 1,
/* [30] */
.reg_cg_check_vrf18_req_mask_b = 1,
/* [31] */
.reg_cg_check_ddr_en_mask_b = 1,
/* SPM_SRC4_MASK */
/* [8:0] */
.reg_mcusys_merge_apsrc_req_mask_b = 0x17,
/* [17:9] */
.reg_mcusys_merge_ddr_en_mask_b = 0x17,
/* [19:18] */
.reg_dramc_md32_infra_req_mask_b = 0,
/* [21:20] */
.reg_dramc_md32_vrf18_req_mask_b = 0,
/* [23:22] */
.reg_dramc_md32_ddr_en_mask_b = 0,
/* [24] */
.reg_dvfsrc_event_trigger_mask_b = 1,
/* SPM_WAKEUP_EVENT_MASK2 */
/* [3:0] */
.reg_sc_sw2spm_wakeup_mask_b = 0,
/* [4] */
.reg_sc_adsp2spm_wakeup_mask_b = 0,
/* [8:5] */
.reg_sc_sspm2spm_wakeup_mask_b = 0,
/* [9] */
.reg_sc_scp2spm_wakeup_mask_b = 0,
/* [10] */
.reg_csyspwrup_ack_mask = 0,
/* [11] */
.reg_csyspwrup_req_mask = 1,
/* SPM_WAKEUP_EVENT_MASK */
/* [31:0] */
.reg_wakeup_event_mask = 0xC1282203,
/* SPM_WAKEUP_EVENT_EXT_MASK */
/* [31:0] */
.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
};
struct spm_lp_scen idle_spm_lp = {
.pwrctrl = &idle_spm_pwr,
};
int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
spm_idle_conduct fn)
{
unsigned int src_req = 0;
if (fn != NULL) {
fn(&idle_spm_lp, &src_req);
}
return spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req);
}
void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
struct wake_status **status)
{
spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status);
}
void mt_spm_idle_generic_init(void)
{
spm_conservation_pwrctrl_init(idle_spm_lp.pwrctrl);
}
plat/mediatek/mt8195/drivers/spm/mt_spm_idle.h 0 → 100644
View file @ 7fa35d06
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_IDLE_H
#define MT_SPM_IDLE_H
typedef void (*spm_idle_conduct)(struct spm_lp_scen *spm_lp,
unsigned int *resource_req);
int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
spm_idle_conduct fn);
void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
struct wake_status **status);
void mt_spm_idle_generic_init(void);
#endif /* MT_SPM_IDLE_H */
plat/mediatek/mt8195/drivers/spm/mt_spm_internal.c 0 → 100644
View file @ 7fa35d06
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stddef.h>
#include <assert.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <mt_spm.h>
#include <mt_spm_internal.h>
#include <mt_spm_pmic_wrap.h>
#include <mt_spm_reg.h>
#include <mt_spm_resource_req.h>
#include <platform_def.h>
#include <plat_pm.h>
/**************************************
* Define and Declare
**************************************/
#define ROOT_CORE_ADDR_OFFSET 0x20000000
#define SPM_WAKEUP_EVENT_MASK_CLEAN_MASK 0xefffffff
#define SPM_INIT_DONE_US 20
static unsigned int mt_spm_bblpm_cnt;
const char *wakeup_src_str[32] = {
[0] = "R12_PCM_TIMER",
[1] = "R12_RESERVED_DEBUG_B",
[2] = "R12_KP_IRQ_B",
[3] = "R12_APWDT_EVENT_B",
[4] = "R12_APXGPT1_EVENT_B",
[5] = "R12_MSDC_WAKEUP_B",
[6] = "R12_EINT_EVENT_B",
[7] = "R12_IRRX_WAKEUP_B",
[8] = "R12_SBD_INTR_WAKEUP_B",
[9] = "R12_RESERVE0",
[10] = "R12_SC_SSPM2SPM_WAKEUP_B",
[11] = "R12_SC_SCP2SPM_WAKEUP_B",
[12] = "R12_SC_ADSP2SPM_WAKEUP_B",
[13] = "R12_WDT_WAKEUP_B",
[14] = "R12_USB_U2_B",
[15] = "R12_USB_TOP_B",
[16] = "R12_SYS_TIMER_EVENT_B",
[17] = "R12_EINT_EVENT_SECURE_B",
[18] = "R12_ECE_INT_HDMI_B",
[19] = "R12_RESERVE1",
[20] = "R12_AFE_IRQ_MCU_B",
[21] = "R12_THERM_CTRL_EVENT_B",
[22] = "R12_SCP_CIRQ_IRQ_B",
[23] = "R12_NNA2INFRA_WAKEUP_B",
[24] = "R12_CSYSPWREQ_B",
[25] = "R12_RESERVE2",
[26] = "R12_PCIE_WAKEUPEVENT_B",
[27] = "R12_SEJ_EVENT_B",
[28] = "R12_SPM_CPU_WAKEUPEVENT_B",
[29] = "R12_APUSYS",
[30] = "R12_RESERVE3",
[31] = "R12_RESERVE4",
};
/**************************************
* Function and API
**************************************/
wake_reason_t __spm_output_wake_reason(int state_id,
const struct wake_status *wakesta)
{
uint32_t i, bk_vtcxo_dur, spm_26m_off_pct = 0U;
wake_reason_t wr = WR_UNKNOWN;
if (wakesta == NULL) {
return WR_UNKNOWN;
}
if (wakesta->abort != 0U) {
ERROR("spmfw flow is aborted: 0x%x, timer_out = %u\n",
wakesta->abort, wakesta->timer_out);
} else {
for (i = 0U; i < 32U; i++) {
if ((wakesta->r12 & (1U << i)) != 0U) {
INFO("wake up by %s, timer_out = %u\n",
wakeup_src_str[i], wakesta->timer_out);
wr = WR_WAKE_SRC;
break;
}
}
}
INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n",
wakesta->r12, wakesta->r12_ext, wakesta->r13, wakesta->debug_flag,
wakesta->debug_flag1);
INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n",
wakesta->raw_sta, wakesta->md32pcm_wakeup_sta,
wakesta->md32pcm_event_sta, wakesta->idle_sta,
wakesta->cg_check_sta);
INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n",
wakesta->req_sta0, wakesta->req_sta1, wakesta->req_sta2,
wakesta->req_sta3, wakesta->req_sta4, wakesta->isr);
INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n",
wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2);
INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n",
wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta);
INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n",
wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1,
wakesta->b_sw_flag0, wakesta->b_sw_flag1, wakesta->src_req);
INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n",
wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L),
mmio_read_32(SYS_TIMER_VALUE_H));
if (wakesta->timer_out != 0U) {
bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR);
spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->timer_out;
INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct);
}
return wr;
}
void __spm_set_cpu_status(unsigned int cpu)
{
uint32_t root_core_addr;
if (cpu < 8U) {
mmio_write_32(ROOT_CPUTOP_ADDR, (1U << cpu));
root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4);
root_core_addr += ROOT_CORE_ADDR_OFFSET;
mmio_write_32(ROOT_CORE_ADDR, root_core_addr);
/* Notify MCUPM that preferred cpu wakeup */
mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu);
} else {
ERROR("%s: error cpu number %d\n", __func__, cpu);
}
}
void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
unsigned int resource_usage)
{
uint8_t apsrc_req = ((resource_usage & MT_SPM_DRAM_S0) != 0U) ?
1 : pwrctrl->reg_spm_apsrc_req;
uint8_t ddr_en_req = ((resource_usage & MT_SPM_DRAM_S1) != 0U) ?
1 : pwrctrl->reg_spm_ddr_en_req;
uint8_t vrf18_req = ((resource_usage & MT_SPM_SYSPLL) != 0U) ?
1 : pwrctrl->reg_spm_vrf18_req;
uint8_t infra_req = ((resource_usage & MT_SPM_INFRA) != 0U) ?
1 : pwrctrl->reg_spm_infra_req;
uint8_t f26m_req = ((resource_usage &
(MT_SPM_26M | MT_SPM_XO_FPM)) != 0U) ?
1 : pwrctrl->reg_spm_f26m_req;
mmio_write_32(SPM_SRC_REQ,
((apsrc_req & 0x1) << 0) |
((f26m_req & 0x1) << 1) |
((infra_req & 0x1) << 3) |
((vrf18_req & 0x1) << 4) |
((ddr_en_req & 0x1) << 7) |
((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
}
void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
{
/* Auto-gen Start */
/* SPM_AP_STANDBY_CON */
mmio_write_32(SPM_AP_STANDBY_CON,
((pwrctrl->reg_wfi_op & 0x1) << 0) |
((pwrctrl->reg_wfi_type & 0x1) << 1) |
((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
/* SPM_SRC_REQ */
mmio_write_32(SPM_SRC_REQ,
((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
/* SPM_SRC_MASK */
mmio_write_32(SPM_SRC_MASK,
((pwrctrl->reg_sspm_srcclkena_0_mask_b & 0x1) << 0) |
((pwrctrl->reg_sspm_infra_req_0_mask_b & 0x1) << 1) |
((pwrctrl->reg_sspm_apsrc_req_0_mask_b & 0x1) << 2) |
((pwrctrl->reg_sspm_vrf18_req_0_mask_b & 0x1) << 3) |
((pwrctrl->reg_sspm_ddr_en_0_mask_b & 0x1) << 4) |
((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 5) |
((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 6) |
((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 7) |
((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 8) |
((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 9) |
((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 10) |
((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 11) |
((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 12) |
((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 13) |
((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 14) |
((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 15) |
((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 16) |
((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 17) |
((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 18) |
((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 19) |
((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 20) |
((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 21) |
((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 22) |
((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 23) |
((pwrctrl->reg_cpueb_ddr_en_mask_b & 0x1) << 24) |
((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 25) |
((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 26) |
((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 27) |
((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 28) |
((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 29));
/* SPM_SRC2_MASK */
mmio_write_32(SPM_SRC2_MASK,
((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 0) |
((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 1) |
((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 2) |
((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 3) |
((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 4) |
((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 5) |
((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 6) |
((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 7) |
((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 8) |
((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 9) |
((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 10) |
((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 11) |
((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 12) |
((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 13) |
((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 14) |
((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 15) |
((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 16) |
((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 17) |
((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 18) |
((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 19) |
((pwrctrl->reg_usb_srcclkena_mask_b & 0x1) << 20) |
((pwrctrl->reg_usb_infra_req_mask_b & 0x1) << 21) |
((pwrctrl->reg_usb_apsrc_req_mask_b & 0x1) << 22) |
((pwrctrl->reg_usb_vrf18_req_mask_b & 0x1) << 23) |
((pwrctrl->reg_usb_ddr_en_mask_b & 0x1) << 24) |
((pwrctrl->reg_pextp_p0_srcclkena_mask_b & 0x1) << 25) |
((pwrctrl->reg_pextp_p0_infra_req_mask_b & 0x1) << 26) |
((pwrctrl->reg_pextp_p0_apsrc_req_mask_b & 0x1) << 27) |
((pwrctrl->reg_pextp_p0_vrf18_req_mask_b & 0x1) << 28) |
((pwrctrl->reg_pextp_p0_ddr_en_mask_b & 0x1) << 29));
/* SPM_SRC3_MASK */
mmio_write_32(SPM_SRC3_MASK,
((pwrctrl->reg_pextp_p1_srcclkena_mask_b & 0x1) << 0) |
((pwrctrl->reg_pextp_p1_infra_req_mask_b & 0x1) << 1) |
((pwrctrl->reg_pextp_p1_apsrc_req_mask_b & 0x1) << 2) |
((pwrctrl->reg_pextp_p1_vrf18_req_mask_b & 0x1) << 3) |
((pwrctrl->reg_pextp_p1_ddr_en_mask_b & 0x1) << 4) |
((pwrctrl->reg_gce0_infra_req_mask_b & 0x1) << 5) |
((pwrctrl->reg_gce0_apsrc_req_mask_b & 0x1) << 6) |
((pwrctrl->reg_gce0_vrf18_req_mask_b & 0x1) << 7) |
((pwrctrl->reg_gce0_ddr_en_mask_b & 0x1) << 8) |
((pwrctrl->reg_gce1_infra_req_mask_b & 0x1) << 9) |
((pwrctrl->reg_gce1_apsrc_req_mask_b & 0x1) << 10) |
((pwrctrl->reg_gce1_vrf18_req_mask_b & 0x1) << 11) |
((pwrctrl->reg_gce1_ddr_en_mask_b & 0x1) << 12) |
((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 13) |
((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 14) |
((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 15) |
((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 16) |
((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 17) |
((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 18) |
((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 19) |
((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 20) |
((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 21) |
((pwrctrl->reg_disp2_apsrc_req_mask_b & 0x1) << 22) |
((pwrctrl->reg_disp2_ddr_en_mask_b & 0x1) << 23) |
((pwrctrl->reg_disp3_apsrc_req_mask_b & 0x1) << 24) |
((pwrctrl->reg_disp3_ddr_en_mask_b & 0x1) << 25) |
((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 26) |
((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 27));
/* Mask MCUSYS request since SOC HW would check it */
mmio_write_32(SPM_SRC4_MASK, 0x1fc0000);
/* SPM_WAKEUP_EVENT_MASK */
mmio_write_32(SPM_WAKEUP_EVENT_MASK,
((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
/* SPM_WAKEUP_EVENT_EXT_MASK */
mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
/* Auto-gen End */
}
void __spm_disable_pcm_timer(void)
{
mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
}
void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
{
uint32_t val, mask;
/* toggle event counter clear */
mmio_setbits_32(PCM_CON1,
SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
/* toggle for reset SYS TIMER start point */
mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
if (pwrctrl->timer_val_cust == 0U) {
val = pwrctrl->timer_val;
} else {
val = pwrctrl->timer_val_cust;
}
mmio_write_32(PCM_TIMER_VAL, val);
mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB);
/* unmask AP wakeup source */
if (pwrctrl->wake_src_cust == 0U) {
mask = pwrctrl->wake_src;
} else {
mask = pwrctrl->wake_src_cust;
}
mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
/* unmask SPM ISR (keep TWAM setting) */
mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX);
/* toggle event counter clear */
mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB,
SPM_REGWR_CFG_KEY);
/* toggle for reset SYS TIMER start point */
mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
}
void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
{
/* set PCM flags and data */
if (pwrctrl->pcm_flags_cust_clr != 0U) {
pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
}
if (pwrctrl->pcm_flags_cust_set != 0U) {
pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
}
if (pwrctrl->pcm_flags1_cust_clr != 0U) {
pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
}
if (pwrctrl->pcm_flags1_cust_set != 0U) {
pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
}
mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);
}
void __spm_get_wakeup_status(struct wake_status *wakesta,
unsigned int ext_status)
{
wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA);
wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0);
wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1);
wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2);
wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3);
wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4);
wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) {
wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE |
SPM_DBG_DEBUG_IDX_DDREN_SLEEP);
mmio_write_32(PCM_WDT_LATCH_SPARE_0,
wakesta->tr.comm.debug_flag);
}
wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
/* record below spm info for debug */
wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA);
wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA);
wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA);
wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA);
wakesta->src_req = mmio_read_32(SPM_SRC_REQ);
/* backup of SPM_WAKEUP_MISC */
wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC);
/* get sleep time, backup of PCM_TIMER_OUT */
wakesta->timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
/* get other SYS and co-clock status */
wakesta->r13 = mmio_read_32(PCM_REG13_DATA);
wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
wakesta->req_sta0 = mmio_read_32(SRC_REQ_STA_0);
wakesta->req_sta1 = mmio_read_32(SRC_REQ_STA_1);
wakesta->req_sta2 = mmio_read_32(SRC_REQ_STA_2);
wakesta->req_sta3 = mmio_read_32(SRC_REQ_STA_3);
wakesta->req_sta4 = mmio_read_32(SRC_REQ_STA_4);
/* get HW CG check status */
wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA);
/* get debug flag for PCM execution check */
wakesta->debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
wakesta->debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
/* get backup SW flag status */
wakesta->b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
wakesta->b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2);
wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3);
wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4);
wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5);
wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6);
/* get ISR status */
wakesta->isr = mmio_read_32(SPM_IRQ_STA);
/* get SW flag status */
wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0);
wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1);
/* get CLK SETTLE */
wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE);
/* check abort */
wakesta->abort = (wakesta->debug_flag & DEBUG_ABORT_MASK) |
(wakesta->debug_flag1 & DEBUG_ABORT_MASK_1);
}
void __spm_clean_after_wakeup(void)
{
mmio_write_32(SPM_BK_WAKE_EVENT,
mmio_read_32(SPM_WAKEUP_STA) |
mmio_read_32(SPM_BK_WAKE_EVENT));
mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0);
/*
* clean wakeup event raw status (for edge trigger event)
* bit[28] for cpu wake up event
*/
mmio_write_32(SPM_WAKEUP_EVENT_MASK, SPM_WAKEUP_EVENT_MASK_CLEAN_MASK);
/* clean ISR status (except TWAM) */
mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
}
void __spm_set_pcm_wdt(int en)
{
mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB,
SPM_REGWR_CFG_KEY);
if (en == 1) {
mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB,
SPM_REGWR_CFG_KEY);
if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) {
mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
}
mmio_write_32(PCM_WDT_VAL,
mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
mmio_setbits_32(PCM_CON1,
SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB);
}
}
void __spm_send_cpu_wakeup_event(void)
{
/* SPM will clear SPM_CPU_WAKEUP_EVENT */
mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
}
void __spm_ext_int_wakeup_req_clr(void)
{
mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR));
/* Clear spm2mcupm wakeup interrupt status */
mmio_write_32(SPM2CPUEB_CON, 0);
}
void __spm_xo_soc_bblpm(int en)
{
if (en == 1) {
mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
RC_SW_SRCLKEN_FPM, RC_SW_SRCLKEN_RC);
assert(mt_spm_bblpm_cnt == 0);
mt_spm_bblpm_cnt += 1;
} else {
mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
RC_SW_SRCLKEN_RC, RC_SW_SRCLKEN_FPM);
mt_spm_bblpm_cnt -= 1;
}
}
void __spm_hw_s1_state_monitor(int en, unsigned int *status)
{
unsigned int reg;
reg = mmio_read_32(SPM_ACK_CHK_CON_3);
if (en == 1) {
reg &= ~SPM_ACK_CHK_3_CON_CLR_ALL;
mmio_write_32(SPM_ACK_CHK_CON_3, reg);
reg |= SPM_ACK_CHK_3_CON_EN;
mmio_write_32(SPM_ACK_CHK_CON_3, reg);
} else {
if (((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) &&
(status != NULL)) {
*status |= SPM_INTERNAL_STATUS_HW_S1;
}
mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN,
SPM_ACK_CHK_3_CON_HW_MODE_TRIG |
SPM_ACK_CHK_3_CON_CLR_ALL);
}
}
plat/mediatek/mt8195/drivers/spm/mt_spm_internal.h 0 → 100644
View file @ 7fa35d06
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_INTERNAL_H
#define MT_SPM_INTERNAL_H
#include "mt_spm.h"
/**************************************
* Config and Parameter
**************************************/
#define POWER_ON_VAL0_DEF 0x0000F100
#define POWER_ON_VAL1_DEF 0x80015860
#define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */
#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
/**************************************
* Define and Declare
**************************************/
/* PCM_PWR_IO_EN */
#define PCM_PWRIO_EN_R0 (1U << 0)
#define PCM_PWRIO_EN_R7 (1U << 7)
#define PCM_RF_SYNC_R0 (1U << 16)
#define PCM_RF_SYNC_R6 (1U << 22)
#define PCM_RF_SYNC_R7 (1U << 23)
/* SPM_SWINT */
#define PCM_SW_INT0 (1U << 0)
#define PCM_SW_INT1 (1U << 1)
#define PCM_SW_INT2 (1U << 2)
#define PCM_SW_INT3 (1U << 3)
#define PCM_SW_INT4 (1U << 4)
#define PCM_SW_INT5 (1U << 5)
#define PCM_SW_INT6 (1U << 6)
#define PCM_SW_INT7 (1U << 7)
#define PCM_SW_INT8 (1U << 8)
#define PCM_SW_INT9 (1U << 9)
#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
PCM_SW_INT0)
/* SPM_AP_STANDBY_CON */
#define WFI_OP_AND 1
#define WFI_OP_OR 0
/* SPM_IRQ_MASK */
#define ISRM_TWAM (1U << 2)
#define ISRM_PCM_RETURN (1U << 3)
#define ISRM_RET_IRQ0 (1U << 8)
#define ISRM_RET_IRQ1 (1U << 9)
#define ISRM_RET_IRQ2 (1U << 10)
#define ISRM_RET_IRQ3 (1U << 11)
#define ISRM_RET_IRQ4 (1U << 12)
#define ISRM_RET_IRQ5 (1U << 13)
#define ISRM_RET_IRQ6 (1U << 14)
#define ISRM_RET_IRQ7 (1U << 15)
#define ISRM_RET_IRQ8 (1U << 16)
#define ISRM_RET_IRQ9 (1U << 17)
#define ISRM_RET_IRQ_AUX ((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \
(ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \
(ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \
(ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \
(ISRM_RET_IRQ1))
#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX)
#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
/* SPM_IRQ_STA */
#define ISRS_TWAM (1U << 2)
#define ISRS_PCM_RETURN (1U << 3)
#define ISRC_TWAM ISRS_TWAM
#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN
#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
/* SPM_WAKEUP_MISC */
#define WAKE_MISC_GIC_WAKEUP 0x3FF
#define WAKE_MISC_DVFSRC_IRQ DVFSRC_IRQ_LSB
#define WAKE_MISC_REG_CPU_WAKEUP SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB
#define WAKE_MISC_PCM_TIMER_EVENT PCM_TIMER_EVENT_LSB
#define WAKE_MISC_PMIC_OUT_B ((1U << 19) | (1U << 20))
#define WAKE_MISC_TWAM_IRQ_B TWAM_IRQ_B_LSB
#define WAKE_MISC_PMSR_IRQ_B_SET0 PMSR_IRQ_B_SET0_LSB
#define WAKE_MISC_PMSR_IRQ_B_SET1 PMSR_IRQ_B_SET1_LSB
#define WAKE_MISC_PMSR_IRQ_B_SET2 PMSR_IRQ_B_SET2_LSB
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0 SPM_ACK_CHK_WAKEUP_0_LSB
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1 SPM_ACK_CHK_WAKEUP_1_LSB
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2 SPM_ACK_CHK_WAKEUP_2_LSB
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3 SPM_ACK_CHK_WAKEUP_3_LSB
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL SPM_ACK_CHK_WAKEUP_ALL_LSB
#define WAKE_MISC_PMIC_IRQ_ACK PMIC_IRQ_ACK_LSB
#define WAKE_MISC_PMIC_SCP_IRQ PMIC_SCP_IRQ_LSB
/* ABORT MASK for DEBUG FOORTPRINT */
#define DEBUG_ABORT_MASK \
(SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC | \
SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
#define DEBUG_ABORT_MASK_1 \
(SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT | \
SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT | \
SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT | \
SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT | \
SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT | \
SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT | \
SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
#define MCUPM_MBOX_WAKEUP_CPU 0x0C55FD10
struct pwr_ctrl {
uint32_t pcm_flags;
uint32_t pcm_flags_cust;
uint32_t pcm_flags_cust_set;
uint32_t pcm_flags_cust_clr;
uint32_t pcm_flags1;
uint32_t pcm_flags1_cust;
uint32_t pcm_flags1_cust_set;
uint32_t pcm_flags1_cust_clr;
uint32_t timer_val;
uint32_t timer_val_cust;
uint32_t timer_val_ramp_en;
uint32_t timer_val_ramp_en_sec;
uint32_t wake_src;
uint32_t wake_src_cust;
uint8_t wdt_disable;
/* SPM_AP_STANDBY_CON */
uint8_t reg_wfi_op;
uint8_t reg_wfi_type;
uint8_t reg_mp0_cputop_idle_mask;
uint8_t reg_mp1_cputop_idle_mask;
uint8_t reg_mcusys_idle_mask;
uint8_t reg_md_apsrc_1_sel;
uint8_t reg_md_apsrc_0_sel;
uint8_t reg_conn_apsrc_sel;
/* SPM_SRC_REQ */
uint8_t reg_spm_apsrc_req;
uint8_t reg_spm_f26m_req;
uint8_t reg_spm_infra_req;
uint8_t reg_spm_vrf18_req;
uint8_t reg_spm_ddr_en_req;
uint8_t reg_spm_dvfs_req;
uint8_t reg_spm_sw_mailbox_req;
uint8_t reg_spm_sspm_mailbox_req;
uint8_t reg_spm_adsp_mailbox_req;
uint8_t reg_spm_scp_mailbox_req;
/* SPM_SRC_MASK */
uint8_t reg_sspm_srcclkena_0_mask_b;
uint8_t reg_sspm_infra_req_0_mask_b;
uint8_t reg_sspm_apsrc_req_0_mask_b;
uint8_t reg_sspm_vrf18_req_0_mask_b;
uint8_t reg_sspm_ddr_en_0_mask_b;
uint8_t reg_scp_srcclkena_mask_b;
uint8_t reg_scp_infra_req_mask_b;
uint8_t reg_scp_apsrc_req_mask_b;
uint8_t reg_scp_vrf18_req_mask_b;
uint8_t reg_scp_ddr_en_mask_b;
uint8_t reg_audio_dsp_srcclkena_mask_b;
uint8_t reg_audio_dsp_infra_req_mask_b;
uint8_t reg_audio_dsp_apsrc_req_mask_b;
uint8_t reg_audio_dsp_vrf18_req_mask_b;
uint8_t reg_audio_dsp_ddr_en_mask_b;
uint8_t reg_apu_srcclkena_mask_b;
uint8_t reg_apu_infra_req_mask_b;
uint8_t reg_apu_apsrc_req_mask_b;
uint8_t reg_apu_vrf18_req_mask_b;
uint8_t reg_apu_ddr_en_mask_b;
uint8_t reg_cpueb_srcclkena_mask_b;
uint8_t reg_cpueb_infra_req_mask_b;
uint8_t reg_cpueb_apsrc_req_mask_b;
uint8_t reg_cpueb_vrf18_req_mask_b;
uint8_t reg_cpueb_ddr_en_mask_b;
uint8_t reg_bak_psri_srcclkena_mask_b;
uint8_t reg_bak_psri_infra_req_mask_b;
uint8_t reg_bak_psri_apsrc_req_mask_b;
uint8_t reg_bak_psri_vrf18_req_mask_b;
uint8_t reg_bak_psri_ddr_en_mask_b;
/* SPM_SRC2_MASK */
uint8_t reg_msdc0_srcclkena_mask_b;
uint8_t reg_msdc0_infra_req_mask_b;
uint8_t reg_msdc0_apsrc_req_mask_b;
uint8_t reg_msdc0_vrf18_req_mask_b;
uint8_t reg_msdc0_ddr_en_mask_b;
uint8_t reg_msdc1_srcclkena_mask_b;
uint8_t reg_msdc1_infra_req_mask_b;
uint8_t reg_msdc1_apsrc_req_mask_b;
uint8_t reg_msdc1_vrf18_req_mask_b;
uint8_t reg_msdc1_ddr_en_mask_b;
uint8_t reg_msdc2_srcclkena_mask_b;
uint8_t reg_msdc2_infra_req_mask_b;
uint8_t reg_msdc2_apsrc_req_mask_b;
uint8_t reg_msdc2_vrf18_req_mask_b;
uint8_t reg_msdc2_ddr_en_mask_b;
uint8_t reg_ufs_srcclkena_mask_b;
uint8_t reg_ufs_infra_req_mask_b;
uint8_t reg_ufs_apsrc_req_mask_b;
uint8_t reg_ufs_vrf18_req_mask_b;
uint8_t reg_ufs_ddr_en_mask_b;
uint8_t reg_usb_srcclkena_mask_b;
uint8_t reg_usb_infra_req_mask_b;
uint8_t reg_usb_apsrc_req_mask_b;
uint8_t reg_usb_vrf18_req_mask_b;
uint8_t reg_usb_ddr_en_mask_b;
uint8_t reg_pextp_p0_srcclkena_mask_b;
uint8_t reg_pextp_p0_infra_req_mask_b;
uint8_t reg_pextp_p0_apsrc_req_mask_b;
uint8_t reg_pextp_p0_vrf18_req_mask_b;
uint8_t reg_pextp_p0_ddr_en_mask_b;
/* SPM_SRC3_MASK */
uint8_t reg_pextp_p1_srcclkena_mask_b;
uint8_t reg_pextp_p1_infra_req_mask_b;
uint8_t reg_pextp_p1_apsrc_req_mask_b;
uint8_t reg_pextp_p1_vrf18_req_mask_b;
uint8_t reg_pextp_p1_ddr_en_mask_b;
uint8_t reg_gce0_infra_req_mask_b;
uint8_t reg_gce0_apsrc_req_mask_b;
uint8_t reg_gce0_vrf18_req_mask_b;
uint8_t reg_gce0_ddr_en_mask_b;
uint8_t reg_gce1_infra_req_mask_b;
uint8_t reg_gce1_apsrc_req_mask_b;
uint8_t reg_gce1_vrf18_req_mask_b;
uint8_t reg_gce1_ddr_en_mask_b;
uint8_t reg_spm_srcclkena_reserved_mask_b;
uint8_t reg_spm_infra_req_reserved_mask_b;
uint8_t reg_spm_apsrc_req_reserved_mask_b;
uint8_t reg_spm_vrf18_req_reserved_mask_b;
uint8_t reg_spm_ddr_en_reserved_mask_b;
uint8_t reg_disp0_apsrc_req_mask_b;
uint8_t reg_disp0_ddr_en_mask_b;
uint8_t reg_disp1_apsrc_req_mask_b;
uint8_t reg_disp1_ddr_en_mask_b;
uint8_t reg_disp2_apsrc_req_mask_b;
uint8_t reg_disp2_ddr_en_mask_b;
uint8_t reg_disp3_apsrc_req_mask_b;
uint8_t reg_disp3_ddr_en_mask_b;
uint8_t reg_infrasys_apsrc_req_mask_b;
uint8_t reg_infrasys_ddr_en_mask_b;
uint8_t reg_cg_check_srcclkena_mask_b;
uint8_t reg_cg_check_apsrc_req_mask_b;
uint8_t reg_cg_check_vrf18_req_mask_b;
uint8_t reg_cg_check_ddr_en_mask_b;
/* SPM_SRC4_MASK */
uint32_t reg_mcusys_merge_apsrc_req_mask_b;
uint32_t reg_mcusys_merge_ddr_en_mask_b;
uint8_t reg_dramc_md32_infra_req_mask_b;
uint8_t reg_dramc_md32_vrf18_req_mask_b;
uint8_t reg_dramc_md32_ddr_en_mask_b;
uint8_t reg_dvfsrc_event_trigger_mask_b;
/* SPM_WAKEUP_EVENT_MASK2 */
uint8_t reg_sc_sw2spm_wakeup_mask_b;
uint8_t reg_sc_adsp2spm_wakeup_mask_b;
uint8_t reg_sc_sspm2spm_wakeup_mask_b;
uint8_t reg_sc_scp2spm_wakeup_mask_b;
uint8_t reg_csyspwrup_ack_mask;
uint8_t reg_csyspwrup_req_mask;
/* SPM_WAKEUP_EVENT_MASK */
uint32_t reg_wakeup_event_mask;
/* SPM_WAKEUP_EVENT_EXT_MASK */
uint32_t reg_ext_wakeup_event_mask;
};
/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
enum pwr_ctrl_enum {
PW_PCM_FLAGS,
PW_PCM_FLAGS_CUST,
PW_PCM_FLAGS_CUST_SET,
PW_PCM_FLAGS_CUST_CLR,
PW_PCM_FLAGS1,
PW_PCM_FLAGS1_CUST,
PW_PCM_FLAGS1_CUST_SET,
PW_PCM_FLAGS1_CUST_CLR,
PW_TIMER_VAL,
PW_TIMER_VAL_CUST,
PW_TIMER_VAL_RAMP_EN,
PW_TIMER_VAL_RAMP_EN_SEC,
PW_WAKE_SRC,
PW_WAKE_SRC_CUST,
PW_WAKELOCK_TIMER_VAL,
PW_WDT_DISABLE,
/* SPM_CLK_CON */
PW_REG_SRCCLKEN0_CTL,
PW_REG_SRCCLKEN1_CTL,
PW_REG_SPM_LOCK_INFRA_DCM,
PW_REG_SRCCLKEN_MASK,
PW_REG_MD1_C32RM_EN,
PW_REG_MD2_C32RM_EN,
PW_REG_CLKSQ0_SEL_CTRL,
PW_REG_CLKSQ1_SEL_CTRL,
PW_REG_SRCCLKEN0_EN,
PW_REG_SRCCLKEN1_EN,
PW_REG_SYSCLK0_SRC_MASK_B,
PW_REG_SYSCLK1_SRC_MASK_B,
/* SPM_AP_STANDBY_CON */
PW_REG_WFI_OP,
PW_REG_WFI_TYPE,
PW_REG_MP0_CPUTOP_IDLE_MASK,
PW_REG_MP1_CPUTOP_IDLE_MASK,
PW_REG_MCUSYS_IDLE_MASK,
PW_REG_MD_APSRC_1_SEL,
PW_REG_MD_APSRC_0_SEL,
PW_REG_CONN_APSRC_SEL,
/* SPM_SRC_REQ */
PW_REG_SPM_APSRC_REQ,
PW_REG_SPM_F26M_REQ,
PW_REG_SPM_INFRA_REQ,
PW_REG_SPM_VRF18_REQ,
PW_REG_SPM_DDR_EN_REQ,
PW_REG_SPM_DVFS_REQ,
PW_REG_SPM_SW_MAILBOX_REQ,
PW_REG_SPM_SSPM_MAILBOX_REQ,
PW_REG_SPM_ADSP_MAILBOX_REQ,
PW_REG_SPM_SCP_MAILBOX_REQ,
/* SPM_SRC_MASK */
PW_REG_MD_SRCCLKENA_0_MASK_B,
PW_REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B,
PW_REG_MD_APSRC2INFRA_REQ_0_MASK_B,
PW_REG_MD_APSRC_REQ_0_MASK_B,
PW_REG_MD_VRF18_REQ_0_MASK_B,
PW_REG_MD_DDR_EN_0_MASK_B,
PW_REG_MD_SRCCLKENA_1_MASK_B,
PW_REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B,
PW_REG_MD_APSRC2INFRA_REQ_1_MASK_B,
PW_REG_MD_APSRC_REQ_1_MASK_B,
PW_REG_MD_VRF18_REQ_1_MASK_B,
PW_REG_MD_DDR_EN_1_MASK_B,
PW_REG_CONN_SRCCLKENA_MASK_B,
PW_REG_CONN_SRCCLKENB_MASK_B,
PW_REG_CONN_INFRA_REQ_MASK_B,
PW_REG_CONN_APSRC_REQ_MASK_B,
PW_REG_CONN_VRF18_REQ_MASK_B,
PW_REG_CONN_DDR_EN_MASK_B,
PW_REG_CONN_VFE28_MASK_B,
PW_REG_SRCCLKENI0_SRCCLKENA_MASK_B,
PW_REG_SRCCLKENI0_INFRA_REQ_MASK_B,
PW_REG_SRCCLKENI1_SRCCLKENA_MASK_B,
PW_REG_SRCCLKENI1_INFRA_REQ_MASK_B,
PW_REG_SRCCLKENI2_SRCCLKENA_MASK_B,
PW_REG_SRCCLKENI2_INFRA_REQ_MASK_B,
PW_REG_INFRASYS_APSRC_REQ_MASK_B,
PW_REG_INFRASYS_DDR_EN_MASK_B,
PW_REG_MD32_SRCCLKENA_MASK_B,
PW_REG_MD32_INFRA_REQ_MASK_B,
PW_REG_MD32_APSRC_REQ_MASK_B,
PW_REG_MD32_VRF18_REQ_MASK_B,
PW_REG_MD32_DDR_EN_MASK_B,
/* SPM_SRC2_MASK */
PW_REG_SCP_SRCCLKENA_MASK_B,
PW_REG_SCP_INFRA_REQ_MASK_B,
PW_REG_SCP_APSRC_REQ_MASK_B,
PW_REG_SCP_VRF18_REQ_MASK_B,
PW_REG_SCP_DDR_EN_MASK_B,
PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
PW_REG_AUDIO_DSP_DDR_EN_MASK_B,
PW_REG_UFS_SRCCLKENA_MASK_B,
PW_REG_UFS_INFRA_REQ_MASK_B,
PW_REG_UFS_APSRC_REQ_MASK_B,
PW_REG_UFS_VRF18_REQ_MASK_B,
PW_REG_UFS_DDR_EN_MASK_B,
PW_REG_DISP0_APSRC_REQ_MASK_B,
PW_REG_DISP0_DDR_EN_MASK_B,
PW_REG_DISP1_APSRC_REQ_MASK_B,
PW_REG_DISP1_DDR_EN_MASK_B,
PW_REG_GCE_INFRA_REQ_MASK_B,
PW_REG_GCE_APSRC_REQ_MASK_B,
PW_REG_GCE_VRF18_REQ_MASK_B,
PW_REG_GCE_DDR_EN_MASK_B,
PW_REG_APU_SRCCLKENA_MASK_B,
PW_REG_APU_INFRA_REQ_MASK_B,
PW_REG_APU_APSRC_REQ_MASK_B,
PW_REG_APU_VRF18_REQ_MASK_B,
PW_REG_APU_DDR_EN_MASK_B,
PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
PW_REG_CG_CHECK_DDR_EN_MASK_B,
/* SPM_SRC3_MASK */
PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
PW_REG_SW2SPM_INT0_MASK_B,
PW_REG_SW2SPM_INT1_MASK_B,
PW_REG_SW2SPM_INT2_MASK_B,
PW_REG_SW2SPM_INT3_MASK_B,
PW_REG_SC_ADSP2SPM_WAKEUP_MASK_B,
PW_REG_SC_SSPM2SPM_WAKEUP_MASK_B,
PW_REG_SC_SCP2SPM_WAKEUP_MASK_B,
PW_REG_CSYSPWRREQ_MASK,
PW_REG_SPM_SRCCLKENA_RESERVED_MASK_B,
PW_REG_SPM_INFRA_REQ_RESERVED_MASK_B,
PW_REG_SPM_APSRC_REQ_RESERVED_MASK_B,
PW_REG_SPM_VRF18_REQ_RESERVED_MASK_B,
PW_REG_SPM_DDR_EN_RESERVED_MASK_B,
PW_REG_MCUPM_SRCCLKENA_MASK_B,
PW_REG_MCUPM_INFRA_REQ_MASK_B,
PW_REG_MCUPM_APSRC_REQ_MASK_B,
PW_REG_MCUPM_VRF18_REQ_MASK_B,
PW_REG_MCUPM_DDR_EN_MASK_B,
PW_REG_MSDC0_SRCCLKENA_MASK_B,
PW_REG_MSDC0_INFRA_REQ_MASK_B,
PW_REG_MSDC0_APSRC_REQ_MASK_B,
PW_REG_MSDC0_VRF18_REQ_MASK_B,
PW_REG_MSDC0_DDR_EN_MASK_B,
PW_REG_MSDC1_SRCCLKENA_MASK_B,
PW_REG_MSDC1_INFRA_REQ_MASK_B,
PW_REG_MSDC1_APSRC_REQ_MASK_B,
PW_REG_MSDC1_VRF18_REQ_MASK_B,
PW_REG_MSDC1_DDR_EN_MASK_B,
/* SPM_SRC4_MASK */
PW_CCIF_EVENT_MASK_B,
PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
PW_REG_BAK_PSRI_DDR_EN_MASK_B,
PW_REG_DRAMC0_MD32_INFRA_REQ_MASK_B,
PW_REG_DRAMC0_MD32_VRF18_REQ_MASK_B,
PW_REG_DRAMC1_MD32_INFRA_REQ_MASK_B,
PW_REG_DRAMC1_MD32_VRF18_REQ_MASK_B,
PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B,
PW_REG_DRAMC0_MD32_WAKEUP_MASK,
PW_REG_DRAMC1_MD32_WAKEUP_MASK,
/* SPM_SRC5_MASK */
PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
PW_REG_MCUSYS_MERGE_DDR_EN_MASK_B,
/* SPM_WAKEUP_EVENT_MASK */
PW_REG_WAKEUP_EVENT_MASK,
/* SPM_WAKEUP_EVENT_EXT_MASK */
PW_REG_EXT_WAKEUP_EVENT_MASK,
PW_MAX_COUNT,
};
#define SPM_INTERNAL_STATUS_HW_S1 (1U << 0)
#define SPM_ACK_CHK_3_SEL_HW_S1 0x00350098
#define SPM_ACK_CHK_3_HW_S1_CNT 1
#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG 0x800
#define SPM_ACK_CHK_3_CON_EN 0x110
#define SPM_ACK_CHK_3_CON_CLR_ALL 0x2
#define SPM_ACK_CHK_3_CON_RESULT 0x8000
struct wake_status_trace_comm {
uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */
uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */
uint32_t timer_out; /* SPM_BK_PCM_TIMER */
uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */
uint32_t b_sw_flag1; /* SPM_SW_RSV_8 */
uint32_t r12; /* SPM_SW_RSV_0 */
uint32_t r13; /* PCM_REG13_DATA */
uint32_t req_sta0; /* SRC_REQ_STA_0 */
uint32_t req_sta1; /* SRC_REQ_STA_1 */
uint32_t req_sta2; /* SRC_REQ_STA_2 */
uint32_t req_sta3; /* SRC_REQ_STA_3 */
uint32_t req_sta4; /* SRC_REQ_STA_4 */
uint32_t raw_sta; /* SPM_WAKEUP_STA */
uint32_t times_h; /* timestamp high bits */
uint32_t times_l; /* timestamp low bits */
uint32_t resumetime; /* timestamp low bits */
};
struct wake_status_trace {
struct wake_status_trace_comm comm;
};
struct wake_status {
struct wake_status_trace tr;
uint32_t r12; /* SPM_BK_WAKE_EVENT */
uint32_t r12_ext; /* SPM_WAKEUP_STA */
uint32_t raw_sta; /* SPM_WAKEUP_STA */
uint32_t raw_ext_sta; /* SPM_WAKEUP_EXT_STA */
uint32_t md32pcm_wakeup_sta; /* MD32PCM_WAKEUP_STA */
uint32_t md32pcm_event_sta; /* MD32PCM_EVENT_STA */
uint32_t src_req; /* SPM_SRC_REQ */
uint32_t wake_misc; /* SPM_BK_WAKE_MISC */
uint32_t timer_out; /* SPM_BK_PCM_TIMER */
uint32_t r13; /* PCM_REG13_DATA */
uint32_t idle_sta; /* SUBSYS_IDLE_STA */
uint32_t req_sta0; /* SRC_REQ_STA_0 */
uint32_t req_sta1; /* SRC_REQ_STA_1 */
uint32_t req_sta2; /* SRC_REQ_STA_2 */
uint32_t req_sta3; /* SRC_REQ_STA_3 */
uint32_t req_sta4; /* SRC_REQ_STA_4 */
uint32_t cg_check_sta; /* SPM_CG_CHECK_STA */
uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */
uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */
uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */
uint32_t b_sw_flag1; /* SPM_SW_RSV_8 */
uint32_t rt_req_sta0; /* SPM_SW_RSV_2 */
uint32_t rt_req_sta1; /* SPM_SW_RSV_3 */
uint32_t rt_req_sta2; /* SPM_SW_RSV_4 */
uint32_t rt_req_sta3; /* SPM_SW_RSV_5 */
uint32_t rt_req_sta4; /* SPM_SW_RSV_6 */
uint32_t isr; /* SPM_IRQ_STA */
uint32_t sw_flag0; /* SPM_SW_FLAG_0 */
uint32_t sw_flag1; /* SPM_SW_FLAG_1 */
uint32_t clk_settle; /* SPM_CLK_SETTLE */
uint32_t abort;
};
struct spm_lp_scen {
struct pcm_desc *pcmdesc;
struct pwr_ctrl *pwrctrl;
};
extern struct spm_lp_scen __spm_vcorefs;
extern void __spm_set_cpu_status(unsigned int cpu);
extern void __spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc);
extern void __spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc);
extern void __spm_init_pcm_register(void);
extern void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
unsigned int resource_usage);
extern void __spm_set_power_control(const struct pwr_ctrl *pwrctrl);
extern void __spm_disable_pcm_timer(void);
extern void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
extern void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl);
extern void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl);
extern void __spm_send_cpu_wakeup_event(void);
extern void __spm_get_wakeup_status(struct wake_status *wakesta,
unsigned int ext_status);
extern void __spm_clean_after_wakeup(void);
extern wake_reason_t
__spm_output_wake_reason(int state_id, const struct wake_status *wakesta);
extern void
__spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
const struct pwr_ctrl *src_pwr_ctrl);
extern void __spm_set_pcm_wdt(int en);
extern uint32_t _spm_get_wake_period(int pwake_time, wake_reason_t last_wr);
extern void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl);
extern void __spm_ext_int_wakeup_req_clr(void);
extern void __spm_xo_soc_bblpm(int en);
static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl,
uint32_t flags)
{
if (pwrctrl->pcm_flags_cust == 0U) {
pwrctrl->pcm_flags = flags;
} else {
pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust;
}
}
static inline void set_pwrctrl_pcm_flags1(struct pwr_ctrl *pwrctrl,
uint32_t flags)
{
if (pwrctrl->pcm_flags1_cust == 0U) {
pwrctrl->pcm_flags1 = flags;
} else {
pwrctrl->pcm_flags1 = pwrctrl->pcm_flags1_cust;
}
}
extern void __spm_hw_s1_state_monitor(int en, unsigned int *status);
static inline void spm_hw_s1_state_monitor_resume(void)
{
__spm_hw_s1_state_monitor(1, NULL);
}
static inline void spm_hw_s1_state_monitor_pause(unsigned int *status)
{
__spm_hw_s1_state_monitor(0, status);
}
#endif /* MT_SPM_INTERNAL_H */
plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.c 0 → 100644
View file @ 7fa35d06
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <string.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <mt_spm.h>
#include <mt_spm_internal.h>
#include <mt_spm_pmic_wrap.h>
#include <mt_spm_reg.h>
#include <plat_pm.h>
#include <platform_def.h>
/* PMIC_WRAP MT6359 */
#define VCORE_BASE_UV 40000
#define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625)
#define PMIC_VAL_TO_VOLT(pmic) (((pmic) * 625) + VCORE_BASE_UV)
#define NR_PMIC_WRAP_CMD (NR_IDX_ALL)
#define SPM_DATA_SHIFT 16
#define BUCK_VGPU11_ELR0 0x15B4
#define TOP_SPI_CON0 0x0456
#define BUCK_TOP_CON1 0x1443
#define TOP_CON 0x0013
#define TOP_DIG_WPK 0x03a9
#define TOP_CON_LOCK 0x03a8
#define TOP_CLK_CON0 0x0134
struct pmic_wrap_cmd {
unsigned long cmd_addr;
unsigned long cmd_wdata;
};
struct pmic_wrap_setting {
enum pmic_wrap_phase_id phase;
struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD];
struct {
struct {
unsigned long cmd_addr;
unsigned long cmd_wdata;
} _[NR_PMIC_WRAP_CMD];
const int nr_idx;
} set[NR_PMIC_WRAP_PHASE];
};
static struct pmic_wrap_setting pw = {
.phase = NR_PMIC_WRAP_PHASE, /* invalid setting for init */
.addr = { {0UL, 0UL} },
.set[PMIC_WRAP_PHASE_ALLINONE] = {
._[CMD_0] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(75000),},
._[CMD_1] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(65000),},
._[CMD_2] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(60000),},
._[CMD_3] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(55000),},
._[CMD_4] = {TOP_SPI_CON0, 0x1,},
._[CMD_5] = {TOP_SPI_CON0, 0x0,},
._[CMD_6] = {BUCK_TOP_CON1, 0x0,},
._[CMD_7] = {BUCK_TOP_CON1, 0xf,},
._[CMD_8] = {TOP_CON, 0x3,},
._[CMD_9] = {TOP_CON, 0x0,},
._[CMD_10] = {TOP_DIG_WPK, 0x63,},
._[CMD_11] = {TOP_CON_LOCK, 0x15,},
._[CMD_12] = {TOP_DIG_WPK, 0x0,},
._[CMD_13] = {TOP_CON_LOCK, 0x0,},
._[CMD_14] = {TOP_CLK_CON0, 0x40,},
._[CMD_15] = {TOP_CLK_CON0, 0x0,},
.nr_idx = NR_IDX_ALL,
},
};
void _mt_spm_pmic_table_init(void)
{
struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = {
{(uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0,},
{(uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1,},
{(uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2,},
{(uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3,},
{(uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4,},
{(uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5,},
{(uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6,},
{(uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7,},
{(uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8,},
{(uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9,},
{(uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10,},
{(uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11,},
{(uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12,},
{(uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13,},
{(uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14,},
{(uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15,},
};
memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default));
}
void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase)
{
uint32_t idx, addr, data;
if (phase >= NR_PMIC_WRAP_PHASE) {
return;
}
if (pw.phase == phase) {
return;
}
if (pw.addr[0].cmd_addr == 0UL) {
_mt_spm_pmic_table_init();
}
pw.phase = phase;
mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) {
addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
data = pw.set[phase]._[idx].cmd_wdata;
mmio_write_32(pw.addr[idx].cmd_addr, addr | data);
}
}
void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx,
uint32_t cmd_wdata)
{
uint32_t addr;
if (phase >= NR_PMIC_WRAP_PHASE) {
return;
}
if (idx >= pw.set[phase].nr_idx) {
return;
}
pw.set[phase]._[idx].cmd_wdata = cmd_wdata;
mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
if (pw.phase == phase) {
addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata);
}
}
uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx)
{
if (phase >= NR_PMIC_WRAP_PHASE) {
return 0UL;
}
if (idx >= pw.set[phase].nr_idx) {
return 0UL;
}
return pw.set[phase]._[idx].cmd_wdata;
}
plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.h 0 → 100644
View file @ 7fa35d06
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/****************************************************************
* Auto generated by DE, please DO NOT modify this file directly.
*****************************************************************/
#ifndef MT_SPM_PMIC_WRAP_H
#define MT_SPM_PMIC_WRAP_H
enum pmic_wrap_phase_id {
PMIC_WRAP_PHASE_ALLINONE,
NR_PMIC_WRAP_PHASE,
};
/* IDX mapping, PMIC_WRAP_PHASE_ALLINONE */
enum {
CMD_0, /* 0x0 */
CMD_1, /* 0x1 */
CMD_2, /* 0x2 */
CMD_3, /* 0x3 */
CMD_4, /* 0x4 */
CMD_5, /* 0x5 */
CMD_6, /* 0x6 */
CMD_7, /* 0x7 */
CMD_8, /* 0x8 */
CMD_9, /* 0x9 */
CMD_10, /* 0xA */
CMD_11, /* 0xB */
CMD_12, /* 0xC */
CMD_13, /* 0xD */
CMD_14, /* 0xE */
CMD_15, /* 0xF */
NR_IDX_ALL,
};
/* APIs */
extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
uint32_t idx, uint32_t cmd_wdata);
extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase,
uint32_t idx);
#endif /* MT_SPM_PMIC_WRAP_H */
plat/mediatek/mt8195/drivers/spm/mt_spm_reg.h 0 → 100644
View file @ 7fa35d06
This diff is collapsed.
plat/mediatek/mt8195/drivers/spm/mt_spm_resource_req.h 0 → 100644
View file @ 7fa35d06
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_RESOURCE_REQ_H
#define MT_SPM_RESOURCE_REQ_H
/* SPM resource request internal bit */
#define MT_SPM_BIT_XO_FPM 0
#define MT_SPM_BIT_26M 1
#define MT_SPM_BIT_INFRA 2
#define MT_SPM_BIT_SYSPLL 3
#define MT_SPM_BIT_DRAM_S0 4
#define MT_SPM_BIT_DRAM_S1 5
/* SPM resource request internal bit_mask */
#define MT_SPM_XO_FPM BIT(MT_SPM_BIT_XO_FPM)
#define MT_SPM_26M BIT(MT_SPM_BIT_26M)
#define MT_SPM_INFRA BIT(MT_SPM_BIT_INFRA)
#define MT_SPM_SYSPLL BIT(MT_SPM_BIT_SYSPLL)
#define MT_SPM_DRAM_S0 BIT(MT_SPM_BIT_DRAM_S0)
#define MT_SPM_DRAM_S1 BIT(MT_SPM_BIT_DRAM_S1)
#endif /* MT_SPM_RESOURCE_REQ_H */
plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.c 0 → 100644
View file @ 7fa35d06
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <lib/mmio.h>
#include <mt_spm.h>
#include <mt_spm_conservation.h>
#include <mt_spm_internal.h>
#include <mt_spm_rc_internal.h>
#include <mt_spm_reg.h>
#include <mt_spm_resource_req.h>
#include <mt_spm_suspend.h>
#include <plat_pm.h>
#include <uart.h>
#define SPM_SUSPEND_SLEEP_PCM_FLAG \
(SPM_FLAG_DISABLE_INFRA_PDN | \
SPM_FLAG_DISABLE_VCORE_DVS | \
SPM_FLAG_DISABLE_VCORE_DFS | \
SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
SPM_FLAG_SRAM_SLEEP_CTRL)
#define SPM_SUSPEND_SLEEP_PCM_FLAG1 0
#define SPM_SUSPEND_PCM_FLAG \
(SPM_FLAG_DISABLE_VCORE_DVS | \
SPM_FLAG_DISABLE_VCORE_DFS | \
SPM_FLAG_ENABLE_TIA_WORKAROUND | \
SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
SPM_FLAG_SRAM_SLEEP_CTRL)
#define SPM_SUSPEND_PCM_FLAG1 0
/* Suspend spm power control */
#define __WAKE_SRC_FOR_SUSPEND_COMMON__ \
(R12_PCM_TIMER | \
R12_KP_IRQ_B | \
R12_APWDT_EVENT_B | \
R12_CONN2AP_SPM_WAKEUP_B | \
R12_EINT_EVENT_B | \
R12_CONN_WDT_IRQ_B | \
R12_CCIF0_EVENT_B | \
R12_SSPM2SPM_WAKEUP_B | \
R12_SCP2SPM_WAKEUP_B | \
R12_ADSP2SPM_WAKEUP_B | \
R12_USBX_CDSC_B | \
R12_USBX_POWERDWN_B | \
R12_SYS_TIMER_EVENT_B | \
R12_EINT_EVENT_SECURE_B | \
R12_SYS_CIRQ_IRQ_B | \
R12_MD2AP_PEER_EVENT_B | \
R12_MD1_WDT_B | \
R12_CLDMA_EVENT_B | \
R12_REG_CPU_WAKEUP | \
R12_APUSYS_WAKE_HOST_B)
#if defined(CFG_MICROTRUST_TEE_SUPPORT)
#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__)
#else
#define WAKE_SRC_FOR_SUSPEND \
(__WAKE_SRC_FOR_SUSPEND_COMMON__ | \
R12_SEJ_EVENT_B)
#endif
static struct pwr_ctrl suspend_ctrl = {
.wake_src = WAKE_SRC_FOR_SUSPEND,
/* SPM_AP_STANDBY_CON */
/* [0] */
.reg_wfi_op = 0,
/* [1] */
.reg_wfi_type = 0,
/* [2] */
.reg_mp0_cputop_idle_mask = 0,
/* [3] */
.reg_mp1_cputop_idle_mask = 0,
/* [4] */
.reg_mcusys_idle_mask = 0,
/* [25] */
.reg_md_apsrc_1_sel = 0,
/* [26] */
.reg_md_apsrc_0_sel = 0,
/* [29] */
.reg_conn_apsrc_sel = 0,
/* SPM_SRC_REQ */
/* [0] */
.reg_spm_apsrc_req = 0,
/* [1] */
.reg_spm_f26m_req = 0,
/* [3] */
.reg_spm_infra_req = 0,
/* [4] */
.reg_spm_vrf18_req = 0,
/* [7] FIXME: default disable HW Auto S1*/
.reg_spm_ddr_en_req = 1,
/* [8] */
.reg_spm_dvfs_req = 0,
/* [9] */
.reg_spm_sw_mailbox_req = 0,
/* [10] */
.reg_spm_sspm_mailbox_req = 0,
/* [11] */
.reg_spm_adsp_mailbox_req = 0,
/* [12] */
.reg_spm_scp_mailbox_req = 0,
/* SPM_SRC_MASK */
/* [0] */
.reg_sspm_srcclkena_0_mask_b = 1,
/* [1] */
.reg_sspm_infra_req_0_mask_b = 1,
/* [2] */
.reg_sspm_apsrc_req_0_mask_b = 1,
/* [3] */
.reg_sspm_vrf18_req_0_mask_b = 1,
/* [4] */
.reg_sspm_ddr_en_0_mask_b = 1,
/* [5] */
.reg_scp_srcclkena_mask_b = 1,
/* [6] */
.reg_scp_infra_req_mask_b = 1,
/* [7] */
.reg_scp_apsrc_req_mask_b = 1,
/* [8] */
.reg_scp_vrf18_req_mask_b = 1,
/* [9] */
.reg_scp_ddr_en_mask_b = 1,
/* [10] */
.reg_audio_dsp_srcclkena_mask_b = 1,
/* [11] */
.reg_audio_dsp_infra_req_mask_b = 1,
/* [12] */
.reg_audio_dsp_apsrc_req_mask_b = 1,
/* [13] */
.reg_audio_dsp_vrf18_req_mask_b = 1,
/* [14] */
.reg_audio_dsp_ddr_en_mask_b = 1,
/* [15] */
.reg_apu_srcclkena_mask_b = 1,
/* [16] */
.reg_apu_infra_req_mask_b = 1,
/* [17] */
.reg_apu_apsrc_req_mask_b = 1,
/* [18] */
.reg_apu_vrf18_req_mask_b = 1,
/* [19] */
.reg_apu_ddr_en_mask_b = 1,
/* [20] */
.reg_cpueb_srcclkena_mask_b = 1,
/* [21] */
.reg_cpueb_infra_req_mask_b = 1,
/* [22] */
.reg_cpueb_apsrc_req_mask_b = 1,
/* [23] */
.reg_cpueb_vrf18_req_mask_b = 1,
/* [24] */
.reg_cpueb_ddr_en_mask_b = 1,
/* [25] */
.reg_bak_psri_srcclkena_mask_b = 0,
/* [26] */
.reg_bak_psri_infra_req_mask_b = 0,
/* [27] */
.reg_bak_psri_apsrc_req_mask_b = 0,
/* [28] */
.reg_bak_psri_vrf18_req_mask_b = 0,
/* [29] */
.reg_bak_psri_ddr_en_mask_b = 0,
/* SPM_SRC2_MASK */
/* [0] */
.reg_msdc0_srcclkena_mask_b = 1,
/* [1] */
.reg_msdc0_infra_req_mask_b = 1,
/* [2] */
.reg_msdc0_apsrc_req_mask_b = 1,
/* [3] */
.reg_msdc0_vrf18_req_mask_b = 1,
/* [4] */
.reg_msdc0_ddr_en_mask_b = 1,
/* [5] */
.reg_msdc1_srcclkena_mask_b = 1,
/* [6] */
.reg_msdc1_infra_req_mask_b = 1,
/* [7] */
.reg_msdc1_apsrc_req_mask_b = 1,
/* [8] */
.reg_msdc1_vrf18_req_mask_b = 1,
/* [9] */
.reg_msdc1_ddr_en_mask_b = 1,
/* [10] */
.reg_msdc2_srcclkena_mask_b = 1,
/* [11] */
.reg_msdc2_infra_req_mask_b = 1,
/* [12] */
.reg_msdc2_apsrc_req_mask_b = 1,
/* [13] */
.reg_msdc2_vrf18_req_mask_b = 1,
/* [14] */
.reg_msdc2_ddr_en_mask_b = 1,
/* [15] */
.reg_ufs_srcclkena_mask_b = 0,
/* [16] */
.reg_ufs_infra_req_mask_b = 0,
/* [17] */
.reg_ufs_apsrc_req_mask_b = 0,
/* [18] */
.reg_ufs_vrf18_req_mask_b = 0,
/* [19] */
.reg_ufs_ddr_en_mask_b = 0,
/* [20] */
.reg_usb_srcclkena_mask_b = 1,
/* [21] */
.reg_usb_infra_req_mask_b = 1,
/* [22] */
.reg_usb_apsrc_req_mask_b = 1,
/* [23] */
.reg_usb_vrf18_req_mask_b = 1,
/* [24] */
.reg_usb_ddr_en_mask_b = 1,
/* [25] */
.reg_pextp_p0_srcclkena_mask_b = 1,
/* [26] */
.reg_pextp_p0_infra_req_mask_b = 1,
/* [27] */
.reg_pextp_p0_apsrc_req_mask_b = 1,
/* [28] */
.reg_pextp_p0_vrf18_req_mask_b = 1,
/* [29] */
.reg_pextp_p0_ddr_en_mask_b = 1,
/* SPM_SRC3_MASK */
/* [0] */
.reg_pextp_p1_srcclkena_mask_b = 1,
/* [1] */
.reg_pextp_p1_infra_req_mask_b = 1,
/* [2] */
.reg_pextp_p1_apsrc_req_mask_b = 1,
/* [3] */
.reg_pextp_p1_vrf18_req_mask_b = 1,
/* [4] */
.reg_pextp_p1_ddr_en_mask_b = 1,
/* [5] */
.reg_gce0_infra_req_mask_b = 1,
/* [6] */
.reg_gce0_apsrc_req_mask_b = 1,
/* [7] */
.reg_gce0_vrf18_req_mask_b = 1,
/* [8] */
.reg_gce0_ddr_en_mask_b = 1,
/* [9] */
.reg_gce1_infra_req_mask_b = 1,
/* [10] */
.reg_gce1_apsrc_req_mask_b = 1,
/* [11] */
.reg_gce1_vrf18_req_mask_b = 1,
/* [12] */
.reg_gce1_ddr_en_mask_b = 1,
/* [13] */
.reg_spm_srcclkena_reserved_mask_b = 1,
/* [14] */
.reg_spm_infra_req_reserved_mask_b = 1,
/* [15] */
.reg_spm_apsrc_req_reserved_mask_b = 1,
/* [16] */
.reg_spm_vrf18_req_reserved_mask_b = 1,
/* [17] */
.reg_spm_ddr_en_reserved_mask_b = 1,
/* [18] */
.reg_disp0_apsrc_req_mask_b = 1,
/* [19] */
.reg_disp0_ddr_en_mask_b = 1,
/* [20] */
.reg_disp1_apsrc_req_mask_b = 1,
/* [21] */
.reg_disp1_ddr_en_mask_b = 1,
/* [22] */
.reg_disp2_apsrc_req_mask_b = 1,
/* [23] */
.reg_disp2_ddr_en_mask_b = 1,
/* [24] */
.reg_disp3_apsrc_req_mask_b = 1,
/* [25] */
.reg_disp3_ddr_en_mask_b = 1,
/* [26] */
.reg_infrasys_apsrc_req_mask_b = 0,
/* [27] */
.reg_infrasys_ddr_en_mask_b = 1,
/* [28] */
.reg_cg_check_srcclkena_mask_b = 1,
/* [29] */
.reg_cg_check_apsrc_req_mask_b = 1,
/* [30] */
.reg_cg_check_vrf18_req_mask_b = 1,
/* [31] */
.reg_cg_check_ddr_en_mask_b = 1,
/* SPM_SRC4_MASK */
/* [8:0] */
.reg_mcusys_merge_apsrc_req_mask_b = 0x17,
/* [17:9] */
.reg_mcusys_merge_ddr_en_mask_b = 0x17,
/* [19:18] */
.reg_dramc_md32_infra_req_mask_b = 0,
/* [21:20] */
.reg_dramc_md32_vrf18_req_mask_b = 0,
/* [23:22] */
.reg_dramc_md32_ddr_en_mask_b = 0,
/* [24] */
.reg_dvfsrc_event_trigger_mask_b = 1,
/* SPM_WAKEUP_EVENT_MASK2 */
/* [3:0] */
.reg_sc_sw2spm_wakeup_mask_b = 0,
/* [4] */
.reg_sc_adsp2spm_wakeup_mask_b = 0,
/* [8:5] */
.reg_sc_sspm2spm_wakeup_mask_b = 0,
/* [9] */
.reg_sc_scp2spm_wakeup_mask_b = 0,
/* [10] */
.reg_csyspwrup_ack_mask = 0,
/* [11] */
.reg_csyspwrup_req_mask = 1,
/* SPM_WAKEUP_EVENT_MASK */
/* [31:0] */
.reg_wakeup_event_mask = 0xC1382213,
/* SPM_WAKEUP_EVENT_EXT_MASK */
/* [31:0] */
.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
};
struct spm_lp_scen __spm_suspend = {
.pwrctrl = &suspend_ctrl,
};
int mt_spm_suspend_mode_set(int mode)
{
if (mode == MT_SPM_SUSPEND_SLEEP) {
suspend_ctrl.pcm_flags = SPM_SUSPEND_SLEEP_PCM_FLAG;
suspend_ctrl.pcm_flags1 = SPM_SUSPEND_SLEEP_PCM_FLAG1;
} else {
suspend_ctrl.pcm_flags = SPM_SUSPEND_PCM_FLAG;
suspend_ctrl.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1;
}
return 0;
}
int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
unsigned int resource_req)
{
/* If FMAudio / ADSP is active, change to sleep suspend mode */
if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SLEEP);
}
/* Notify MCUPM that device is going suspend flow */
mmio_write_32(MCUPM_MBOX_OFFSET_PDN, MCUPM_POWER_DOWN);
/* Notify UART to sleep */
mt_uart_save();
return spm_conservation(state_id, ext_opand,
&__spm_suspend, resource_req);
}
void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
struct wake_status **status)
{
spm_conservation_finish(state_id, ext_opand, &__spm_suspend, status);
/* Notify UART to wakeup */
mt_uart_restore();
/* Notify MCUPM that device leave suspend */
mmio_write_32(MCUPM_MBOX_OFFSET_PDN, 0);
/* If FMAudio / ADSP is active, change back to suspend mode */
if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SYSTEM_PDN);
}
}
void mt_spm_suspend_init(void)
{
spm_conservation_pwrctrl_init(__spm_suspend.pwrctrl);
}
plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.h 0 → 100644
View file @ 7fa35d06
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_SUSPEND_H
#define MT_SPM_SUSPEND_H
#include <mt_spm_internal.h>
#define MCUPM_MBOX_OFFSET_PDN 0x1031FF88
#define MCUPM_POWER_DOWN 0x4D50444E
enum MT_SPM_SUSPEND_MODE {
MT_SPM_SUSPEND_SYSTEM_PDN,
MT_SPM_SUSPEND_SLEEP,
};
extern int mt_spm_suspend_mode_set(int mode);
extern int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
unsigned int reosuce_req);
extern void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
struct wake_status **status);
extern void mt_spm_suspend_init(void);
#endif /* MT_SPM_SUSPEND_H */
plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_notifier.h 0 → 100644
View file @ 7fa35d06
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_SSPM_NOTIFIER_H
#define MT_SPM_SSPM_NOTIFIER_H
enum MT_SPM_SSPM_NOTIFY_ID {
MT_SPM_NOTIFY_LP_ENTER,
MT_SPM_NOTIFY_LP_LEAVE,
};
int mt_spm_sspm_notify(int type, unsigned int lp_mode);
static inline int mt_spm_sspm_notify_u32(int type, unsigned int lp_mode)
{
return mt_spm_sspm_notify(type, lp_mode);
}
#endif /* MT_SPM_SSPM_NOTIFIER_H */
plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_intc.h 0 → 100644
View file @ 7fa35d06
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_SSPM_INTC_H
#define MT_SPM_SSPM_INTC_H
#include <mt_spm_reg.h>
#define MT_SPM_SSPM_INTC_SEL_0 0x10
#define MT_SPM_SSPM_INTC_SEL_1 0x20
#define MT_SPM_SSPM_INTC_SEL_2 0x40
#define MT_SPM_SSPM_INTC_SEL_3 0x80
#define MT_SPM_SSPM_INTC_TRIGGER(id, sg) \
(((0x10 << id) | (sg << id)) & 0xff)
#define MT_SPM_SSPM_INTC0_HIGH MT_SPM_SSPM_INTC_TRIGGER(0, 1)
#define MT_SPM_SSPM_INTC0_LOW MT_SPM_SSPM_INTC_TRIGGER(0, 0)
#define MT_SPM_SSPM_INTC1_HIGH MT_SPM_SSPM_INTC_TRIGGER(1, 1)
#define MT_SPM_SSPM_INTC1_LOW MT_SPM_SSPM_INTC_TRIGGER(1, 0)
#define MT_SPM_SSPM_INTC2_HIGH MT_SPM_SSPM_INTC_TRIGGER(2, 1)
#define MT_SPM_SSPM_INTC2_LOW MT_SPM_SSPM_INTC_TRIGGER(2, 0)
#define MT_SPM_SSPM_INTC3_HIGH MT_SPM_SSPM_INTC_TRIGGER(3, 1)
#define MT_SPM_SSPM_INTC3_LOW MT_SPM_SSPM_INTC_TRIGGER(3, 0)
#define DO_SPM_SSPM_LP_SUSPEND() \
mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_HIGH)
#define DO_SPM_SSPM_LP_RESUME() \
mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_LOW)
#endif /* MT_SPM_SSPM_INTC_H */
plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_notifier.c 0 → 100644
View file @ 7fa35d06
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stddef.h>
#include <lib/mmio.h>
#include <mt_spm_notifier.h>
#include <mt_spm_sspm_intc.h>
#define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_BASE + x)
#define MT_SPM_MBOX(slot) MT_SPM_SSPM_MBOX_OFF((slot << 2UL))
#define SSPM_MBOX_SPM_LP_LOOKUP1 MT_SPM_MBOX(0)
#define SSPM_MBOX_SPM_LP_LOOKUP2 MT_SPM_MBOX(1)
#define SSPM_MBOX_SPM_LP1 MT_SPM_MBOX(2)
#define SSPM_MBOX_SPM_LP2 MT_SPM_MBOX(3)
int mt_spm_sspm_notify(int type, unsigned int lp_mode)
{
switch (type) {
case MT_SPM_NOTIFY_LP_ENTER:
mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
DO_SPM_SSPM_LP_SUSPEND();
break;
case MT_SPM_NOTIFY_LP_LEAVE:
mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
DO_SPM_SSPM_LP_RESUME();
break;
default:
break;
}
return 0;
}
plat/mediatek/mt8195/drivers/spm/pcm_def.h 0 → 100644
View file @ 7fa35d06
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PCM_DEF_H
#define PCM_DEF_H
/*
* Auto generated by DE, please DO NOT modify this file directly.
*/
/* --- R0 Define --- */
#define R0_SC_26M_CK_OFF (1U << 0)
#define R0_SC_TX_TRACK_RETRY_EN (1U << 1)
#define R0_SC_MEM_CK_OFF (1U << 2)
#define R0_SC_AXI_CK_OFF (1U << 3)
#define R0_SC_DR_SRAM_LOAD (1U << 4)
#define R0_SC_MD26M_CK_OFF (1U << 5)
#define R0_SC_DPY_MODE_SW (1U << 6)
#define R0_SC_DMSUS_OFF (1U << 7)
#define R0_SC_DPY_2ND_DLL_EN (1U << 8)
#define R0_SC_DR_SRAM_RESTORE (1U << 9)
#define R0_SC_MPLLOUT_OFF (1U << 10)
#define R0_SC_TX_TRACKING_DIS (1U << 11)
#define R0_SC_DPY_DLL_EN (1U << 12)
#define R0_SC_DPY_DLL_CK_EN (1U << 13)
#define R0_SC_DPY_VREF_EN (1U << 14)
#define R0_SC_PHYPLL_EN (1U << 15)
#define R0_SC_DDRPHY_FB_CK_EN (1U << 16)
#define R0_SC_DPY_BCLK_ENABLE (1U << 17)
#define R0_SC_MPLL_OFF (1U << 18)
#define R0_SC_SHU_RESTORE (1U << 19)
#define R0_SC_CKSQ0_OFF (1U << 20)
#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH (1U << 21)
#define R0_SC_DR_SHU_EN (1U << 22)
#define R0_SC_DPHY_PRECAL_UP (1U << 23)
#define R0_SC_MPLL_S_OFF (1U << 24)
#define R0_SC_DPHY_RXDLY_TRACKING_EN (1U << 25)
#define R0_SC_PHYPLL_SHU_EN (1U << 26)
#define R0_SC_PHYPLL2_SHU_EN (1U << 27)
#define R0_SC_PHYPLL_MODE_SW (1U << 28)
#define R0_SC_PHYPLL2_MODE_SW (1U << 29)
#define R0_SC_DR_SHU_LEVEL0 (1U << 30)
#define R0_SC_DR_SHU_LEVEL1 (1U << 31)
/* --- R7 Define --- */
#define R7_PWRAP_SLEEP_REQ (1U << 0)
#define R7_EMI_CLK_OFF_REQ (1U << 1)
#define R7_PCM_BUS_PROTECT_REQ (1U << 2)
#define R7_SPM_CK_UPDATE (1U << 3)
#define R7_SPM_CK_SEL0 (1U << 4)
#define R7_SPM_CK_SEL1 (1U << 5)
#define R7_SPM_LEAVE_DEEPIDLE_REQ (1U << 6)
#define R7_SC_FHC_PAUSE_MPLL (1U << 7)
#define R7_SC_26M_CK_SEL (1U << 8)
#define R7_PCM_TIMER_SET (1U << 9)
#define R7_PCM_TIMER_CLR (1U << 10)
#define R7_SPM_LEAVE_SUSPEND_REQ (1U << 11)
#define R7_CSYSPWRUPACK (1U << 12)
#define R7_PCM_IM_SLP_EN (1U << 13)
#define R7_SRCCLKENO0 (1U << 14)
#define R7_FORCE_DDR_EN_WAKE (1U << 15)
#define R7_SPM_APSRC_INTERNAL_ACK (1U << 16)
#define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17)
#define R7_SC_AXI_DCM_DIS (1U << 18)
#define R7_SC_FHC_PAUSE_MEM (1U << 19)
#define R7_SC_FHC_PAUSE_MAIN (1U << 20)
#define R7_SRCCLKENO1 (1U << 21)
#define R7_PCM_WDT_KICK_P (1U << 22)
#define R7_SPM2EMI_S1_MODE_ASYNC (1U << 23)
#define R7_SC_DDR_PST_REQ_PCM (1U << 24)
#define R7_SC_DDR_PST_ABORT_REQ_PCM (1U << 25)
#define R7_PMIC_IRQ_REQ_EN (1U << 26)
#define R7_FORCE_F26M_WAKE (1U << 27)
#define R7_FORCE_APSRC_WAKE (1U << 28)
#define R7_FORCE_INFRA_WAKE (1U << 29)
#define R7_FORCE_VRF18_WAKE (1U << 30)
#define R7_SPM_DDR_EN_INTERNAL_ACK (1U << 31)
/* --- R12 Define --- */
#define R12_PCM_TIMER (1U << 0)
#define R12_TWAM_IRQ_B (1U << 1)
#define R12_KP_IRQ_B (1U << 2)
#define R12_APWDT_EVENT_B (1U << 3)
#define R12_APXGPT1_EVENT_B (1U << 4)
#define R12_CONN2AP_SPM_WAKEUP_B (1U << 5)
#define R12_EINT_EVENT_B (1U << 6)
#define R12_CONN_WDT_IRQ_B (1U << 7)
#define R12_CCIF0_EVENT_B (1U << 8)
#define R12_LOWBATTERY_IRQ_B (1U << 9)
#define R12_SSPM2SPM_WAKEUP_B (1U << 10)
#define R12_SCP2SPM_WAKEUP_B (1U << 11)
#define R12_ADSP2SPM_WAKEUP_B (1U << 12)
#define R12_PCM_WDT_WAKEUP_B (1U << 13)
#define R12_USBX_CDSC_B (1U << 14)
#define R12_USBX_POWERDWN_B (1U << 15)
#define R12_SYS_TIMER_EVENT_B (1U << 16)
#define R12_EINT_EVENT_SECURE_B (1U << 17)
#define R12_CCIF1_EVENT_B (1U << 18)
#define R12_UART0_IRQ_B (1U << 19)
#define R12_AFE_IRQ_MCU_B (1U << 20)
#define R12_THERM_CTRL_EVENT_B (1U << 21)
#define R12_SYS_CIRQ_IRQ_B (1U << 22)
#define R12_MD2AP_PEER_EVENT_B (1U << 23)
#define R12_CSYSPWREQ_B (1U << 24)
#define R12_MD1_WDT_B (1U << 25)
#define R12_CLDMA_EVENT_B (1U << 26)
#define R12_SEJ_EVENT_B (1U << 27)
#define R12_REG_CPU_WAKEUP (1U << 28)
#define R12_APUSYS_WAKE_HOST_B (1U << 29)
#define R12_NOT_USED1 (1U << 30)
#define R12_NOT_USED2 (1U << 31)
/* --- R12ext Define --- */
#define R12EXT_26M_WAKE (1U << 0)
#define R12EXT_26M_SLEEP (1U << 1)
#define R12EXT_INFRA_WAKE (1U << 2)
#define R12EXT_INFRA_SLEEP (1U << 3)
#define R12EXT_APSRC_WAKE (1U << 4)
#define R12EXT_APSRC_SLEEP (1U << 5)
#define R12EXT_VRF18_WAKE (1U << 6)
#define R12EXT_VRF18_SLEEP (1U << 7)
#define R12EXT_DVFS_WAKE (1U << 8)
#define R12EXT_DDREN_WAKE (1U << 9)
#define R12EXT_DDREN_SLEEP (1U << 10)
#define R12EXT_MCU_PM_WFI (1U << 11)
#define R12EXT_SSPM_IDLE (1U << 12)
#define R12EXT_CONN_SRCCLKENB (1U << 13)
#define R12EXT_DRAMC_SSPM_WFI_MERGE (1U << 14)
#define R12EXT_SW_MAILBOX_WAKE (1U << 15)
#define R12EXT_SSPM_MAILBOX_WAKE (1U << 16)
#define R12EXT_ADSP_MAILBOX_WAKE (1U << 17)
#define R12EXT_SCP_MAILBOX_WAKE (1U << 18)
#define R12EXT_SPM_LEAVE_SUSPEND_ACK (1U << 19)
#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK (1U << 20)
#define R12EXT_VS1_TRIGGER (1U << 21)
#define R12EXT_VS2_TRIGGER (1U << 22)
#define R12EXT_COROSS_REQ_APU (1U << 23)
#define R12EXT_CROSS_REQ_L3 (1U << 24)
#define R12EXT_DDR_PST_ACK (1U << 25)
#define R12EXT_BIT26 (1U << 26)
#define R12EXT_BIT27 (1U << 27)
#define R12EXT_BIT28 (1U << 28)
#define R12EXT_BIT29 (1U << 29)
#define R12EXT_BIT30 (1U << 30)
#define R12EXT_BIT31 (1U << 31)
/* --- R13 Define --- */
#define R13_SRCCLKENI0 (1U << 0)
#define R13_SRCCLKENI1 (1U << 1)
#define R13_MD_SRCCLKENA_0 (1U << 2)
#define R13_MD_APSRC_REQ_0 (1U << 3)
#define R13_CONN_DDR_EN (1U << 4)
#define R13_MD_SRCCLKENA_1 (1U << 5)
#define R13_SSPM_SRCCLKENA (1U << 6)
#define R13_SSPM_APSRC_REQ (1U << 7)
#define R13_MD1_STATE (1U << 8)
#define R13_BIT9 (1U << 9)
#define R13_MM_STATE (1U << 10)
#define R13_SSPM_STATE (1U << 11)
#define R13_MD_DDR_EN_0 (1U << 12)
#define R13_CONN_STATE (1U << 13)
#define R13_CONN_SRCCLKENA (1U << 14)
#define R13_CONN_APSRC_REQ (1U << 15)
#define R13_SC_DDR_PST_ACK_ALL (1U << 16)
#define R13_SC_DDR_PST_ABORT_ACK_ALL (1U << 17)
#define R13_SCP_STATE (1U << 18)
#define R13_CSYSPWRUPREQ (1U << 19)
#define R13_PWRAP_SLEEP_ACK (1U << 20)
#define R13_SC_EMI_CLK_OFF_ACK_ALL (1U << 21)
#define R13_AUDIO_DSP_STATE (1U << 22)
#define R13_SC_DMDRAMCSHU_ACK_ALL (1U << 23)
#define R13_CONN_SRCCLKENB (1U << 24)
#define R13_SC_DR_SRAM_LOAD_ACK_ALL (1U << 25)
#define R13_SUBSYS_IDLE_SIGNALS0 (1U << 26)
#define R13_DVFS_STATE (1U << 27)
#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL (1U << 28)
#define R13_SC_DR_SRAM_RESTORE_ACK_ALL (1U << 29)
#define R13_MD_VRF18_REQ_0 (1U << 30)
#define R13_DDR_EN_STATE (1U << 31)
#endif /* PCM_DEF_H */
plat/mediatek/mt8195/drivers/spm/sleep_def.h 0 → 100644
View file @ 7fa35d06
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SLEEP_DEF_H
#define SLEEP_DEF_H
/*
* Auto generated by DE, please DO NOT modify this file directly.
*/
/* --- SPM Flag Define --- */
#define SPM_FLAG_DISABLE_CPU_PDN (1U << 0)
#define SPM_FLAG_DISABLE_INFRA_PDN (1U << 1)
#define SPM_FLAG_DISABLE_DDRPHY_PDN (1U << 2)
#define SPM_FLAG_DISABLE_VCORE_DVS (1U << 3)
#define SPM_FLAG_DISABLE_VCORE_DFS (1U << 4)
#define SPM_FLAG_DISABLE_COMMON_SCENARIO (1U << 5)
#define SPM_FLAG_DISABLE_BUS_CLK_OFF (1U << 6)
#define SPM_FLAG_DISABLE_ARMPLL_OFF (1U << 7)
#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH (1U << 8)
#define SPM_FLAG_ENABLE_LVTS_WORKAROUND (1U << 9)
#define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10)
#define SPM_FLAG_RESERVED_BIT11 (1U << 11)
#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP (1U << 12)
#define SPM_FLAG_USE_SRCCLKENO2 (1U << 13)
#define SPM_FLAG_ENABLE_6315_CTRL (1U << 14)
#define SPM_FLAG_ENABLE_TIA_WORKAROUND (1U << 15)
#define SPM_FLAG_DISABLE_SYSRAM_SLEEP (1U << 16)
#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP (1U << 17)
#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP (1U << 18)
#define SPM_FLAG_DISABLE_DRAMC_ISSUE_CMD (1U << 19)
#define SPM_FLAG_ENABLE_VOLTAGE_BIN (1U << 20)
#define SPM_FLAG_RESERVED_BIT21 (1U << 21)
#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP (1U << 22)
#define SPM_FLAG_DISABLE_DRAMC_MD32_BACKUP (1U << 23)
#define SPM_FLAG_RESERVED_BIT24 (1U << 24)
#define SPM_FLAG_RESERVED_BIT25 (1U << 25)
#define SPM_FLAG_RESERVED_BIT26 (1U << 26)
#define SPM_FLAG_VTCXO_STATE (1U << 27)
#define SPM_FLAG_INFRA_STATE (1U << 28)
#define SPM_FLAG_APSRC_STATE (1U << 29)
#define SPM_FLAG_VRF18_STATE (1U << 30)
#define SPM_FLAG_DDREN_STATE (1U << 31)
/* --- SPM Flag1 Define --- */
#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M (1U << 0)
#define SPM_FLAG1_DISABLE_SYSPLL_OFF (1U << 1)
#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH (1U << 2)
#define SPM_FLAG1_DISABLE_ULPOSC_OFF (1U << 3)
#define SPM_FLAG1_FW_SET_ULPOSC_ON (1U << 4)
#define SPM_FLAG1_RESERVED_BIT5 (1U << 5)
#define SPM_FLAG1_ENABLE_REKICK (1U << 6)
#define SPM_FLAG1_RESERVED_BIT7 (1U << 7)
#define SPM_FLAG1_RESERVED_BIT8 (1U << 8)
#define SPM_FLAG1_RESERVED_BIT9 (1U << 9)
#define SPM_FLAG1_DISABLE_SRCLKEN_LOW (1U << 10)
#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH (1U << 11)
#define SPM_FLAG1_RESERVED_BIT12 (1U << 12)
#define SPM_FLAG1_RESERVED_BIT13 (1U << 13)
#define SPM_FLAG1_RESERVED_BIT14 (1U << 14)
#define SPM_FLAG1_RESERVED_BIT15 (1U << 15)
#define SPM_FLAG1_RESERVED_BIT16 (1U << 16)
#define SPM_FLAG1_RESERVED_BIT17 (1U << 17)
#define SPM_FLAG1_RESERVED_BIT18 (1U << 18)
#define SPM_FLAG1_RESERVED_BIT19 (1U << 19)
#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP (1U << 20)
#define SPM_FLAG1_RESERVED_BIT21 (1U << 21)
#define SPM_FLAG1_ENABLE_VS1_VOTER (1U << 22)
#define SPM_FLAG1_ENABLE_VS2_VOTER (1U << 23)
#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL (1U << 24)
#define SPM_FLAG1_RESERVED_BIT25 (1U << 25)
#define SPM_FLAG1_RESERVED_BIT26 (1U << 26)
#define SPM_FLAG1_RESERVED_BIT27 (1U << 27)
#define SPM_FLAG1_RESERVED_BIT28 (1U << 28)
#define SPM_FLAG1_RESERVED_BIT29 (1U << 29)
#define SPM_FLAG1_RESERVED_BIT30 (1U << 30)
#define SPM_FLAG1_RESERVED_BIT31 (1U << 31)
/* --- SPM DEBUG Define --- */
#define SPM_DBG_DEBUG_IDX_26M_WAKE (1U << 0)
#define SPM_DBG_DEBUG_IDX_26M_SLEEP (1U << 1)
#define SPM_DBG_DEBUG_IDX_INFRA_WAKE (1U << 2)
#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP (1U << 3)
#define SPM_DBG_DEBUG_IDX_APSRC_WAKE (1U << 4)
#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP (1U << 5)
#define SPM_DBG_DEBUG_IDX_VRF18_WAKE (1U << 6)
#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP (1U << 7)
#define SPM_DBG_DEBUG_IDX_DDREN_WAKE (1U << 8)
#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP (1U << 9)
#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC (1U << 10)
#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE (1U << 11)
#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE (1U << 12)
#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN (1U << 13)
#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE (1U << 14)
#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP (1U << 15)
#define SPM_DBG_DEBUG_IDX_SYSRAM_ON (1U << 16)
#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP (1U << 17)
#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON (1U << 18)
#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP (1U << 19)
#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON (1U << 20)
#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP (1U << 21)
#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON (1U << 22)
#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P575V (1U << 23)
#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P600V (1U << 24)
#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P650V (1U << 25)
#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P725V (1U << 26)
#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW (1U << 27)
#define SPM_DBG_DEBUG_IDX_VTCXO_STATE (1U << 28)
#define SPM_DBG_DEBUG_IDX_INFRA_STATE (1U << 29)
#define SPM_DBG_DEBUG_IDX_VRR18_STATE (1U << 30)
#define SPM_DBG_DEBUG_IDX_APSRC_STATE (1U << 31)
/* --- SPM DEBUG1 Define --- */
#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP (1U << 0)
#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START (1U << 1)
#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF (1U << 2)
#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON (1U << 3)
#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS (1U << 4)
#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF (1U << 5)
#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON (1U << 6)
#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT (1U << 7)
#define SPM_DBG1_RESERVED_BIT8 (1U << 8)
#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_OFF (1U << 9)
#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_ON (1U << 10)
#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC (1U << 11)
#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M (1U << 12)
#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K (1U << 13)
#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M (1U << 14)
#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF (1U << 15)
#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON (1U << 16)
#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW (1U << 17)
#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH (1U << 18)
#define SPM_DBG1_RESERVED_BIT19 (1U << 19)
#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON (1U << 20)
#define SPM_DBG1_DEBUG_IDX_6315_LOW (1U << 21)
#define SPM_DBG1_DEBUG_IDX_6315_HIGH (1U << 22)
#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT (1U << 23)
#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT (1U << 24)
#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT (1U << 25)
#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT (1U << 26)
#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT (1U << 27)
#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT (1U << 28)
#define SPM_DBG1_RESERVED_BIT29 (1U << 29)
#define SPM_DBG1_RESERVED_BIT30 (1U << 30)
#define SPM_DBG1_RESERVED_BIT31 (1U << 31)
/* Macro and Inline */
#define is_cpu_pdn(flags) (((flags) & SPM_FLAG_DISABLE_CPU_PDN) == 0U)
#define is_infra_pdn(flags) (((flags) & SPM_FLAG_DISABLE_INFRA_PDN) == 0U)
#define is_ddrphy_pdn(flags) (((flags) & SPM_FLAG_DISABLE_DDRPHY_PDN) == 0U)
#endif /* SLEEP_DEF_H */
plat/mediatek/mt8195/include/plat_mtk_lpm.h
View file @ 7fa35d06
/* /*
* Copyright (c) 2020, MediaTek Inc. All rights reserved. * Copyright (c) 2021, MediaTek Inc. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
#include <lib/psci/psci.h> #include <lib/psci/psci.h>
#include <lib/utils_def.h> #include <lib/utils_def.h>
#define MT_IRQ_REMAIN_MAX U(8) #define MT_IRQ_REMAIN_MAX U(32)
#define MT_IRQ_REMAIN_CAT_LOG BIT(31) #define MT_IRQ_REMAIN_CAT_LOG BIT(31)
struct mt_irqremain { struct mt_irqremain {
......
plat/mediatek/mt8195/include/platform_def.h
View file @ 7fa35d06
...@@ -15,15 +15,22 @@ ...@@ -15,15 +15,22 @@
/* Aggregate of all devices for MMU mapping */ /* Aggregate of all devices for MMU mapping */
#define MTK_DEV_RNG0_BASE IO_PHYS #define MTK_DEV_RNG0_BASE IO_PHYS
#define MTK_DEV_RNG0_SIZE 0x400000 #define MTK_DEV_RNG0_SIZE 0x10000000
#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000)
#define MTK_DEV_RNG1_SIZE 0xa110000
#define MTK_DEV_RNG2_BASE MT_GIC_BASE #define MTK_DEV_RNG2_BASE MT_GIC_BASE
#define MTK_DEV_RNG2_SIZE 0x600000 #define MTK_DEV_RNG2_SIZE 0x600000
#define MTK_MCDI_SRAM_BASE 0x11B000 #define MTK_MCDI_SRAM_BASE 0x11B000
#define MTK_MCDI_SRAM_MAP_SIZE 0x1000 #define MTK_MCDI_SRAM_MAP_SIZE 0x1000
#define TOPCKGEN_BASE (IO_PHYS + 0x00000000)
#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
#define SPM_BASE (IO_PHYS + 0x00006000) #define SPM_BASE (IO_PHYS + 0x00006000)
#define APMIXEDSYS (IO_PHYS + 0x0000C000)
#define SSPM_MBOX_BASE (IO_PHYS + 0x00480000)
#define PERICFG_AO_BASE (IO_PHYS + 0x01003000)
#define VPPSYS0_BASE (IO_PHYS + 0x04000000)
#define VPPSYS1_BASE (IO_PHYS + 0x04f00000)
#define VDOSYS0_BASE (IO_PHYS + 0x0C01A000)
#define VDOSYS1_BASE (IO_PHYS + 0x0C100000)
/******************************************************************************* /*******************************************************************************
* DP/eDP related constants * DP/eDP related constants
......
plat/mediatek/mt8195/plat_pm.c
View file @ 7fa35d06
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
/* platform specific headers */ /* platform specific headers */
#include <mt_gic_v3.h> #include <mt_gic_v3.h>
#include <mtk_ptp3_common.h>
#include <mtspmc.h> #include <mtspmc.h>
#include <plat/common/platform.h> #include <plat/common/platform.h>
#include <plat_mtk_lpm.h> #include <plat_mtk_lpm.h>
...@@ -84,10 +85,8 @@ static void plat_cpu_pwron_common(unsigned int cpu, ...@@ -84,10 +85,8 @@ static void plat_cpu_pwron_common(unsigned int cpu,
coordinate_cluster_pwron(); coordinate_cluster_pwron();
/* Enable the GIC CPU interface */ /* PTP3 config */
gicv3_rdistif_on(cpu); ptp3_core_init(cpu);
gicv3_cpuif_enable(cpu);
mt_gic_rdistif_init();
/* /*
* If mcusys does power down before then restore * If mcusys does power down before then restore
...@@ -96,6 +95,9 @@ static void plat_cpu_pwron_common(unsigned int cpu, ...@@ -96,6 +95,9 @@ static void plat_cpu_pwron_common(unsigned int cpu,
if (IS_MCUSYS_OFF_STATE(state)) { if (IS_MCUSYS_OFF_STATE(state)) {
mt_gic_rdistif_restore_all(); mt_gic_rdistif_restore_all();
} else { } else {
gicv3_rdistif_on(cpu);
gicv3_cpuif_enable(cpu);
mt_gic_rdistif_init();
mt_gic_rdistif_restore(); mt_gic_rdistif_restore();
} }
} }
......
plat/mediatek/mt8195/platform.mk
View file @ 7fa35d06
...@@ -12,11 +12,14 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ ...@@ -12,11 +12,14 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT}/common/drivers/gpio/ \ -I${MTK_PLAT}/common/drivers/gpio/ \
-I${MTK_PLAT}/common/drivers/rtc/ \ -I${MTK_PLAT}/common/drivers/rtc/ \
-I${MTK_PLAT}/common/drivers/timer/ \ -I${MTK_PLAT}/common/drivers/timer/ \
-I${MTK_PLAT}/common/drivers/uart/ \
-I${MTK_PLAT}/common/lpm/ \
-I${MTK_PLAT_SOC}/drivers/dp/ \ -I${MTK_PLAT_SOC}/drivers/dp/ \
-I${MTK_PLAT_SOC}/drivers/gpio/ \ -I${MTK_PLAT_SOC}/drivers/gpio/ \
-I${MTK_PLAT_SOC}/drivers/mcdi/ \ -I${MTK_PLAT_SOC}/drivers/mcdi/ \
-I${MTK_PLAT_SOC}/drivers/pmic/ \ -I${MTK_PLAT_SOC}/drivers/pmic/ \
-I${MTK_PLAT_SOC}/drivers/spmc/ \ -I${MTK_PLAT_SOC}/drivers/spmc/ \
-I${MTK_PLAT_SOC}/drivers/ptp3/ \
-I${MTK_PLAT_SOC}/include/ -I${MTK_PLAT_SOC}/include/
GICV3_SUPPORT_GIC600 := 1 GICV3_SUPPORT_GIC600 := 1
...@@ -44,6 +47,8 @@ BL31_SOURCES += common/desc_image_load.c \ ...@@ -44,6 +47,8 @@ BL31_SOURCES += common/desc_image_load.c \
${MTK_PLAT}/common/drivers/rtc/rtc_common.c \ ${MTK_PLAT}/common/drivers/rtc/rtc_common.c \
${MTK_PLAT}/common/drivers/rtc/rtc_mt6359p.c \ ${MTK_PLAT}/common/drivers/rtc/rtc_mt6359p.c \
${MTK_PLAT}/common/drivers/timer/mt_timer.c \ ${MTK_PLAT}/common/drivers/timer/mt_timer.c \
${MTK_PLAT}/common/drivers/uart/uart.c \
${MTK_PLAT}/common/lpm/mt_lp_rm.c \
${MTK_PLAT}/common/mtk_cirq.c \ ${MTK_PLAT}/common/mtk_cirq.c \
${MTK_PLAT}/common/mtk_plat_common.c \ ${MTK_PLAT}/common/mtk_plat_common.c \
${MTK_PLAT}/common/mtk_sip_svc.c \ ${MTK_PLAT}/common/mtk_sip_svc.c \
...@@ -56,13 +61,18 @@ BL31_SOURCES += common/desc_image_load.c \ ...@@ -56,13 +61,18 @@ BL31_SOURCES += common/desc_image_load.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \ ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \ ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c \ ${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c \
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \ ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
${MTK_PLAT_SOC}/drivers/pmic/pmic.c \ ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \
${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c \
${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \ ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \
${MTK_PLAT_SOC}/plat_pm.c \ ${MTK_PLAT_SOC}/plat_pm.c \
${MTK_PLAT_SOC}/plat_sip_calls.c \ ${MTK_PLAT_SOC}/plat_sip_calls.c \
${MTK_PLAT_SOC}/plat_topology.c ${MTK_PLAT_SOC}/plat_topology.c
# Build SPM drivers
include ${MTK_PLAT_SOC}/drivers/spm/build.mk
# Configs for A78 and A55 # Configs for A78 and A55
HW_ASSISTED_COHERENCY := 1 HW_ASSISTED_COHERENCY := 1
USE_COHERENT_MEM := 0 USE_COHERENT_MEM := 0
......
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