From 8074448f096615a94d7bb54aa70a7dbfa6053ab4 Mon Sep 17 00:00:00 2001
From: John Tsichritzis <john.tsichritzis@arm.com>
Date: Mon, 4 Mar 2019 16:41:26 +0000
Subject: [PATCH] Apply variant 4 mitigation for Neoverse N1

This patch applies the new MSR instruction to directly set the
PSTATE.SSBS bit which controls speculative loads. This new instruction
is available at Neoverse N1 core so it's utilised.

Change-Id: Iee18a8b042c90fdb72d2b98f364dcfbb17510728
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
---
 include/arch/aarch64/arch.h    | 5 +++++
 lib/cpus/aarch64/neoverse_n1.S | 4 ++++
 2 files changed, 9 insertions(+)

diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index debe8722c..d3c5beaad 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -843,4 +843,9 @@
 #define DIT			S3_3_C4_C2_5
 #define DIT_BIT			BIT(24)
 
+/*******************************************************************************
+ * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field
+ ******************************************************************************/
+#define SSBS			S3_3_C4_C2_6
+
 #endif /* ARCH_H */
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index c6a5c08f9..060c625d4 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -46,6 +46,10 @@ endfunc check_errata_1043202
 
 func neoverse_n1_reset_func
 	mov	x19, x30
+
+	/* Disables speculative loads */
+	msr	SSBS, xzr
+
 	bl	cpu_get_rev_var
 	mov	x18, x0
 
-- 
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