Commit 80fb66b3 authored by Sandrine Bailleux's avatar Sandrine Bailleux
Browse files

Rockchip: Add some debug assertions in the PMU driver

This patch adds some debug assertions ensuring that array indices
are within the bounds of the array.

Change-Id: I96ee81d14834c1e92cdfb7e60b49995cdacfd93a
parent 8fc83577
...@@ -349,6 +349,7 @@ static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint) ...@@ -349,6 +349,7 @@ static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint)
cpus_id_power_domain(cluster, cpu, pmu_pd_off, CKECK_WFEI_MSK); cpus_id_power_domain(cluster, cpu, pmu_pd_off, CKECK_WFEI_MSK);
cpuon_id = (cluster * PLATFORM_CLUSTER0_CORE_COUNT) + cpu; cpuon_id = (cluster * PLATFORM_CLUSTER0_CORE_COUNT) + cpu;
assert(cpuon_id < PLATFORM_CORE_COUNT);
assert(cpuson_flags[cpuon_id] == 0); assert(cpuson_flags[cpuon_id] == 0);
cpuson_flags[cpuon_id] = PMU_CPU_HOTPLUG; cpuson_flags[cpuon_id] = PMU_CPU_HOTPLUG;
cpuson_entry_point[cpuon_id] = entrypoint; cpuson_entry_point[cpuon_id] = entrypoint;
......
...@@ -132,11 +132,13 @@ void plat_rockchip_pmusram_prepare(void) ...@@ -132,11 +132,13 @@ void plat_rockchip_pmusram_prepare(void)
static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id) static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id)
{ {
assert(cpu_id < PLATFORM_CORE_COUNT);
return core_pm_cfg_info[cpu_id]; return core_pm_cfg_info[cpu_id];
} }
static inline void set_cpus_pwr_domain_cfg_info(uint32_t cpu_id, uint32_t value) static inline void set_cpus_pwr_domain_cfg_info(uint32_t cpu_id, uint32_t value)
{ {
assert(cpu_id < PLATFORM_CORE_COUNT);
core_pm_cfg_info[cpu_id] = value; core_pm_cfg_info[cpu_id] = value;
#if !USE_COHERENT_MEM #if !USE_COHERENT_MEM
flush_dcache_range((uintptr_t)&core_pm_cfg_info[cpu_id], flush_dcache_range((uintptr_t)&core_pm_cfg_info[cpu_id],
...@@ -234,6 +236,7 @@ static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint) ...@@ -234,6 +236,7 @@ static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint)
{ {
uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
assert(cpu_id < PLATFORM_CORE_COUNT);
assert(cpuson_flags[cpu_id] == 0); assert(cpuson_flags[cpu_id] == 0);
cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG; cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG;
cpuson_entry_point[cpu_id] = entrypoint; cpuson_entry_point[cpu_id] = entrypoint;
...@@ -257,6 +260,7 @@ static int cores_pwr_domain_suspend(void) ...@@ -257,6 +260,7 @@ static int cores_pwr_domain_suspend(void)
{ {
uint32_t cpu_id = plat_my_core_pos(); uint32_t cpu_id = plat_my_core_pos();
assert(cpu_id < PLATFORM_CORE_COUNT);
assert(cpuson_flags[cpu_id] == 0); assert(cpuson_flags[cpu_id] == 0);
cpuson_flags[cpu_id] = PMU_CPU_AUTO_PWRDN; cpuson_flags[cpu_id] = PMU_CPU_AUTO_PWRDN;
cpuson_entry_point[cpu_id] = (uintptr_t)psci_entrypoint; cpuson_entry_point[cpu_id] = (uintptr_t)psci_entrypoint;
......
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