Commit 81646055 authored by Grzegorz Jaszczyk's avatar Grzegorz Jaszczyk Committed by Marcin Wojtas
Browse files

plat: marvell: armada: add support for loading MG CM3 images



In order to access MG SRAM, the amb bridge needs to be configured which is
done in bl2 platform init.

For MG CM3, the image is only loaded to its SRAM and the CM3 itself is
left in reset. It is because the next stage bootloader (e.g. u-boot)
will trigger action which will take it out of reset when needed. This
can happen e.g. when appropriate device-tree setup (which has enabled
802.3 auto-neg) will be chosen. In other cases the MG CM3 should not be
running.

Change-Id: I816ea14e3a7174eace068ec44e3cc09998d0337e
Signed-off-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
parent f69a5828
...@@ -303,7 +303,7 @@ static void cp110_axi_attr_init(uintptr_t base) ...@@ -303,7 +303,7 @@ static void cp110_axi_attr_init(uintptr_t base)
DOMAIN_SYSTEM_SHAREABLE); DOMAIN_SYSTEM_SHAREABLE);
} }
static void amb_bridge_init(uintptr_t base) void cp110_amb_init(uintptr_t base)
{ {
uint32_t reg; uint32_t reg;
...@@ -399,7 +399,7 @@ void cp110_init(uintptr_t cp110_base, uint32_t stream_id) ...@@ -399,7 +399,7 @@ void cp110_init(uintptr_t cp110_base, uint32_t stream_id)
cp110_stream_id_init(cp110_base, stream_id); cp110_stream_id_init(cp110_base, stream_id);
/* Open AMB bridge for comphy for CP0 & CP1*/ /* Open AMB bridge for comphy for CP0 & CP1*/
amb_bridge_init(cp110_base); cp110_amb_init(cp110_base);
/* Reset RTC if needed */ /* Reset RTC if needed */
cp110_rtc_init(cp110_base); cp110_rtc_init(cp110_base);
...@@ -411,7 +411,7 @@ void cp110_ble_init(uintptr_t cp110_base) ...@@ -411,7 +411,7 @@ void cp110_ble_init(uintptr_t cp110_base)
#if PCI_EP_SUPPORT #if PCI_EP_SUPPORT
INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base); INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base);
amb_bridge_init(cp110_base); cp110_amb_init(cp110_base);
/* Configure PCIe clock */ /* Configure PCIe clock */
cp110_pcie_clk_cfg(cp110_base); cp110_pcie_clk_cfg(cp110_base);
......
...@@ -51,5 +51,6 @@ static inline uint32_t cp110_rev_id_get(uintptr_t base) ...@@ -51,5 +51,6 @@ static inline uint32_t cp110_rev_id_get(uintptr_t base)
void cp110_init(uintptr_t cp110_base, uint32_t stream_id); void cp110_init(uintptr_t cp110_base, uint32_t stream_id);
void cp110_ble_init(uintptr_t cp110_base); void cp110_ble_init(uintptr_t cp110_base);
void cp110_amb_init(uintptr_t base);
#endif /* CP110_SETUP_H */ #endif /* CP110_SETUP_H */
...@@ -8,7 +8,8 @@ ...@@ -8,7 +8,8 @@
PLAT_MARVELL := plat/marvell PLAT_MARVELL := plat/marvell
A8K_MSS_SOURCE := $(PLAT_MARVELL)/a8k/common/mss A8K_MSS_SOURCE := $(PLAT_MARVELL)/a8k/common/mss
BL2_SOURCES += $(A8K_MSS_SOURCE)/mss_bl2_setup.c BL2_SOURCES += $(A8K_MSS_SOURCE)/mss_bl2_setup.c \
$(MARVELL_MOCHI_DRV)
BL31_SOURCES += $(A8K_MSS_SOURCE)/mss_pm_ipc.c BL31_SOURCES += $(A8K_MSS_SOURCE)/mss_pm_ipc.c
......
...@@ -74,6 +74,12 @@ static int bl2_plat_mmap_init(void) ...@@ -74,6 +74,12 @@ static int bl2_plat_mmap_init(void)
/* Set the default target id to PIDI */ /* Set the default target id to PIDI */
mmio_write_32(MVEBU_IO_WIN_BASE(MVEBU_AP0) + IOW_GCR_OFFSET, PIDI_TID); mmio_write_32(MVEBU_IO_WIN_BASE(MVEBU_AP0) + IOW_GCR_OFFSET, PIDI_TID);
/* Open AMB bridge required for MG access */
cp110_amb_init(MVEBU_CP_REGS_BASE(0));
if (CP_COUNT == 2)
cp110_amb_init(MVEBU_CP_REGS_BASE(1));
return 0; return 0;
} }
......
...@@ -42,6 +42,8 @@ ...@@ -42,6 +42,8 @@
#define MSS_HANDSHAKE_TIMEOUT 50 #define MSS_HANDSHAKE_TIMEOUT 50
#define MG_CM3_SRAM_BASE(CP) (MVEBU_CP_REGS_BASE(CP) + 0x100000)
static int mss_check_image_ready(volatile struct mss_pm_ctrl_block *mss_pm_crtl) static int mss_check_image_ready(volatile struct mss_pm_ctrl_block *mss_pm_crtl)
{ {
int timeout = MSS_HANDSHAKE_TIMEOUT; int timeout = MSS_HANDSHAKE_TIMEOUT;
...@@ -59,6 +61,28 @@ static int mss_check_image_ready(volatile struct mss_pm_ctrl_block *mss_pm_crtl) ...@@ -59,6 +61,28 @@ static int mss_check_image_ready(volatile struct mss_pm_ctrl_block *mss_pm_crtl)
return 0; return 0;
} }
static int mg_image_load(uintptr_t src_addr, uint32_t size, uintptr_t mg_regs)
{
if (size > MG_SRAM_SIZE) {
ERROR("image is too big to fit into MG CM3 memory\n");
return 1;
}
NOTICE("Loading MG image from address 0x%lx Size 0x%x to MG at 0x%lx\n",
src_addr, size, mg_regs);
/* Copy image to MG CM3 SRAM */
memcpy((void *)mg_regs, (void *)src_addr, size);
/*
* Don't release MG CM3 from reset - it will be done by next step
* bootloader (e.g. U-Boot), when appriopriate device-tree setup (which
* has enabeld 802.3. auto-neg) will be choosen.
*/
return 0;
}
static int mss_image_load(uint32_t src_addr, uint32_t size, uintptr_t mss_regs) static int mss_image_load(uint32_t src_addr, uint32_t size, uintptr_t mss_regs)
{ {
uint32_t i, loop_num, timeout; uint32_t i, loop_num, timeout;
...@@ -225,12 +249,15 @@ static int load_img_to_cm3(enum cm3_t cm3_type, ...@@ -225,12 +249,15 @@ static int load_img_to_cm3(enum cm3_t cm3_type,
} }
break; break;
case MG_CP0: case MG_CP0:
/* TODO: */
NOTICE("Load image to CP0 MG not supported\n");
break;
case MG_CP1: case MG_CP1:
/* TODO: */ cp_index = cm3_type - MG_CP0;
NOTICE("Load image to CP1 MG not supported\n"); NOTICE("Load image to CP%d MG\n", cp_index);
ret = mg_image_load(single_img, image_size,
MG_CM3_SRAM_BASE(cp_index));
if (ret != 0) {
ERROR("SCP Image load failed\n");
return -1;
}
break; break;
default: default:
ERROR("SCP_BL2 wrong img format (cm3_type=%d)\n", cm3_type); ERROR("SCP_BL2 wrong img format (cm3_type=%d)\n", cm3_type);
......
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