From 83314d087a90a781f759a7a5cb19d421bf0bf433 Mon Sep 17 00:00:00 2001 From: Marek Vasut <marek.vasut+renesas@gmail.com> Date: Sat, 15 Jun 2019 14:55:29 +0200 Subject: [PATCH] rcar_gen3: drivers: qos: D3: Replace ad-hoc register addresses with macros Replace the remaining ad-hoc register addresses with proper macros. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: If125f0c8ef77ed280107324edaa05f21979a2c27 --- .../staging/renesas/rcar/qos/D3/qos_init_d3.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c b/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c index dd9c4c531..bc8c589f9 100644 --- a/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c +++ b/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c @@ -126,17 +126,17 @@ void qos_init_d3(void) } /* 3DG bus Leaf setting */ - io_write_32(0xFD820808U, 0x00001234U); - io_write_32(0xFD820800U, 0x00000000U); - io_write_32(0xFD821800U, 0x00000000U); - io_write_32(0xFD822800U, 0x00000000U); - io_write_32(0xFD823800U, 0x00000000U); + io_write_32(GPU_ACT_GRD, 0x00001234U); + io_write_32(GPU_ACT0, 0x00000000U); + io_write_32(GPU_ACT1, 0x00000000U); + io_write_32(GPU_ACT2, 0x00000000U); + io_write_32(GPU_ACT3, 0x00000000U); /* RT bus Leaf setting */ - io_write_32(0xF1300800U, 0x00000003U); - io_write_32(0xF1340800U, 0x00000003U); - io_write_32(0xFFC50800U, 0x00000000U); - io_write_32(0xFFC51800U, 0x00000000U); + io_write_32(CPU_ACT0, 0x00000003U); + io_write_32(CPU_ACT1, 0x00000003U); + io_write_32(RT_ACT0, 0x00000000U); + io_write_32(RT_ACT1, 0x00000000U); /* Resource Alloc start */ io_write_32(QOSCTRL_RAEN, 0x00000001U); -- GitLab