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Commit 859df7d5 authored by Madhukar Pappireddy's avatar Madhukar Pappireddy Committed by TrustedFirmware Code Review
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Merge changes from topic "tegra-downstream-08252020" into integration 

* changes:
  Tegra194: remove unused tegra_mc_defs header
  Tegra: memctrl: platform setup handler functions
  Tegra194: memctrl: remove streamid security cfg registers
  Tegra194: memctrl: remove streamid override cfg registers
  Tegra: debug prints indicating SC7 entry sequence completion
  Tegra194: add strict checking mode verification
  Tegra194: memctrl: update TZDRAM base at 1MB granularity
  Tegra194: ras: split up RAS error clear SMC call.
  Tegra: platform specific GIC sources
  Tegra194: add memory barriers during DRAM to SysRAM copy
  Tegra: sip: add VPR resize enabled check
  Tegra194: add redundancy checks for MMIO writes
  Tegra: remove unused cortex_a53.h
  Tegra194: report failure to enable dual execution
  Tegra194: verify firewall settings before resource use
parents 90b0cad4 837df485
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plat/nvidia/tegra/soc/t194/plat_memctrl.c
View file @ 859df7d5
......@@ -8,406 +8,14 @@
#include <common/bl_common.h>
#include <mce.h>
#include <memctrl_v2.h>
#include <tegra_mc_def.h>
#include <tegra_platform.h>
/*******************************************************************************
* Array to hold the security configs for stream IDs
******************************************************************************/
const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = {
mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(PCIE0R1, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(NVDEC1SRD, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(NVDEC1SRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(NVDEC1SWR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(MIU4R, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(MIU4W, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(MIU5R, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(MIU5W, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(MIU6R, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(MIU6W, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(MIU7R, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(MIU7W, NON_SECURE, OVERRIDE, DISABLE)
};
#include <tegra_private.h>
/*******************************************************************************
* Array to hold MC context for Tegra194
******************************************************************************/
static __attribute__((aligned(16))) mc_regs_t tegra194_mc_context[] = {
_START_OF_TABLE_,
mc_make_sid_security_cfg(HDAR),
mc_make_sid_security_cfg(HOST1XDMAR),
mc_make_sid_security_cfg(NVENCSRD),
mc_make_sid_security_cfg(SATAR),
mc_make_sid_security_cfg(NVENCSWR),
mc_make_sid_security_cfg(HDAW),
mc_make_sid_security_cfg(SATAW),
mc_make_sid_security_cfg(ISPRA),
mc_make_sid_security_cfg(ISPFALR),
mc_make_sid_security_cfg(ISPWA),
mc_make_sid_security_cfg(ISPWB),
mc_make_sid_security_cfg(XUSB_HOSTR),
mc_make_sid_security_cfg(XUSB_HOSTW),
mc_make_sid_security_cfg(XUSB_DEVR),
mc_make_sid_security_cfg(XUSB_DEVW),
mc_make_sid_security_cfg(TSECSRD),
mc_make_sid_security_cfg(TSECSWR),
mc_make_sid_security_cfg(SDMMCRA),
mc_make_sid_security_cfg(SDMMCR),
mc_make_sid_security_cfg(SDMMCRAB),
mc_make_sid_security_cfg(SDMMCWA),
mc_make_sid_security_cfg(SDMMCW),
mc_make_sid_security_cfg(SDMMCWAB),
mc_make_sid_security_cfg(VICSRD),
mc_make_sid_security_cfg(VICSWR),
mc_make_sid_security_cfg(VIW),
mc_make_sid_security_cfg(NVDECSRD),
mc_make_sid_security_cfg(NVDECSWR),
mc_make_sid_security_cfg(APER),
mc_make_sid_security_cfg(APEW),
mc_make_sid_security_cfg(NVJPGSRD),
mc_make_sid_security_cfg(NVJPGSWR),
mc_make_sid_security_cfg(SESRD),
mc_make_sid_security_cfg(SESWR),
mc_make_sid_security_cfg(AXIAPR),
mc_make_sid_security_cfg(AXIAPW),
mc_make_sid_security_cfg(ETRR),
mc_make_sid_security_cfg(ETRW),
mc_make_sid_security_cfg(TSECSRDB),
mc_make_sid_security_cfg(TSECSWRB),
mc_make_sid_security_cfg(AXISR),
mc_make_sid_security_cfg(AXISW),
mc_make_sid_security_cfg(EQOSR),
mc_make_sid_security_cfg(EQOSW),
mc_make_sid_security_cfg(UFSHCR),
mc_make_sid_security_cfg(UFSHCW),
mc_make_sid_security_cfg(NVDISPLAYR),
mc_make_sid_security_cfg(BPMPR),
mc_make_sid_security_cfg(BPMPW),
mc_make_sid_security_cfg(BPMPDMAR),
mc_make_sid_security_cfg(BPMPDMAW),
mc_make_sid_security_cfg(AONR),
mc_make_sid_security_cfg(AONW),
mc_make_sid_security_cfg(AONDMAR),
mc_make_sid_security_cfg(AONDMAW),
mc_make_sid_security_cfg(SCER),
mc_make_sid_security_cfg(SCEW),
mc_make_sid_security_cfg(SCEDMAR),
mc_make_sid_security_cfg(SCEDMAW),
mc_make_sid_security_cfg(APEDMAR),
mc_make_sid_security_cfg(APEDMAW),
mc_make_sid_security_cfg(NVDISPLAYR1),
mc_make_sid_security_cfg(VICSRD1),
mc_make_sid_security_cfg(NVDECSRD1),
mc_make_sid_security_cfg(VIFALR),
mc_make_sid_security_cfg(VIFALW),
mc_make_sid_security_cfg(DLA0RDA),
mc_make_sid_security_cfg(DLA0FALRDB),
mc_make_sid_security_cfg(DLA0WRA),
mc_make_sid_security_cfg(DLA0FALWRB),
mc_make_sid_security_cfg(DLA1RDA),
mc_make_sid_security_cfg(DLA1FALRDB),
mc_make_sid_security_cfg(DLA1WRA),
mc_make_sid_security_cfg(DLA1FALWRB),
mc_make_sid_security_cfg(PVA0RDA),
mc_make_sid_security_cfg(PVA0RDB),
mc_make_sid_security_cfg(PVA0RDC),
mc_make_sid_security_cfg(PVA0WRA),
mc_make_sid_security_cfg(PVA0WRB),
mc_make_sid_security_cfg(PVA0WRC),
mc_make_sid_security_cfg(PVA1RDA),
mc_make_sid_security_cfg(PVA1RDB),
mc_make_sid_security_cfg(PVA1RDC),
mc_make_sid_security_cfg(PVA1WRA),
mc_make_sid_security_cfg(PVA1WRB),
mc_make_sid_security_cfg(PVA1WRC),
mc_make_sid_security_cfg(RCER),
mc_make_sid_security_cfg(RCEW),
mc_make_sid_security_cfg(RCEDMAR),
mc_make_sid_security_cfg(RCEDMAW),
mc_make_sid_security_cfg(NVENC1SRD),
mc_make_sid_security_cfg(NVENC1SWR),
mc_make_sid_security_cfg(PCIE0R),
mc_make_sid_security_cfg(PCIE0W),
mc_make_sid_security_cfg(PCIE1R),
mc_make_sid_security_cfg(PCIE1W),
mc_make_sid_security_cfg(PCIE2AR),
mc_make_sid_security_cfg(PCIE2AW),
mc_make_sid_security_cfg(PCIE3R),
mc_make_sid_security_cfg(PCIE3W),
mc_make_sid_security_cfg(PCIE4R),
mc_make_sid_security_cfg(PCIE4W),
mc_make_sid_security_cfg(PCIE5R),
mc_make_sid_security_cfg(PCIE5W),
mc_make_sid_security_cfg(ISPFALW),
mc_make_sid_security_cfg(DLA0RDA1),
mc_make_sid_security_cfg(DLA1RDA1),
mc_make_sid_security_cfg(PVA0RDA1),
mc_make_sid_security_cfg(PVA0RDB1),
mc_make_sid_security_cfg(PVA1RDA1),
mc_make_sid_security_cfg(PVA1RDB1),
mc_make_sid_security_cfg(PCIE5R1),
mc_make_sid_security_cfg(NVENCSRD1),
mc_make_sid_security_cfg(NVENC1SRD1),
mc_make_sid_security_cfg(ISPRA1),
mc_make_sid_security_cfg(PCIE0R1),
mc_make_sid_security_cfg(MIU0R),
mc_make_sid_security_cfg(MIU0W),
mc_make_sid_security_cfg(MIU1R),
mc_make_sid_security_cfg(MIU1W),
mc_make_sid_security_cfg(MIU2R),
mc_make_sid_security_cfg(MIU2W),
mc_make_sid_security_cfg(MIU3R),
mc_make_sid_security_cfg(MIU3W),
mc_make_sid_override_cfg(HDAR),
mc_make_sid_override_cfg(HOST1XDMAR),
mc_make_sid_override_cfg(NVENCSRD),
mc_make_sid_override_cfg(SATAR),
mc_make_sid_override_cfg(NVENCSWR),
mc_make_sid_override_cfg(HDAW),
mc_make_sid_override_cfg(SATAW),
mc_make_sid_override_cfg(ISPRA),
mc_make_sid_override_cfg(ISPFALR),
mc_make_sid_override_cfg(ISPWA),
mc_make_sid_override_cfg(ISPWB),
mc_make_sid_override_cfg(XUSB_HOSTR),
mc_make_sid_override_cfg(XUSB_HOSTW),
mc_make_sid_override_cfg(XUSB_DEVR),
mc_make_sid_override_cfg(XUSB_DEVW),
mc_make_sid_override_cfg(TSECSRD),
mc_make_sid_override_cfg(TSECSWR),
mc_make_sid_override_cfg(SDMMCRA),
mc_make_sid_override_cfg(SDMMCR),
mc_make_sid_override_cfg(SDMMCRAB),
mc_make_sid_override_cfg(SDMMCWA),
mc_make_sid_override_cfg(SDMMCW),
mc_make_sid_override_cfg(SDMMCWAB),
mc_make_sid_override_cfg(VICSRD),
mc_make_sid_override_cfg(VICSWR),
mc_make_sid_override_cfg(VIW),
mc_make_sid_override_cfg(NVDECSRD),
mc_make_sid_override_cfg(NVDECSWR),
mc_make_sid_override_cfg(APER),
mc_make_sid_override_cfg(APEW),
mc_make_sid_override_cfg(NVJPGSRD),
mc_make_sid_override_cfg(NVJPGSWR),
mc_make_sid_override_cfg(SESRD),
mc_make_sid_override_cfg(SESWR),
mc_make_sid_override_cfg(AXIAPR),
mc_make_sid_override_cfg(AXIAPW),
mc_make_sid_override_cfg(ETRR),
mc_make_sid_override_cfg(ETRW),
mc_make_sid_override_cfg(TSECSRDB),
mc_make_sid_override_cfg(TSECSWRB),
mc_make_sid_override_cfg(AXISR),
mc_make_sid_override_cfg(AXISW),
mc_make_sid_override_cfg(EQOSR),
mc_make_sid_override_cfg(EQOSW),
mc_make_sid_override_cfg(UFSHCR),
mc_make_sid_override_cfg(UFSHCW),
mc_make_sid_override_cfg(NVDISPLAYR),
mc_make_sid_override_cfg(BPMPR),
mc_make_sid_override_cfg(BPMPW),
mc_make_sid_override_cfg(BPMPDMAR),
mc_make_sid_override_cfg(BPMPDMAW),
mc_make_sid_override_cfg(AONR),
mc_make_sid_override_cfg(AONW),
mc_make_sid_override_cfg(AONDMAR),
mc_make_sid_override_cfg(AONDMAW),
mc_make_sid_override_cfg(SCER),
mc_make_sid_override_cfg(SCEW),
mc_make_sid_override_cfg(SCEDMAR),
mc_make_sid_override_cfg(SCEDMAW),
mc_make_sid_override_cfg(APEDMAR),
mc_make_sid_override_cfg(APEDMAW),
mc_make_sid_override_cfg(NVDISPLAYR1),
mc_make_sid_override_cfg(VICSRD1),
mc_make_sid_override_cfg(NVDECSRD1),
mc_make_sid_override_cfg(VIFALR),
mc_make_sid_override_cfg(VIFALW),
mc_make_sid_override_cfg(DLA0RDA),
mc_make_sid_override_cfg(DLA0FALRDB),
mc_make_sid_override_cfg(DLA0WRA),
mc_make_sid_override_cfg(DLA0FALWRB),
mc_make_sid_override_cfg(DLA1RDA),
mc_make_sid_override_cfg(DLA1FALRDB),
mc_make_sid_override_cfg(DLA1WRA),
mc_make_sid_override_cfg(DLA1FALWRB),
mc_make_sid_override_cfg(PVA0RDA),
mc_make_sid_override_cfg(PVA0RDB),
mc_make_sid_override_cfg(PVA0RDC),
mc_make_sid_override_cfg(PVA0WRA),
mc_make_sid_override_cfg(PVA0WRB),
mc_make_sid_override_cfg(PVA0WRC),
mc_make_sid_override_cfg(PVA1RDA),
mc_make_sid_override_cfg(PVA1RDB),
mc_make_sid_override_cfg(PVA1RDC),
mc_make_sid_override_cfg(PVA1WRA),
mc_make_sid_override_cfg(PVA1WRB),
mc_make_sid_override_cfg(PVA1WRC),
mc_make_sid_override_cfg(RCER),
mc_make_sid_override_cfg(RCEW),
mc_make_sid_override_cfg(RCEDMAR),
mc_make_sid_override_cfg(RCEDMAW),
mc_make_sid_override_cfg(NVENC1SRD),
mc_make_sid_override_cfg(NVENC1SWR),
mc_make_sid_override_cfg(PCIE0R),
mc_make_sid_override_cfg(PCIE0W),
mc_make_sid_override_cfg(PCIE1R),
mc_make_sid_override_cfg(PCIE1W),
mc_make_sid_override_cfg(PCIE2AR),
mc_make_sid_override_cfg(PCIE2AW),
mc_make_sid_override_cfg(PCIE3R),
mc_make_sid_override_cfg(PCIE3W),
mc_make_sid_override_cfg(PCIE4R),
mc_make_sid_override_cfg(PCIE4W),
mc_make_sid_override_cfg(PCIE5R),
mc_make_sid_override_cfg(PCIE5W),
mc_make_sid_override_cfg(ISPFALW),
mc_make_sid_override_cfg(DLA0RDA1),
mc_make_sid_override_cfg(DLA1RDA1),
mc_make_sid_override_cfg(PVA0RDA1),
mc_make_sid_override_cfg(PVA0RDB1),
mc_make_sid_override_cfg(PVA1RDA1),
mc_make_sid_override_cfg(PVA1RDB1),
mc_make_sid_override_cfg(PCIE5R1),
mc_make_sid_override_cfg(NVENCSRD1),
mc_make_sid_override_cfg(NVENC1SRD1),
mc_make_sid_override_cfg(ISPRA1),
mc_make_sid_override_cfg(PCIE0R1),
mc_make_sid_override_cfg(MIU0R),
mc_make_sid_override_cfg(MIU0W),
mc_make_sid_override_cfg(MIU1R),
mc_make_sid_override_cfg(MIU1W),
mc_make_sid_override_cfg(MIU2R),
mc_make_sid_override_cfg(MIU2W),
mc_make_sid_override_cfg(MIU3R),
mc_make_sid_override_cfg(MIU3W),
mc_smmu_bypass_cfg, /* TBU settings */
_END_OF_TABLE_,
};
......@@ -415,7 +23,7 @@ static __attribute__((aligned(16))) mc_regs_t tegra194_mc_context[] = {
/*******************************************************************************
* Handler to return the pointer to the MC's context struct
******************************************************************************/
static mc_regs_t *tegra194_get_mc_system_suspend_ctx(void)
mc_regs_t *plat_memctrl_get_sys_suspend_ctx(void)
{
/* index of _END_OF_TABLE_ */
tegra194_mc_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_mc_context) - 1U;
......@@ -424,20 +32,19 @@ static mc_regs_t *tegra194_get_mc_system_suspend_ctx(void)
}
/*******************************************************************************
* Struct to hold the memory controller settings
* Handler to restore platform specific settings to the memory controller
******************************************************************************/
static tegra_mc_settings_t tegra194_mc_settings = {
.streamid_security_cfg = tegra194_streamid_sec_cfgs,
.num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs),
.get_mc_system_suspend_ctx = tegra194_get_mc_system_suspend_ctx
};
void plat_memctrl_restore(void)
{
UNUSED_FUNC_NOP(); /* do nothing */
}
/*******************************************************************************
* Handler to return the pointer to the memory controller's settings struct
* Handler to program platform specific settings to the memory controller
******************************************************************************/
tegra_mc_settings_t *tegra_get_mc_settings(void)
void plat_memctrl_setup(void)
{
return &tegra194_mc_settings;
UNUSED_FUNC_NOP(); /* do nothing */
}
/*******************************************************************************
......@@ -447,6 +54,8 @@ tegra_mc_settings_t *tegra_get_mc_settings(void)
void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
{
uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0);
uint32_t phys_base_lo = (uint32_t)phys_base & 0xFFF00000;
uint32_t phys_base_hi = (uint32_t)(phys_base >> 32);
/*
* Check TZDRAM carveout register access status. Setup TZDRAM fence
......@@ -461,8 +70,8 @@ void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
*/
INFO("Configuring TrustZone DRAM Memory Carveout\n");
tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base);
tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32));
tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base_lo);
tegra_mc_write_32(MC_SECURITY_CFG3_0, phys_base_hi);
tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20));
/*
......
plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
View file @ 859df7d5
......@@ -418,16 +418,28 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_PF_0) == TEGRA_SID_XUSB_HOST);
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_0) == TEGRA_SID_XUSB_VF0);
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_1) == TEGRA_SID_XUSB_VF1);
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_2) == TEGRA_SID_XUSB_VF2);
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_3) == TEGRA_SID_XUSB_VF3);
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_DEV_AXI_STREAMID_PF_0) == TEGRA_SID_XUSB_DEV);
}
}
......
plat/nvidia/tegra/soc/t194/plat_ras.c
View file @ 859df7d5
......@@ -9,6 +9,7 @@
#include <common/debug.h>
#include <lib/bakery_lock.h>
#include <lib/cassert.h>
#include <lib/extensions/ras.h>
#include <lib/utils_def.h>
#include <services/sdei.h>
......@@ -26,6 +27,17 @@
*/
#define ERR_FR_EN_BITS_MASK 0xFFFFFFFF00000000ULL
/*
* Number of RAS errors will be cleared per 'tegra194_ras_corrected_err_clear'
* function call.
*/
#define RAS_ERRORS_PER_CALL 8
/*
* the max possible RAS node index value.
*/
#define RAS_NODE_INDEX_MAX 0x1FFFFFFFU
/* bakery lock for platform RAS handler. */
static DEFINE_BAKERY_LOCK(ras_handler_lock);
#define ras_lock() bakery_lock_get(&ras_handler_lock)
......@@ -151,12 +163,41 @@ void tegra194_ras_enable(void)
/*
* Function to clear RAS ERR<n>STATUS for corrected RAS error.
* This function ignores any new RAS error signaled during clearing; it is not
* multi-core safe(no ras_lock is taken to reduce overhead).
*
* This function clears number of 'RAS_ERRORS_PER_CALL' RAS errors at most.
* 'cookie' - in/out cookie parameter to specify/store last visited RAS
* error record index. it is set to '0' to indicate no more RAS
* error record to clear.
*/
void tegra194_ras_corrected_err_clear(void)
void tegra194_ras_corrected_err_clear(uint64_t *cookie)
{
/*
* 'last_node' and 'last_idx' represent last visited RAS node index from
* previous function call. they are set to 0 when first smc call is made
* or all RAS error are visited by followed multipile smc calls.
*/
union prev_record {
struct record {
uint32_t last_node;
uint32_t last_idx;
} rec;
uint64_t value;
} prev;
uint64_t clear_ce_status = 0ULL;
int32_t nerrs_per_call = RAS_ERRORS_PER_CALL;
uint32_t i;
if (cookie == NULL) {
return;
}
prev.value = *cookie;
if ((prev.rec.last_node >= RAS_NODE_INDEX_MAX) ||
(prev.rec.last_idx >= RAS_NODE_INDEX_MAX)) {
return;
}
ERR_STATUS_SET_FIELD(clear_ce_status, AV, 0x1UL);
ERR_STATUS_SET_FIELD(clear_ce_status, V, 0x1UL);
......@@ -164,25 +205,56 @@ void tegra194_ras_corrected_err_clear(void)
ERR_STATUS_SET_FIELD(clear_ce_status, MV, 0x1UL);
ERR_STATUS_SET_FIELD(clear_ce_status, CE, 0x3UL);
for (uint32_t i = 0U; i < err_record_mappings.num_err_records; i++) {
for (i = prev.rec.last_node; i < err_record_mappings.num_err_records; i++) {
const struct err_record_info *info = &err_record_mappings.err_records[i];
uint32_t idx_start = info->sysreg.idx_start;
uint32_t num_idx = info->sysreg.num_idx;
for (uint32_t j = 0U; j < num_idx; j++) {
uint32_t j;
j = (i == prev.rec.last_node && prev.value != 0UL) ?
(prev.rec.last_idx + 1U) : 0U;
for (; j < num_idx; j++) {
uint64_t status;
uint32_t err_idx = idx_start + j;
if (err_idx >= RAS_NODE_INDEX_MAX) {
return;
}
write_errselr_el1(err_idx);
status = read_erxstatus_el1();
if (ERR_STATUS_GET_FIELD(status, CE) != 0U) {
write_erxstatus_el1(clear_ce_status);
}
--nerrs_per_call;
/* only clear 'nerrs_per_call' errors each time. */
if (nerrs_per_call <= 0) {
prev.rec.last_idx = j;
prev.rec.last_node = i;
/* save last visited error record index
* into cookie.
*/
*cookie = prev.value;
return;
}
}
}
/*
* finish if all ras error records are checked or provided index is out
* of range.
*/
*cookie = 0ULL;
return;
}
/* Function to probe an error from error record group. */
......@@ -330,18 +402,26 @@ CCPLEX_RAS_NODE_LIST(DEFINE_ONE_RAS_NODE)
static struct ras_aux_data per_core_ras_group[] = {
PER_CORE_RAS_GROUP_NODES
};
CASSERT(ARRAY_SIZE(per_core_ras_group) < RAS_NODE_INDEX_MAX,
assert_max_per_core_ras_group_size);
static struct ras_aux_data per_cluster_ras_group[] = {
PER_CLUSTER_RAS_GROUP_NODES
};
CASSERT(ARRAY_SIZE(per_cluster_ras_group) < RAS_NODE_INDEX_MAX,
assert_max_per_cluster_ras_group_size);
static struct ras_aux_data scf_l3_ras_group[] = {
SCF_L3_BANK_RAS_GROUP_NODES
};
CASSERT(ARRAY_SIZE(scf_l3_ras_group) < RAS_NODE_INDEX_MAX,
assert_max_scf_l3_ras_group_size);
static struct ras_aux_data ccplex_ras_group[] = {
CCPLEX_RAS_GROUP_NODES
};
CASSERT(ARRAY_SIZE(ccplex_ras_group) < RAS_NODE_INDEX_MAX,
assert_max_ccplex_ras_group_size);
/*
* We have same probe and handler for each error record group, use a macro to
......@@ -395,6 +475,9 @@ static struct err_record_info carmel_ras_records[] = {
ADD_ONE_ERR_GROUP(0x400, ccplex_ras_group),
};
CASSERT(ARRAY_SIZE(carmel_ras_records) < RAS_NODE_INDEX_MAX,
assert_max_carmel_ras_records_size);
REGISTER_ERR_RECORD_INFO(carmel_ras_records);
/* dummy RAS interrupt */
......
plat/nvidia/tegra/soc/t194/plat_secondary.c
View file @ 859df7d5
......@@ -4,11 +4,14 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <string.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <mce.h>
#include <string.h>
#include <tegra194_private.h>
#include <tegra_def.h>
#include <tegra_private.h>
......@@ -52,15 +55,21 @@ void plat_secondary_setup(void)
/* write lower 32 bits first, then the upper 11 bits */
mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low);
assert(mmio_read_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW) == addr_low);
mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high);
assert(mmio_read_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH) == addr_high);
/* save reset vector to be used during SYSTEM_SUSPEND exit */
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO,
addr_low);
assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO) == addr_low);
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI,
addr_high);
assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI) == addr_high);
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_LO,
(uint32_t)tzdram_addr);
assert(mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_LO) == (uint32_t)tzdram_addr);
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_HI,
(uint32_t)src_len_bytes);
assert(mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_HI) == (uint32_t)src_len_bytes);
}
plat/nvidia/tegra/soc/t194/plat_setup.c
View file @ 859df7d5
......@@ -23,7 +23,6 @@
#include <plat/common/platform.h>
#include <spe.h>
#include <tegra_def.h>
#include <tegra_mc_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
......@@ -31,6 +30,27 @@
/* ID for spe-console */
#define TEGRA_CONSOLE_SPE_ID 0xFE
/*******************************************************************************
* Structure to store the SCR addresses and its expected settings.
*******************************************************************************
*/
typedef struct {
uint32_t scr_addr;
uint32_t scr_val;
} scr_settings_t;
static const scr_settings_t t194_scr_settings[] = {
{ SCRATCH_RSV68_SCR, SCRATCH_RSV68_SCR_VAL },
{ SCRATCH_RSV71_SCR, SCRATCH_RSV71_SCR_VAL },
{ SCRATCH_RSV72_SCR, SCRATCH_RSV72_SCR_VAL },
{ SCRATCH_RSV75_SCR, SCRATCH_RSV75_SCR_VAL },
{ SCRATCH_RSV81_SCR, SCRATCH_RSV81_SCR_VAL },
{ SCRATCH_RSV97_SCR, SCRATCH_RSV97_SCR_VAL },
{ SCRATCH_RSV99_SCR, SCRATCH_RSV99_SCR_VAL },
{ SCRATCH_RSV109_SCR, SCRATCH_RSV109_SCR_VAL },
{ MISCREG_SCR_SCRTZWELCK, MISCREG_SCR_SCRTZWELCK_VAL }
};
/*******************************************************************************
* The Tegra power domain tree has a single system level power domain i.e. a
* single root node. The first entry in the power domain descriptor specifies
......@@ -66,8 +86,6 @@ const uint8_t *plat_get_power_domain_tree_desc(void)
static const mmap_region_t tegra_mmap[] = {
MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x4000U, /* 16KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_GPCDMA_BASE, 0x10000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */
......@@ -196,6 +214,24 @@ void plat_enable_console(int32_t id)
#endif
}
/*******************************************************************************
* Verify SCR settings
******************************************************************************/
static inline bool tegra194_is_scr_valid(void)
{
uint32_t scr_val;
bool ret = true;
for (uint8_t i = 0U; i < ARRAY_SIZE(t194_scr_settings); i++) {
scr_val = mmio_read_32((uintptr_t)t194_scr_settings[i].scr_addr);
if (scr_val != t194_scr_settings[i].scr_val) {
ERROR("Mismatch at SCR addr = 0x%x\n", t194_scr_settings[i].scr_addr);
ret = false;
}
}
return ret;
}
/*******************************************************************************
* Handler for early platform setup
******************************************************************************/
......@@ -208,6 +244,11 @@ void plat_early_platform_setup(void)
/* Verify chip id is t194 */
assert(tegra_chipid_is_t194());
/* Verify SCR settings */
if (tegra_platform_is_silicon()) {
assert(tegra194_is_scr_valid());
}
/* sanity check MCE firmware compatibility */
mce_verify_firmware_version();
......@@ -251,16 +292,28 @@ void plat_early_platform_setup(void)
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_PF_0) == TEGRA_SID_XUSB_HOST);
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_0) == TEGRA_SID_XUSB_VF0);
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_1) == TEGRA_SID_XUSB_VF1);
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_2) == TEGRA_SID_XUSB_VF2);
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_3) == TEGRA_SID_XUSB_VF3);
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_DEV_AXI_STREAMID_PF_0) == TEGRA_SID_XUSB_DEV);
}
/*
......@@ -270,14 +323,20 @@ void plat_early_platform_setup(void)
actlr_elx = read_actlr_el3();
actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3;
write_actlr_el3(actlr_elx);
/* check if the bit is actually set */
assert((read_actlr_el3() & DENVER_CPU_ENABLE_DUAL_EXEC_EL3) != 0ULL);
actlr_elx = read_actlr_el2();
actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2;
write_actlr_el2(actlr_elx);
/* check if the bit is actually set */
assert((read_actlr_el2() & DENVER_CPU_ENABLE_DUAL_EXEC_EL2) != 0ULL);
actlr_elx = read_actlr_el1();
actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1;
write_actlr_el1(actlr_elx);
/* check if the bit is actually set */
assert((read_actlr_el1() & DENVER_CPU_ENABLE_DUAL_EXEC_EL1) != 0ULL);
}
}
......@@ -344,6 +403,7 @@ void plat_late_platform_setup(void)
* enabling TZSRAM and TZDRAM
*/
mce_enable_strict_checking();
mce_verify_strict_checking();
#endif
}
......
plat/nvidia/tegra/soc/t194/plat_sip_calls.c
View file @ 859df7d5
......@@ -73,11 +73,25 @@ int32_t plat_sip_handler(uint32_t smc_fid,
#if RAS_EXTENSION
case TEGRA_SIP_CLEAR_RAS_CORRECTED_ERRORS:
/* clear all RAS error records for corrected errors at first. */
tegra194_ras_corrected_err_clear();
/* clear HSM corrected error status. */
{
/*
* clear all RAS error records for corrected errors at first.
* x1 shall be 0 for first SMC call after FHI is asserted.
* */
uint64_t local_x1 = x1;
tegra194_ras_corrected_err_clear(&local_x1);
if (local_x1 == 0ULL) {
/* clear HSM corrected error status after all corrected
* RAS errors are cleared.
*/
mce_clear_hsm_corr_status();
}
write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, local_x1);
break;
}
#endif
default:
......
plat/nvidia/tegra/soc/t194/plat_trampoline.S
View file @ 859df7d5
......@@ -58,6 +58,13 @@ m_loop1:
subs x2, x2, #1
b.ne m_loop1
/*
* Synchronization barriers to make sure that memory is flushed out
* before we start execution in SysRAM.
*/
dsb sy
isb
boot_cpu:
adr x0, __tegra194_cpu_reset_handler_data
ldr x0, [x0]
......
plat/nvidia/tegra/soc/t194/platform_t194.mk
View file @ 859df7d5
......@@ -38,7 +38,8 @@ RAS_EXTENSION := 1
PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t194 \
-I${SOC_DIR}/drivers/include
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
BL31_SOURCES += ${TEGRA_GICv2_SOURCES} \
drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/denver.S \
${TEGRA_DRIVERS}/bpmp_ipc/intf.c \
${TEGRA_DRIVERS}/bpmp_ipc/ivc.c \
......
plat/nvidia/tegra/soc/t210/platform_t210.mk
View file @ 859df7d5
......@@ -28,7 +28,8 @@ ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING := 1
PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t210 \
-I${SOC_DIR}/drivers/se
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
BL31_SOURCES += ${TEGRA_GICv2_SOURCES} \
drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
${TEGRA_DRIVERS}/bpmp/bpmp.c \
......
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