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Commit 859df7d5 authored by Madhukar Pappireddy's avatar Madhukar Pappireddy Committed by TrustedFirmware Code Review
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Merge changes from topic "tegra-downstream-08252020" into integration 

* changes:
  Tegra194: remove unused tegra_mc_defs header
  Tegra: memctrl: platform setup handler functions
  Tegra194: memctrl: remove streamid security cfg registers
  Tegra194: memctrl: remove streamid override cfg registers
  Tegra: debug prints indicating SC7 entry sequence completion
  Tegra194: add strict checking mode verification
  Tegra194: memctrl: update TZDRAM base at 1MB granularity
  Tegra194: ras: split up RAS error clear SMC call.
  Tegra: platform specific GIC sources
  Tegra194: add memory barriers during DRAM to SysRAM copy
  Tegra: sip: add VPR resize enabled check
  Tegra194: add redundancy checks for MMIO writes
  Tegra: remove unused cortex_a53.h
  Tegra194: report failure to enable dual execution
  Tegra194: verify firewall settings before resource use
parents 90b0cad4 837df485
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plat/nvidia/tegra/common/aarch64/tegra_helpers.S
View file @ 859df7d5
......@@ -4,12 +4,13 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <assert_macros.S>
#include <cpu_macros.S>
#include <cortex_a53.h>
#include <cortex_a57.h>
#include <cpu_macros.S>
#include <platform_def.h>
#include <tegra_def.h>
#include <tegra_platform.h>
......
plat/nvidia/tegra/common/tegra_bl31_setup.c
View file @ 859df7d5
......@@ -17,7 +17,6 @@
#include <bl31/bl31.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <cortex_a53.h>
#include <cortex_a57.h>
#include <denver.h>
#include <drivers/console.h>
......
plat/nvidia/tegra/common/tegra_common.mk
View file @ 859df7d5
......@@ -39,7 +39,7 @@ TEGRA_GICv3_SOURCES := drivers/arm/gic/common/gic_common.c \
BL31_SOURCES += drivers/delay_timer/delay_timer.c \
drivers/io/io_storage.c \
plat/common/aarch64/crash_console_helpers.S \
${TEGRA_GICv2_SOURCES} \
${TEGRA_LIBS}/debug/profiler.c \
${TEGRA_COMMON}/aarch64/tegra_helpers.S \
${TEGRA_LIBS}/debug/profiler.c \
${TEGRA_COMMON}/tegra_bl31_setup.c \
......
plat/nvidia/tegra/common/tegra_pm.c
View file @ 859df7d5
......@@ -117,13 +117,6 @@ static void tegra_pwr_domain_suspend(const psci_power_state_t *target_state)
{
(void)tegra_soc_pwr_domain_suspend(target_state);
/* Disable console if we are entering deep sleep. */
if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
PSTATE_ID_SOC_POWERDN) {
(void)console_flush();
console_switch_state(0);
}
/* disable GICC */
tegra_gic_cpuif_deactivate();
}
......@@ -138,6 +131,14 @@ static __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t
/* call the chip's power down handler */
(void)tegra_soc_pwr_domain_power_down_wfi(target_state);
/* Disable console if we are entering deep sleep. */
if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
PSTATE_ID_SOC_POWERDN) {
INFO("%s: complete. Entering System Suspend...\n", __func__);
(void)console_flush();
console_switch_state(0);
}
wfi();
panic();
}
......
plat/nvidia/tegra/common/tegra_sip_calls.c
View file @ 859df7d5
......@@ -52,6 +52,12 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
switch (smc_fid) {
case TEGRA_SIP_NEW_VIDEOMEM_REGION:
/* Check whether Video memory resize is enabled */
if (mmio_read_32(TEGRA_MC_BASE + MC_VIDEO_PROTECT_REG_CTRL)
!= MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED) {
ERROR("Video Memory Resize isn't enabled! \n");
SMC_RET1(handle, (uint64_t)-ENOTSUP);
}
/*
* Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
......
plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c
View file @ 859df7d5
......@@ -32,38 +32,13 @@ static uint64_t video_mem_size_mb;
*/
void tegra_memctrl_setup(void)
{
uint32_t val;
const uint32_t *mc_streamid_override_regs;
uint32_t num_streamid_override_regs;
const mc_streamid_security_cfg_t *mc_streamid_sec_cfgs;
uint32_t num_streamid_sec_cfgs;
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
uint32_t i;
INFO("Tegra Memory Controller (v2)\n");
/* Program the SMMU pagesize */
/* Initialize the System memory management unit */
tegra_smmu_init();
/* Get the settings from the platform */
assert(plat_mc_settings != NULL);
mc_streamid_override_regs = plat_mc_settings->streamid_override_cfg;
num_streamid_override_regs = plat_mc_settings->num_streamid_override_cfgs;
mc_streamid_sec_cfgs = plat_mc_settings->streamid_security_cfg;
num_streamid_sec_cfgs = plat_mc_settings->num_streamid_security_cfgs;
/* Program all the Stream ID overrides */
for (i = 0; i < num_streamid_override_regs; i++)
tegra_mc_streamid_write_32(mc_streamid_override_regs[i],
MC_STREAM_ID_MAX);
/* Program the security config settings for all Stream IDs */
for (i = 0; i < num_streamid_sec_cfgs; i++) {
val = mc_streamid_sec_cfgs[i].override_enable << 16 |
mc_streamid_sec_cfgs[i].override_client_inputs << 8 |
mc_streamid_sec_cfgs[i].override_client_ns_flag << 0;
tegra_mc_streamid_write_32(mc_streamid_sec_cfgs[i].offset, val);
}
/* allow platforms to program custom memory controller settings */
plat_memctrl_setup();
/*
* All requests at boot time, and certain requests during
......@@ -80,21 +55,6 @@ void tegra_memctrl_setup(void)
*/
tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG,
MC_SMMU_BYPASS_CONFIG_SETTINGS);
/*
* Re-configure MSS to allow ROC to deal with ordering of the
* Memory Controller traffic. This is needed as the Memory Controller
* boots with MSS having all control, but ROC provides a performance
* boost as compared to MSS.
*/
if (plat_mc_settings->reconfig_mss_clients != NULL) {
plat_mc_settings->reconfig_mss_clients();
}
/* Program overrides for MC transactions */
if (plat_mc_settings->set_txn_overrides != NULL) {
plat_mc_settings->set_txn_overrides();
}
}
/*
......@@ -102,32 +62,23 @@ void tegra_memctrl_setup(void)
*/
void tegra_memctrl_restore_settings(void)
{
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
assert(plat_mc_settings != NULL);
/*
* Re-configure MSS to allow ROC to deal with ordering of the
* Memory Controller traffic. This is needed as the Memory Controller
* resets during System Suspend with MSS having all control, but ROC
* provides a performance boost as compared to MSS.
*/
if (plat_mc_settings->reconfig_mss_clients != NULL) {
plat_mc_settings->reconfig_mss_clients();
}
/* Program overrides for MC transactions */
if (plat_mc_settings->set_txn_overrides != NULL) {
plat_mc_settings->set_txn_overrides();
}
/* restore platform's memory controller settings */
plat_memctrl_restore();
/* video memory carveout region */
if (video_mem_base != 0ULL) {
tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO,
(uint32_t)video_mem_base);
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_BASE_LO)
== (uint32_t)video_mem_base);
tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
(uint32_t)(video_mem_base >> 32));
tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size_mb);
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_BASE_HI)
== (uint32_t)(video_mem_base >> 32));
tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB,
(uint32_t)video_mem_size_mb);
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_SIZE_MB)
== (uint32_t)video_mem_size_mb);
/*
* MCE propagates the VideoMem configuration values across the
......@@ -167,7 +118,6 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
*/
void tegra_mc_save_context(uint64_t mc_ctx_addr)
{
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
uint32_t i, num_entries = 0;
mc_regs_t *mc_ctx_regs;
const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
......@@ -177,7 +127,7 @@ void tegra_mc_save_context(uint64_t mc_ctx_addr)
assert((mc_ctx_addr >= tzdram_base) && (mc_ctx_addr <= tzdram_end));
/* get MC context table */
mc_ctx_regs = plat_mc_settings->get_mc_system_suspend_ctx();
mc_ctx_regs = plat_memctrl_get_sys_suspend_ctx();
assert(mc_ctx_regs != NULL);
/*
......@@ -210,8 +160,12 @@ void tegra_mc_save_context(uint64_t mc_ctx_addr)
/* save the MC table address */
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_LO,
(uint32_t)mc_ctx_addr);
assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_LO)
== (uint32_t)mc_ctx_addr);
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_HI,
(uint32_t)(mc_ctx_addr >> 32));
assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_HI)
== (uint32_t)(mc_ctx_addr >> 32));
}
static void tegra_lock_videomem_nonoverlap(uint64_t phys_base,
......@@ -361,6 +315,14 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
(uint32_t)(phys_base >> 32));
tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20);
/* Redundancy check for Video Protect setting */
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_BASE_LO)
== (uint32_t)phys_base);
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_BASE_HI)
== (uint32_t)(phys_base >> 32));
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_SIZE_MB)
== (size_in_bytes >> 20));
/*
* MCE propagates the VideoMem configuration values across the
* CCPLEX.
......
plat/nvidia/tegra/include/drivers/memctrl_v2.h
View file @ 859df7d5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -7,58 +8,9 @@
#ifndef MEMCTRL_V2_H
#define MEMCTRL_V2_H
#include <tegra_def.h>
#ifndef __ASSEMBLER__
#include <lib/mmio.h>
#include <stdint.h>
/*******************************************************************************
* Structure to hold the transaction override settings to use to override
* client inputs
******************************************************************************/
typedef struct mc_txn_override_cfg {
uint32_t offset;
uint8_t cgid_tag;
} mc_txn_override_cfg_t;
#define mc_make_txn_override_cfg(off, val) \
{ \
.offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \
.cgid_tag = MC_TXN_OVERRIDE_ ## val \
}
/*******************************************************************************
* Structure to hold the Stream ID to use to override client inputs
******************************************************************************/
typedef struct mc_streamid_override_cfg {
uint32_t offset;
uint8_t stream_id;
} mc_streamid_override_cfg_t;
#include <arch.h>
/*******************************************************************************
* Structure to hold the Stream ID Security Configuration settings
******************************************************************************/
typedef struct mc_streamid_security_cfg {
char *name;
uint32_t offset;
int override_enable;
int override_client_inputs;
int override_client_ns_flag;
} mc_streamid_security_cfg_t;
#define OVERRIDE_DISABLE 1U
#define OVERRIDE_ENABLE 0U
#define CLIENT_FLAG_SECURE 0U
#define CLIENT_FLAG_NON_SECURE 1U
#define CLIENT_INPUTS_OVERRIDE 1U
#define CLIENT_INPUTS_NO_OVERRIDE 0U
/*******************************************************************************
* StreamID to indicate no SMMU translations (requests to be steered on the
* SMMU bypass path)
******************************************************************************/
#define MC_STREAM_ID_MAX 0x7FU
#include <tegra_def.h>
/*******************************************************************************
* Memory Controller SMMU Bypass config register
......@@ -74,33 +26,15 @@ typedef struct mc_streamid_security_cfg {
#define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
#define mc_make_sec_cfg(off, ns, ovrrd, access) \
{ \
.name = # off, \
.offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \
MC_STREAMID_OVERRIDE_CFG_ ## off), \
.override_client_ns_flag = CLIENT_FLAG_ ## ns, \
.override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \
.override_enable = OVERRIDE_ ## access \
}
#ifndef __ASSEMBLY__
#include <assert.h>
typedef struct mc_regs {
uint32_t reg;
uint32_t val;
} mc_regs_t;
#define mc_make_sid_override_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \
.val = 0x00000000U, \
}
#define mc_make_sid_security_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(MC_STREAMID_OVERRIDE_CFG_ ## name), \
.val = 0x00000000U, \
}
#define mc_smmu_bypass_cfg \
{ \
.reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \
......@@ -119,20 +53,11 @@ typedef struct mc_regs {
.val = 0xFFFFFFFFU, \
}
/*******************************************************************************
* Structure to hold Memory Controller's Configuration settings
******************************************************************************/
typedef struct tegra_mc_settings {
const uint32_t *streamid_override_cfg;
uint32_t num_streamid_override_cfgs;
const mc_streamid_security_cfg_t *streamid_security_cfg;
uint32_t num_streamid_security_cfgs;
const mc_txn_override_cfg_t *txn_override_cfg;
uint32_t num_txn_override_cfgs;
void (*reconfig_mss_clients)(void);
void (*set_txn_overrides)(void);
mc_regs_t* (*get_mc_system_suspend_ctx)(void);
} tegra_mc_settings_t;
#endif /* __ASSEMBLY__ */
#ifndef __ASSEMBLY__
#include <lib/mmio.h>
static inline uint32_t tegra_mc_read_32(uint32_t off)
{
......@@ -153,55 +78,14 @@ static inline uint32_t tegra_mc_streamid_read_32(uint32_t off)
static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val)
{
mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val);
assert(mmio_read_32(TEGRA_MC_STREAMID_BASE + off) == val);
}
#endif
#define mc_set_pcfifo_unordered_boot_so_mss(id, client) \
((uint32_t)~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)
#define mc_set_pcfifo_ordered_boot_so_mss(id, client) \
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_ORDERED
#define mc_set_tsa_passthrough(client) \
{ \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
(TSA_CONFIG_STATIC0_CSW_##client##_RESET & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
}
void plat_memctrl_setup(void);
#define mc_set_tsa_w_passthrough(client) \
{ \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
(TSA_CONFIG_STATIC0_CSW_RESET_W & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
}
#define mc_set_tsa_r_passthrough(client) \
{ \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSR_##client, \
(TSA_CONFIG_STATIC0_CSR_RESET_R & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
}
#define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \
{ \
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
MC_TXN_OVERRIDE_##normal_axi_id | \
MC_TXN_OVERRIDE_CONFIG_COH_PATH_##so_dev_override##_SO_DEV | \
MC_TXN_OVERRIDE_CONFIG_COH_PATH_##normal_override##_NORMAL | \
MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \
}
/*******************************************************************************
* Handler to read memory configuration settings
*
* Implemented by SoCs under tegra/soc/txxx
******************************************************************************/
tegra_mc_settings_t *tegra_get_mc_settings(void);
void plat_memctrl_restore(void);
mc_regs_t *plat_memctrl_get_sys_suspend_ctx(void);
/*******************************************************************************
* Handler to save MC settings before "System Suspend" to TZDRAM
......
plat/nvidia/tegra/include/t132/tegra_def.h
View file @ 859df7d5
......@@ -104,6 +104,8 @@
#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
/*******************************************************************************
* Tegra TZRAM constants
......
plat/nvidia/tegra/include/t186/tegra_def.h
View file @ 859df7d5
......@@ -163,6 +163,8 @@
#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64C)
#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
/*
* Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
......
plat/nvidia/tegra/include/t186/tegra_mc_def.h
View file @ 859df7d5
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -282,4 +282,117 @@
#define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 24)
#define MC_CLIENT_HOTRESET_STATUS1 0x974U
#ifndef __ASSEMBLY__
/*******************************************************************************
* Structure to hold the transaction override settings to use to override
* client inputs
******************************************************************************/
typedef struct mc_txn_override_cfg {
uint32_t offset;
uint8_t cgid_tag;
} mc_txn_override_cfg_t;
#define mc_make_txn_override_cfg(off, val) \
{ \
.offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \
.cgid_tag = MC_TXN_OVERRIDE_ ## val \
}
/*******************************************************************************
* Structure to hold the Stream ID to use to override client inputs
******************************************************************************/
typedef struct mc_streamid_override_cfg {
uint32_t offset;
uint8_t stream_id;
} mc_streamid_override_cfg_t;
/*******************************************************************************
* Structure to hold the Stream ID Security Configuration settings
******************************************************************************/
typedef struct mc_streamid_security_cfg {
char *name;
uint32_t offset;
uint32_t override_enable;
uint32_t override_client_inputs;
uint32_t override_client_ns_flag;
} mc_streamid_security_cfg_t;
#define OVERRIDE_DISABLE 1U
#define OVERRIDE_ENABLE 0U
#define CLIENT_FLAG_SECURE 0U
#define CLIENT_FLAG_NON_SECURE 1U
#define CLIENT_INPUTS_OVERRIDE 1U
#define CLIENT_INPUTS_NO_OVERRIDE 0U
/*******************************************************************************
* StreamID to indicate no SMMU translations (requests to be steered on the
* SMMU bypass path)
******************************************************************************/
#define MC_STREAM_ID_MAX 0x7FU
#define mc_make_sec_cfg(off, ns, ovrrd, access) \
{ \
.name = # off, \
.offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \
MC_STREAMID_OVERRIDE_CFG_ ## off), \
.override_client_ns_flag = CLIENT_FLAG_ ## ns, \
.override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \
.override_enable = OVERRIDE_ ## access \
}
#define mc_make_sid_override_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \
.val = 0x00000000U, \
}
#define mc_make_sid_security_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(MC_STREAMID_OVERRIDE_CFG_ ## name), \
.val = 0x00000000U, \
}
#define mc_set_pcfifo_unordered_boot_so_mss(id, client) \
((uint32_t)~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)
#define mc_set_pcfifo_ordered_boot_so_mss(id, client) \
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_ORDERED
#define mc_set_tsa_passthrough(client) \
do { \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
(TSA_CONFIG_STATIC0_CSW_##client##_RESET & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
} while (0)
#define mc_set_tsa_w_passthrough(client) \
do { \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
(TSA_CONFIG_STATIC0_CSW_RESET_W & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
} while (0)
#define mc_set_tsa_r_passthrough(client) \
{ \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSR_##client, \
(TSA_CONFIG_STATIC0_CSR_RESET_R & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
} while (0)
#define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \
do { \
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
MC_TXN_OVERRIDE_##normal_axi_id | \
MC_TXN_OVERRIDE_CONFIG_COH_PATH_##so_dev_override##_SO_DEV | \
MC_TXN_OVERRIDE_CONFIG_COH_PATH_##normal_override##_NORMAL | \
MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \
} while (0)
#endif /* __ASSEMBLY__ */
#endif /* TEGRA_MC_DEF_H */
plat/nvidia/tegra/include/t194/tegra_def.h
View file @ 859df7d5
......@@ -105,6 +105,8 @@
#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
/*
* Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
......@@ -294,4 +296,26 @@
#define TEGRA_SID_XUSB_VF2 U(0x5f)
#define TEGRA_SID_XUSB_VF3 U(0x60)
/*******************************************************************************
* SCR addresses and expected settings
******************************************************************************/
#define SCRATCH_RSV68_SCR U(0x0C398110)
#define SCRATCH_RSV68_SCR_VAL U(0x38000101)
#define SCRATCH_RSV71_SCR U(0x0C39811C)
#define SCRATCH_RSV71_SCR_VAL U(0x38000101)
#define SCRATCH_RSV72_SCR U(0x0C398120)
#define SCRATCH_RSV72_SCR_VAL U(0x38000101)
#define SCRATCH_RSV75_SCR U(0x0C39812C)
#define SCRATCH_RSV75_SCR_VAL U(0x3A000005)
#define SCRATCH_RSV81_SCR U(0x0C398144)
#define SCRATCH_RSV81_SCR_VAL U(0x3A000105)
#define SCRATCH_RSV97_SCR U(0x0C398184)
#define SCRATCH_RSV97_SCR_VAL U(0x38000101)
#define SCRATCH_RSV99_SCR U(0x0C39818C)
#define SCRATCH_RSV99_SCR_VAL U(0x38000101)
#define SCRATCH_RSV109_SCR U(0x0C3981B4)
#define SCRATCH_RSV109_SCR_VAL U(0x38000101)
#define MISCREG_SCR_SCRTZWELCK U(0x00109000)
#define MISCREG_SCR_SCRTZWELCK_VAL U(0x30000100)
#endif /* TEGRA_DEF_H */
plat/nvidia/tegra/include/t194/tegra_mc_def.h deleted 100644 → 0
View file @ 90b0cad4
/*
* Copyright (c) 2019-2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef TEGRA_MC_DEF_H
#define TEGRA_MC_DEF_H
/*******************************************************************************
* Memory Controller Order_id registers
******************************************************************************/
#define MC_CLIENT_ORDER_ID_9 U(0x2a24)
#define MC_CLIENT_ORDER_ID_9_RESET_VAL 0x00000000U
#define MC_CLIENT_ORDER_ID_9_XUSB_HOSTW_MASK (0x3U << 12)
#define MC_CLIENT_ORDER_ID_9_XUSB_HOSTW_ORDER_ID (3U << 12)
#define MC_CLIENT_ORDER_ID_27 U(0x2a6c)
#define MC_CLIENT_ORDER_ID_27_RESET_VAL 0x00000000U
#define MC_CLIENT_ORDER_ID_27_PCIE0W_MASK (0x3U << 4)
#define MC_CLIENT_ORDER_ID_27_PCIE0W_ORDER_ID (2U << 4)
#define MC_CLIENT_ORDER_ID_28 U(0x2a70)
#define MC_CLIENT_ORDER_ID_28_RESET_VAL 0x00000000U
#define MC_CLIENT_ORDER_ID_28_PCIE4W_MASK (0x3U << 4)
#define MC_CLIENT_ORDER_ID_28_PCIE4W_ORDER_ID (3U << 4)
#define MC_CLIENT_ORDER_ID_28_PCIE5W_MASK (0x3U << 12)
#define MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID (1U << 12)
#define mc_client_order_id(val, id, client) \
((val & ~MC_CLIENT_ORDER_ID_##id##_##client##_MASK) | \
MC_CLIENT_ORDER_ID_##id##_##client##_ORDER_ID)
/*******************************************************************************
* Memory Controller's VC ID configuration registers
******************************************************************************/
#define VC_NISO 0U
#define VC_SISO 1U
#define VC_ISO 2U
#define MC_HUB_PC_VC_ID_0 U(0x2a78)
#define MC_HUB_PC_VC_ID_0_RESET_VAL 0x00020100U
#define MC_HUB_PC_VC_ID_0_APB_VC_ID_MASK (0x3U << 8)
#define MC_HUB_PC_VC_ID_0_APB_VC_ID (VC_NISO << 8)
#define MC_HUB_PC_VC_ID_2 U(0x2a80)
#define MC_HUB_PC_VC_ID_2_RESET_VAL 0x10001000U
#define MC_HUB_PC_VC_ID_2_SD_VC_ID_MASK (0x3U << 28)
#define MC_HUB_PC_VC_ID_2_SD_VC_ID (VC_NISO << 28)
#define MC_HUB_PC_VC_ID_4 U(0x2a88)
#define MC_HUB_PC_VC_ID_4_RESET_VAL 0x10020011U
#define MC_HUB_PC_VC_ID_4_NIC_VC_ID_MASK (0x3U << 28)
#define MC_HUB_PC_VC_ID_4_NIC_VC_ID (VC_NISO << 28)
#define MC_HUB_PC_VC_ID_12 U(0x2aa8)
#define MC_HUB_PC_VC_ID_12_RESET_VAL 0x11001011U
#define MC_HUB_PC_VC_ID_12_UFSHCPC2_VC_ID_MASK (0x3U << 12)
#define MC_HUB_PC_VC_ID_12_UFSHCPC2_VC_ID (VC_NISO << 12)
#define mc_hub_vc_id(val, id, client) \
((val & ~MC_HUB_PC_VC_ID_##id##_##client##_VC_ID_MASK) | \
MC_HUB_PC_VC_ID_##id##_##client##_VC_ID)
/*******************************************************************************
* Memory Controller's PCFIFO client configuration registers
******************************************************************************/
#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0U
#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4U
#define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20200000U
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0U << 17)
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1U << 17)
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0U << 21)
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1U << 21)
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0U << 29)
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_ORDERED (1U << 29)
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1U << 29)
#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8U
#define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x00002800U
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0U << 11)
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1U << 11)
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0U << 13)
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_ORDERED (1U << 13)
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1U << 13)
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_TSECSWR_UNORDERED (0U << 21)
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_TSECSWR_MASK (1U << 21)
#define MC_PCFIFO_CLIENT_CONFIG3 0xddcU
#define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0x08000080U
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWA_UNORDERED (0U << 4)
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWA_MASK (1U << 4)
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCW_UNORDERED (0U << 6)
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCW_MASK (1U << 6)
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0U << 7)
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1U << 7)
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_VICSWR_UNORDERED (0U << 13)
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_VICSWR_MASK (1U << 13)
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_APEW_UNORDERED (0U << 27)
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_APEW_MASK (1U << 27)
#define MC_PCFIFO_CLIENT_CONFIG4 0xde0U
#define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0x5552a022U
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0U << 1)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1U << 1)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0U << 5)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1U << 5)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_UNORDERED (0U << 7)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_MASK (1U << 7)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0U << 13)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1U << 13)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0U << 15)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1U << 15)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0U << 17)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1U << 17)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPW_UNORDERED (0U << 20)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPW_MASK (1U << 20)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0U << 22)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1U << 22)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONW_UNORDERED (0U << 24)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONW_MASK (1U << 24)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0U << 26)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1U << 26)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEW_UNORDERED (0U << 28)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEW_MASK (1U << 28)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0U << 30)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1U << 30)
#define MC_PCFIFO_CLIENT_CONFIG5 0xbf4U
#define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0x20000001U
#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0U << 0)
#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1U << 0)
#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_VIFALW_UNORDERED (0U << 30)
#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_VIFALW_MASK (1U << 30)
#define MC_PCFIFO_CLIENT_CONFIG6 0xb90U
#define MC_PCFIFO_CLIENT_CONFIG6_RESET_VAL 0xaa280000U
#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEW_UNORDERED (0U << 19)
#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEW_MASK (1U << 19)
#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEDMAW_UNORDERED (0U << 21)
#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEDMAW_MASK (1U << 21)
#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE0W_UNORDERED (0U << 25)
#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE0W_MASK (1U << 25)
#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE1W_ORDERED (1U << 27)
#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE1W_MASK (1U << 27)
#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE2W_ORDERED (1U << 29)
#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE2W_MASK (1U << 29)
#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE3W_ORDERED (1U << 31)
#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE3W_MASK (1U << 31)
#define MC_PCFIFO_CLIENT_CONFIG7 0xaccU
#define MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL 0x0000000aU
#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE4W_UNORDERED (0U << 1)
#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE4W_MASK (1U << 1)
#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE5W_UNORDERED (0U << 3)
#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE5W_MASK (1U << 3)
/*******************************************************************************
* StreamID to indicate no SMMU translations (requests to be steered on the
* SMMU bypass path)
******************************************************************************/
#define MC_STREAM_ID_MAX 0x7FU
/*******************************************************************************
* Stream ID Override Config registers
******************************************************************************/
#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660U
#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0xe0U
#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3f8U
#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758U
#define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640U
#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5f0U
#define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498U
#define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4f8U
#define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460U
#define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2a0U
#define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5f8U
#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788U
#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1c8U
#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780U
#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250U
#define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540U
#define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530U
#define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6d8U
#define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678U
#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258U
#define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418U
#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338U
#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1e8U
#define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600U
#define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6f0U
#define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588U
#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4e8U
#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0xb0U
#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320U
#define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570U
#define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500U
#define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6e8U
#define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408U
#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770U
#define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468U
#define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618U
#define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4d0U
#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438U
#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238U
#define MC_STREAMID_OVERRIDE_CFG_HDAR 0xa8U
#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300U
#define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428U
#define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6a8U
#define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2a8U
#define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420U
#define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310U
#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3f0U
#define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4c8U
#define MC_STREAMID_OVERRIDE_CFG_SCER 0x4d8U
#define MC_STREAMID_OVERRIDE_CFG_MIU5W 0x7e8U
#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6b0U
#define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700U
#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230U
#define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6c8U
#define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778U
#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610U
#define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368U
#define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400U
#define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330U
#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318U
#define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720U
#define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478U
#define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6a0U
#define MC_STREAMID_OVERRIDE_CFG_RCER 0x690U
#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3c8U
#define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480U
#define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708U
#define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360U
#define MC_STREAMID_OVERRIDE_CFG_APER 0x3d0U
#define MC_STREAMID_OVERRIDE_CFG_MIU7R 0x8U
#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7c8U
#define MC_STREAMID_OVERRIDE_CFG_MIU7W 0x10U
#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768U
#define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688U
#define MC_STREAMID_OVERRIDE_CFG_AONW 0x4c0U
#define MC_STREAMID_OVERRIDE_CFG_MIU4W 0x598U
#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1a8U
#define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4a0U
#define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620U
#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748U
#define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548U
#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508U
#define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510U
#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4b0U
#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7d8U
#define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658U
#define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710U
#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260U
#define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488U
#define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680U
#define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650U
#define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628U
#define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6b8U
#define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6c0U
#define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6f8U
#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630U
#define MC_STREAMID_OVERRIDE_CFG_MIU6W 0x7f8U
#define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6d0U
#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7d0U
#define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608U
#define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670U
#define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538U
#define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578U
#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138U
#define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410U
#define MC_STREAMID_OVERRIDE_CFG_AONR 0x4b8U
#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4a8U
#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638U
#define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5e8U
#define MC_STREAMID_OVERRIDE_CFG_MIU6R 0x7f0U
#define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470U
#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3c0U
#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430U
#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518U
#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760U
#define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798U
#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4f0U
#define MC_STREAMID_OVERRIDE_CFG_APEW 0x3d8U
#define MC_STREAMID_OVERRIDE_CFG_MIU5R 0x7e0U
#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750U
#define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648U
#define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228U
#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x0U
#define MC_STREAMID_OVERRIDE_CFG_MIU4R 0x590U
#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220U
#define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5e0U
#define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6e0U
#define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698U
#define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790U
#define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4e0U
#define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580U
#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268U
#define MC_STREAMID_OVERRIDE_CFG_SATAR 0xf8U
#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490U
#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668U
#define MC_STREAMID_OVERRIDE_CFG_VIW 0x390U
#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158U
#define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718U
/*******************************************************************************
* Macro to calculate Security cfg register addr from StreamID Override register
******************************************************************************/
#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + (uint32_t)sizeof(uint32_t))
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV (0U << 4)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV (1U << 4)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV (2U << 4)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV (3U << 4)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL (0U << 8)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL (1U << 8)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL (2U << 8)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL (3U << 8)
#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO (0U << 12)
#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID (1U << 12)
/*******************************************************************************
* Memory Controller transaction override config registers
******************************************************************************/
#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8U
#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624U
#define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16dcU
#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644U
#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000U
#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478U
#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8U
#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162cU
#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460U
#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654U
#define MC_TXN_OVERRIDE_CONFIG_MIU6R 0x17f4U
#define MC_TXN_OVERRIDE_CONFIG_MIU5R 0x17e4U
#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784U
#define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16c4U
#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470U
#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0U
#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178cU
#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774U
#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16bcU
#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510U
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8U
#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390U
#define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714U
#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468U
#define MC_TXN_OVERRIDE_CONFIG_MIU6W 0x17fcU
#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480U
#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179cU
#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764U
#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8U
#define MC_TXN_OVERRIDE_CONFIG_MIU7R 0x1008U
#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8U
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258U
#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15f4U
#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438U
#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17dcU
#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176cU
#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166cU
#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0U
#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0U
#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420U
#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16ecU
#define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16d4U
#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674U
#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164cU
#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430U
#define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548U
#define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16ccU
#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17ccU
#define MC_TXN_OVERRIDE_CONFIG_MIU7W 0x1010U
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518U
#define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580U
#define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158cU
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250U
#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400U
#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8U
#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138U
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320U
#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8U
#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8U
#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634U
#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8U
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338U
#define MC_TXN_OVERRIDE_CONFIG_ISPFALR 0x1228U
#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175cU
#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16b4U
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508U
#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664U
#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174cU
#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238U
#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8U
#define MC_TXN_OVERRIDE_CONFIG_AXIAPR 0x1410U
#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16e4U
#define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724U
#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310U
#define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578U
#define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694U
#define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170cU
#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0U
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490U
#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220U
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8U
#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360U
#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17d4U
#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614U
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0U
#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330U
#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161cU
#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8U
#define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169cU
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318U
#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604U
#define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15e4U
#define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16f4U
#define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540U
#define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171cU
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260U
#define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538U
#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160cU
#define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15ecU
#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15fcU
#define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16fcU
#define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530U
#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165cU
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8U
#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500U
#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0U
#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408U
#define MC_TXN_OVERRIDE_CONFIG_AXIAPW 0x1418U
#define MC_TXN_OVERRIDE_CONFIG_MIU4R 0x1594U
#define MC_TXN_OVERRIDE_CONFIG_MIU4W 0x159cU
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0U
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0U
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0U
#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0U
#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754U
#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684U
#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230U
#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168cU
#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16a4U
#define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794U
#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8U
#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16acU
#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488U
#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428U
#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8U
#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368U
#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158U
#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177cU
#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163cU
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300U
#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167cU
#define MC_TXN_OVERRIDE_CONFIG_MIU5W 0x17ecU
#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498U
#define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570U
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268U
#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0U
#define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704U
#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0U
#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1U << 0)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2U << 4)
#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1U << 12)
/*******************************************************************************
* Non-SO_DEV transactions override values for CGID_TAG bitfield for the
* MC_TXN_OVERRIDE_CONFIG_{module} registers
******************************************************************************/
#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0U
#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1U
#define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2U
#define MC_TXN_OVERRIDE_CGID_TAG_ADR 3U
#define MC_TXN_OVERRIDE_CGID_TAG_MASK 3ULL
/*******************************************************************************
* Memory Controller Reset Control registers
******************************************************************************/
#define MC_CLIENT_HOTRESET_CTRL0 0x200U
#define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0U
#define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1U << 0)
#define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1U << 6)
#define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1U << 7)
#define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1U << 8)
#define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1U << 9)
#define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1U << 11)
#define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1U << 15)
#define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1U << 17)
#define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1U << 18)
#define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1U << 19)
#define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1U << 20)
#define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1U << 22)
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1U << 29)
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1U << 30)
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1U << 31)
#define MC_CLIENT_HOTRESET_STATUS0 0x204U
#define MC_CLIENT_HOTRESET_CTRL1 0x970U
#define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0U
#define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1U << 0)
#define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1U << 2)
#define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1U << 5)
#define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1U << 6)
#define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1U << 7)
#define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1U << 8)
#define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1U << 12)
#define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1U << 13)
#define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1U << 17)
#define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1U << 18)
#define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1U << 19)
#define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1U << 20)
#define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1U << 21)
#define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1U << 22)
#define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 23)
#define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1U << 26)
#define MC_CLIENT_HOTRESET_CTRL1_RCE_FLUSH_ENB (1U << 31)
#define MC_CLIENT_HOTRESET_STATUS1 0x974U
#define MC_CLIENT_HOTRESET_CTRL2 0x97cU
#define MC_CLIENT_HOTRESET_CTRL2_RESET_VAL 0U
#define MC_CLIENT_HOTRESET_CTRL2_RCEDMA_FLUSH_ENB (1U << 0)
#define MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB (1U << 2)
#define MC_CLIENT_HOTRESET_CTRL2_PCIE5A_FLUSH_ENB (1U << 4)
#define MC_CLIENT_HOTRESET_CTRL2_AONDMA_FLUSH_ENB (1U << 9)
#define MC_CLIENT_HOTRESET_CTRL2_BPMPDMA_FLUSH_ENB (1U << 10)
#define MC_CLIENT_HOTRESET_CTRL2_SCEDMA_FLUSH_ENB (1U << 11)
#define MC_CLIENT_HOTRESET_CTRL2_APEDMA_FLUSH_ENB (1U << 14)
#define MC_CLIENT_HOTRESET_CTRL2_PCIE3A_FLUSH_ENB (1U << 16)
#define MC_CLIENT_HOTRESET_CTRL2_PCIE3_FLUSH_ENB (1U << 17)
#define MC_CLIENT_HOTRESET_CTRL2_PCIE0A_FLUSH_ENB (1U << 22)
#define MC_CLIENT_HOTRESET_CTRL2_PCIE0A2_FLUSH_ENB (1U << 23)
#define MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB (1U << 25)
#define MC_CLIENT_HOTRESET_STATUS2 0x1898U
#define MC_COALESCE_CTRL 0x2930U
#define MC_COALESCE_CTRL_COALESCER_ENABLE (1U << 31)
#define MC_COALESCE_CONFIG_6_0 0x294cU
#define MC_COALESCE_CONFIG_6_0_PVA0RDC_COALESCER_ENABLED (1U << 8)
#define MC_COALESCE_CONFIG_6_0_PVA1RDC_COALESCER_ENABLED (1U << 14)
/*******************************************************************************
* Tegra TSA Controller constants
******************************************************************************/
#define TEGRA_TSA_BASE U(0x02000000)
#define TSA_CONFIG_STATIC0_CSR_RESET_R 0x20000000U
#define TSA_CONFIG_STATIC0_CSW_RESET_W 0x20001000U
#define TSA_CONFIG_STATIC0_CSW_RESET_SO_DEV 0x20001000U
#define TSA_CONFIG_STATIC0_CSW_PCIE1W 0x1004U
#define TSA_CONFIG_STATIC0_CSW_PCIE2AW 0x1008U
#define TSA_CONFIG_STATIC0_CSW_PCIE3W 0x100cU
#define TSA_CONFIG_STATIC0_CSW_PCIE4W 0x1028U
#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x2004U
#define TSA_CONFIG_STATIC0_CSR_SATAR 0x2010U
#define TSA_CONFIG_STATIC0_CSW_SATAW 0x2014U
#define TSA_CONFIG_STATIC0_CSW_PCIE0W 0x2020U
#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x202cU
#define TSA_CONFIG_STATIC0_CSW_NVENC1SWR 0x3004U
#define TSA_CONFIG_STATIC0_CSW_NVENCSWR 0x3010U
#define TSA_CONFIG_STATIC0_CSW_NVDEC1SWR 0x4004U
#define TSA_CONFIG_STATIC0_CSR_ISPFALR 0x4010U
#define TSA_CONFIG_STATIC0_CSW_ISPWA 0x4014U
#define TSA_CONFIG_STATIC0_CSW_ISPWB 0x4018U
#define TSA_CONFIG_STATIC0_CSW_ISPFALW 0x401cU
#define TSA_CONFIG_STATIC0_CSW_NVDECSWR 0x5004U
#define TSA_CONFIG_STATIC0_CSR_EQOSR 0x5010U
#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x5014U
#define TSA_CONFIG_STATIC0_CSR_SDMMCRAB 0x5020U
#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5024U
#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6004U
#define TSA_CONFIG_STATIC0_CSR_SDMMCR 0x6010U
#define TSA_CONFIG_STATIC0_CSR_SDMMCRA 0x6014U
#define TSA_CONFIG_STATIC0_CSW_SDMMCW 0x6018U
#define TSA_CONFIG_STATIC0_CSW_SDMMCWA 0x601cU
#define TSA_CONFIG_STATIC0_CSR_RCER 0x6030U
#define TSA_CONFIG_STATIC0_CSR_RCEDMAR 0x6034U
#define TSA_CONFIG_STATIC0_CSW_RCEW 0x6038U
#define TSA_CONFIG_STATIC0_CSW_RCEDMAW 0x603cU
#define TSA_CONFIG_STATIC0_CSR_SCER 0x6050U
#define TSA_CONFIG_STATIC0_CSR_SCEDMAR 0x6054U
#define TSA_CONFIG_STATIC0_CSW_SCEW 0x6058U
#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x605cU
#define TSA_CONFIG_STATIC0_CSR_AXIAPR 0x7004U
#define TSA_CONFIG_STATIC0_CSR_ETRR 0x7008U
#define TSA_CONFIG_STATIC0_CSR_HOST1XDMAR 0x700cU
#define TSA_CONFIG_STATIC0_CSW_AXIAPW 0x7010U
#define TSA_CONFIG_STATIC0_CSW_ETRW 0x7014U
#define TSA_CONFIG_STATIC0_CSR_NVJPGSRD 0x8004U
#define TSA_CONFIG_STATIC0_CSW_NVJPGSWR 0x8008U
#define TSA_CONFIG_STATIC0_CSR_AXISR 0x8014U
#define TSA_CONFIG_STATIC0_CSW_AXISW 0x8018U
#define TSA_CONFIG_STATIC0_CSR_BPMPR 0x9004U
#define TSA_CONFIG_STATIC0_CSR_BPMPDMAR 0x9008U
#define TSA_CONFIG_STATIC0_CSW_BPMPW 0x900cU
#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9010U
#define TSA_CONFIG_STATIC0_CSR_SESRD 0x9024U
#define TSA_CONFIG_STATIC0_CSR_TSECSRD 0x9028U
#define TSA_CONFIG_STATIC0_CSR_TSECSRDB 0x902cU
#define TSA_CONFIG_STATIC0_CSW_SESWR 0x9030U
#define TSA_CONFIG_STATIC0_CSW_TSECSWR 0x9034U
#define TSA_CONFIG_STATIC0_CSW_TSECSWRB 0x9038U
#define TSA_CONFIG_STATIC0_CSW_PCIE5W 0xb004U
#define TSA_CONFIG_STATIC0_CSW_VICSWR 0xc004U
#define TSA_CONFIG_STATIC0_CSR_APER 0xd004U
#define TSA_CONFIG_STATIC0_CSR_APEDMAR 0xd008U
#define TSA_CONFIG_STATIC0_CSW_APEW 0xd00cU
#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xd010U
#define TSA_CONFIG_STATIC0_CSR_HDAR 0xf004U
#define TSA_CONFIG_STATIC0_CSW_HDAW 0xf008U
#define TSA_CONFIG_STATIC0_CSR_NVDISPLAYR 0xf014U
#define TSA_CONFIG_STATIC0_CSR_VIFALR 0x10004U
#define TSA_CONFIG_STATIC0_CSW_VIW 0x10008U
#define TSA_CONFIG_STATIC0_CSW_VIFALW 0x1000cU
#define TSA_CONFIG_STATIC0_CSR_AONR 0x12004U
#define TSA_CONFIG_STATIC0_CSR_AONDMAR 0x12008U
#define TSA_CONFIG_STATIC0_CSW_AONW 0x1200cU
#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0x12010U
#define TSA_CONFIG_STATIC0_CSR_PCIE1R 0x14004U
#define TSA_CONFIG_STATIC0_CSR_PCIE2AR 0x14008U
#define TSA_CONFIG_STATIC0_CSR_PCIE3R 0x1400cU
#define TSA_CONFIG_STATIC0_CSR_PCIE4R 0x14028U
#define TSA_CONFIG_STATIC0_CSR_XUSB_DEVR 0x15004U
#define TSA_CONFIG_STATIC0_CSR_XUSB_HOSTR 0x15010U
#define TSA_CONFIG_STATIC0_CSR_UFSHCR 0x16004U
#define TSA_CONFIG_STATIC0_CSW_DLA1WRA 0x18004U
#define TSA_CONFIG_STATIC0_CSR_DLA1FALRDB 0x18010U
#define TSA_CONFIG_STATIC0_CSW_DLA1FALWRB 0x18014U
#define TSA_CONFIG_STATIC0_CSW_DLA0WRA 0x19004U
#define TSA_CONFIG_STATIC0_CSR_DLA0FALRDB 0x19010U
#define TSA_CONFIG_STATIC0_CSW_DLA0FALWRB 0x19014U
#define TSA_CONFIG_STATIC0_CSR_PVA1RDC 0x1a004U
#define TSA_CONFIG_STATIC0_CSW_PVA1WRC 0x1a008U
#define TSA_CONFIG_STATIC0_CSW_PVA1WRA 0x1a014U
#define TSA_CONFIG_STATIC0_CSW_PVA1WRB 0x1a020U
#define TSA_CONFIG_STATIC0_CSW_PVA0WRB 0x1b004U
#define TSA_CONFIG_STATIC0_CSR_PVA0RDC 0x1b010U
#define TSA_CONFIG_STATIC0_CSW_PVA0WRC 0x1b014U
#define TSA_CONFIG_STATIC0_CSW_PVA0WRA 0x1b020U
#define TSA_CONFIG_STATIC0_CSR_NVENC1SRD 0x1d004U
#define TSA_CONFIG_STATIC0_CSR_NVENCSRD 0x1d010U
#define TSA_CONFIG_STATIC0_CSR_NVDEC1SRD 0x1e004U
#define TSA_CONFIG_STATIC0_CSR_ISPRA 0x1e010U
#define TSA_CONFIG_STATIC0_CSR_NVDECSRD 0x1f004U
#define TSA_CONFIG_STATIC0_CSR_PCIE0R 0x21004U
#define TSA_CONFIG_STATIC0_CSR_PCIE5R 0x23004U
#define TSA_CONFIG_STATIC0_CSR_VICSRD 0x24004U
#define TSA_CONFIG_STATIC0_CSR_DLA1RDA 0x26004U
#define TSA_CONFIG_STATIC0_CSR_DLA0RDA 0x27004U
#define TSA_CONFIG_STATIC0_CSR_PVA1RDA 0x28004U
#define TSA_CONFIG_STATIC0_CSR_PVA1RDB 0x28010U
#define TSA_CONFIG_STATIC0_CSR_PVA0RDB 0x29004U
#define TSA_CONFIG_STATIC0_CSR_PVA0RDA 0x29010U
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11)
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11)
#define TSA_CONFIG_CSW_SO_DEV_HUBID_MASK (ULL(0x3) << 15)
#define TSA_CONFIG_CSW_SO_DEV_HUB2 (ULL(2) << 15)
#define REORDER_DEPTH_LIMIT 16
#define TSA_CONFIG_CSW_REORDER_DEPTH_LIMIT_MASK (ULL(0x7FF) << 21)
#define reorder_depth_limit(limit) (ULL(limit) << 21)
#define tsa_read_32(client) \
mmio_read_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client)
#define mc_set_tsa_hub2(val, client) \
{ \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
((val & ~TSA_CONFIG_CSW_SO_DEV_HUBID_MASK) | \
TSA_CONFIG_CSW_SO_DEV_HUB2)); \
}
#define mc_set_tsa_depth_limit(limit, client) \
{ \
uint32_t val = mmio_read_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client); \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
((val & ~TSA_CONFIG_CSW_REORDER_DEPTH_LIMIT_MASK) | \
reorder_depth_limit(limit))); \
}
#endif /* TEGRA_MC_DEF_H */
plat/nvidia/tegra/include/t210/tegra_def.h
View file @ 859df7d5
......@@ -240,6 +240,8 @@
#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
/* SMMU configuration registers*/
#define MC_SMMU_PPCS_ASID_0 0x270U
......
plat/nvidia/tegra/include/tegra_private.h
View file @ 859df7d5
......@@ -68,6 +68,11 @@ struct tegra_bl31_params {
image_info_t *bl33_image_info;
};
/*******************************************************************************
* To suppress Coverity MISRA C-2012 Rule 2.2 violations
*******************************************************************************/
#define UNUSED_FUNC_NOP() asm("nop")
/* Declarations for plat_psci_handlers.c */
int32_t tegra_soc_validate_power_state(uint32_t power_state,
psci_power_state_t *req_state);
......@@ -146,7 +151,7 @@ int plat_sip_handler(uint32_t smc_fid,
#if RAS_EXTENSION
void tegra194_ras_enable(void);
void tegra194_ras_corrected_err_clear(void);
void tegra194_ras_corrected_err_clear(uint64_t *cookie);
#endif
#endif /* TEGRA_PRIVATE_H */
plat/nvidia/tegra/soc/t132/platform_t132.mk
View file @ 859df7d5
......@@ -23,11 +23,12 @@ $(eval $(call add_define,MAX_MMAP_REGIONS))
# platform files
PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t132
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
BL31_SOURCES += ${TEGRA_GICv2_SOURCES} \
drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/denver.S \
${TEGRA_DRIVERS}/flowctrl/flowctrl.c \
${TEGRA_DRIVERS}/memctrl/memctrl_v1.c \
${TEGRA_DRIVERS}/pmc/pmc.c \
${TEGRA_DRIVERS}/pmc/pmc.c \
${SOC_DIR}/plat_psci_handlers.c \
${SOC_DIR}/plat_sip_calls.c \
${SOC_DIR}/plat_setup.c \
......
plat/nvidia/tegra/soc/t186/plat_memctrl.c
View file @ 859df7d5
......@@ -402,16 +402,8 @@ static void tegra186_memctrl_reconfig_mss_clients(void)
static void tegra186_memctrl_set_overrides(void)
{
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
const mc_txn_override_cfg_t *mc_txn_override_cfgs;
uint32_t num_txn_override_cfgs;
uint32_t i, val;
/* Get the settings from the platform */
assert(plat_mc_settings != NULL);
mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg;
num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs;
/*
* Set the MC_TXN_OVERRIDE registers for write clients.
*/
......@@ -443,11 +435,11 @@ static void tegra186_memctrl_set_overrides(void)
/*
* Settings for Tegra186 silicon rev. A02 and onwards.
*/
for (i = 0; i < num_txn_override_cfgs; i++) {
val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset);
for (i = 0; i < ARRAY_SIZE(tegra186_txn_override_cfgs); i++) {
val = tegra_mc_read_32(tegra186_txn_override_cfgs[i].offset);
val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(mc_txn_override_cfgs[i].offset,
val | mc_txn_override_cfgs[i].cgid_tag);
tegra_mc_write_32(tegra186_txn_override_cfgs[i].offset,
val | tegra186_txn_override_cfgs[i].cgid_tag);
}
}
}
......@@ -609,7 +601,7 @@ static __attribute__((aligned(16))) mc_regs_t tegra186_mc_context[] = {
/*******************************************************************************
* Handler to return the pointer to the MC's context struct
******************************************************************************/
static mc_regs_t *tegra186_get_mc_system_suspend_ctx(void)
mc_regs_t *plat_memctrl_get_sys_suspend_ctx(void)
{
/* index of _END_OF_TABLE_ */
tegra186_mc_context[0].val = (uint32_t)(ARRAY_SIZE(tegra186_mc_context)) - 1U;
......@@ -617,27 +609,52 @@ static mc_regs_t *tegra186_get_mc_system_suspend_ctx(void)
return tegra186_mc_context;
}
/*******************************************************************************
* Struct to hold the memory controller settings
******************************************************************************/
static tegra_mc_settings_t tegra186_mc_settings = {
.streamid_override_cfg = tegra186_streamid_override_regs,
.num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_streamid_override_regs),
.streamid_security_cfg = tegra186_streamid_sec_cfgs,
.num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra186_streamid_sec_cfgs),
.txn_override_cfg = tegra186_txn_override_cfgs,
.num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_txn_override_cfgs),
.reconfig_mss_clients = tegra186_memctrl_reconfig_mss_clients,
.set_txn_overrides = tegra186_memctrl_set_overrides,
.get_mc_system_suspend_ctx = tegra186_get_mc_system_suspend_ctx,
};
void plat_memctrl_setup(void)
{
uint32_t val;
unsigned int i;
/* Program all the Stream ID overrides */
for (i = 0U; i < ARRAY_SIZE(tegra186_streamid_override_regs); i++) {
tegra_mc_streamid_write_32(tegra186_streamid_override_regs[i],
MC_STREAM_ID_MAX);
}
/* Program the security config settings for all Stream IDs */
for (i = 0U; i < ARRAY_SIZE(tegra186_streamid_sec_cfgs); i++) {
val = (tegra186_streamid_sec_cfgs[i].override_enable << 16) |
(tegra186_streamid_sec_cfgs[i].override_client_inputs << 8) |
(tegra186_streamid_sec_cfgs[i].override_client_ns_flag << 0);
tegra_mc_streamid_write_32(tegra186_streamid_sec_cfgs[i].offset, val);
}
/*
* Re-configure MSS to allow ROC to deal with ordering of the
* Memory Controller traffic. This is needed as the Memory Controller
* boots with MSS having all control, but ROC provides a performance
* boost as compared to MSS.
*/
tegra186_memctrl_reconfig_mss_clients();
/* Program overrides for MC transactions */
tegra186_memctrl_set_overrides();
}
/*******************************************************************************
* Handler to return the pointer to the memory controller's settings struct
* Handler to restore platform specific settings to the memory controller
******************************************************************************/
tegra_mc_settings_t *tegra_get_mc_settings(void)
void plat_memctrl_restore(void)
{
return &tegra186_mc_settings;
/*
* Re-configure MSS to allow ROC to deal with ordering of the
* Memory Controller traffic. This is needed as the Memory Controller
* boots with MSS having all control, but ROC provides a performance
* boost as compared to MSS.
*/
tegra186_memctrl_reconfig_mss_clients();
/* Program overrides for MC transactions */
tegra186_memctrl_set_overrides();
}
/*******************************************************************************
......
plat/nvidia/tegra/soc/t186/platform_t186.mk
View file @ 859df7d5
......@@ -40,7 +40,8 @@ $(eval $(call add_define,MAX_MMAP_REGIONS))
PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t186 \
-I${SOC_DIR}/drivers/include
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
BL31_SOURCES += ${TEGRA_GICv2_SOURCES} \
drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/denver.S \
lib/cpus/aarch64/cortex_a57.S \
${TEGRA_DRIVERS}/bpmp_ipc/intf.c \
......
plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
View file @ 859df7d5
......@@ -56,6 +56,7 @@ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
int32_t nvg_roc_clean_cache_trbits(void);
void nvg_enable_strict_checking_mode(void);
void nvg_verify_strict_checking_mode(void);
void nvg_system_shutdown(void);
void nvg_system_reboot(void);
void nvg_clear_hsm_corr_status(void);
......@@ -70,6 +71,7 @@ uint64_t nvg_cache_inval_all(void);
/* MCE helper functions */
void mce_enable_strict_checking(void);
void mce_verify_strict_checking(void);
void mce_system_shutdown(void);
void mce_system_reboot(void);
void mce_clear_hsm_corr_status(void);
......
plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
View file @ 859df7d5
......@@ -217,6 +217,15 @@ void mce_enable_strict_checking(void)
nvg_enable_strict_checking_mode();
}
}
void mce_verify_strict_checking(void)
{
bool is_silicon = tegra_platform_is_silicon();
bool is_fpga = tegra_platform_is_fpga();
if (is_silicon || is_fpga) {
nvg_verify_strict_checking_mode();
}
}
#endif
/*******************************************************************************
......
plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
View file @ 859df7d5
......@@ -4,12 +4,15 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <errno.h>
#include <arch.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <denver.h>
#include <errno.h>
#include <lib/mmio.h>
#include <mce_private.h>
#include <platform_def.h>
#include <t194_nvg.h>
......@@ -211,6 +214,15 @@ void nvg_enable_strict_checking_mode(void)
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params);
}
void nvg_verify_strict_checking_mode(void)
{
uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET |
STRICT_CHECKING_LOCKED_SET);
nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_SECURITY_CONFIG);
assert(params == (uint64_t)nvg_get_result());
}
#endif
/*
......
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