Commit 859df7d5 authored by Madhukar Pappireddy's avatar Madhukar Pappireddy Committed by TrustedFirmware Code Review
Browse files

Merge changes from topic "tegra-downstream-08252020" into integration

* changes:
  Tegra194: remove unused tegra_mc_defs header
  Tegra: memctrl: platform setup handler functions
  Tegra194: memctrl: remove streamid security cfg registers
  Tegra194: memctrl: remove streamid override cfg registers
  Tegra: debug prints indicating SC7 entry sequence completion
  Tegra194: add strict checking mode verification
  Tegra194: memctrl: update TZDRAM base at 1MB granularity
  Tegra194: ras: split up RAS error clear SMC call.
  Tegra: platform specific GIC sources
  Tegra194: add memory barriers during DRAM to SysRAM copy
  Tegra: sip: add VPR resize enabled check
  Tegra194: add redundancy checks for MMIO writes
  Tegra: remove unused cortex_a53.h
  Tegra194: report failure to enable dual execution
  Tegra194: verify firewall settings before resource use
parents 90b0cad4 837df485
...@@ -4,12 +4,13 @@ ...@@ -4,12 +4,13 @@
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <arch.h> #include <arch.h>
#include <asm_macros.S> #include <asm_macros.S>
#include <assert_macros.S> #include <assert_macros.S>
#include <cpu_macros.S>
#include <cortex_a53.h>
#include <cortex_a57.h> #include <cortex_a57.h>
#include <cpu_macros.S>
#include <platform_def.h> #include <platform_def.h>
#include <tegra_def.h> #include <tegra_def.h>
#include <tegra_platform.h> #include <tegra_platform.h>
......
...@@ -17,7 +17,6 @@ ...@@ -17,7 +17,6 @@
#include <bl31/bl31.h> #include <bl31/bl31.h>
#include <common/bl_common.h> #include <common/bl_common.h>
#include <common/debug.h> #include <common/debug.h>
#include <cortex_a53.h>
#include <cortex_a57.h> #include <cortex_a57.h>
#include <denver.h> #include <denver.h>
#include <drivers/console.h> #include <drivers/console.h>
......
...@@ -39,7 +39,7 @@ TEGRA_GICv3_SOURCES := drivers/arm/gic/common/gic_common.c \ ...@@ -39,7 +39,7 @@ TEGRA_GICv3_SOURCES := drivers/arm/gic/common/gic_common.c \
BL31_SOURCES += drivers/delay_timer/delay_timer.c \ BL31_SOURCES += drivers/delay_timer/delay_timer.c \
drivers/io/io_storage.c \ drivers/io/io_storage.c \
plat/common/aarch64/crash_console_helpers.S \ plat/common/aarch64/crash_console_helpers.S \
${TEGRA_GICv2_SOURCES} \ ${TEGRA_LIBS}/debug/profiler.c \
${TEGRA_COMMON}/aarch64/tegra_helpers.S \ ${TEGRA_COMMON}/aarch64/tegra_helpers.S \
${TEGRA_LIBS}/debug/profiler.c \ ${TEGRA_LIBS}/debug/profiler.c \
${TEGRA_COMMON}/tegra_bl31_setup.c \ ${TEGRA_COMMON}/tegra_bl31_setup.c \
......
...@@ -117,13 +117,6 @@ static void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) ...@@ -117,13 +117,6 @@ static void tegra_pwr_domain_suspend(const psci_power_state_t *target_state)
{ {
(void)tegra_soc_pwr_domain_suspend(target_state); (void)tegra_soc_pwr_domain_suspend(target_state);
/* Disable console if we are entering deep sleep. */
if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
PSTATE_ID_SOC_POWERDN) {
(void)console_flush();
console_switch_state(0);
}
/* disable GICC */ /* disable GICC */
tegra_gic_cpuif_deactivate(); tegra_gic_cpuif_deactivate();
} }
...@@ -138,6 +131,14 @@ static __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t ...@@ -138,6 +131,14 @@ static __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t
/* call the chip's power down handler */ /* call the chip's power down handler */
(void)tegra_soc_pwr_domain_power_down_wfi(target_state); (void)tegra_soc_pwr_domain_power_down_wfi(target_state);
/* Disable console if we are entering deep sleep. */
if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
PSTATE_ID_SOC_POWERDN) {
INFO("%s: complete. Entering System Suspend...\n", __func__);
(void)console_flush();
console_switch_state(0);
}
wfi(); wfi();
panic(); panic();
} }
......
...@@ -52,6 +52,12 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid, ...@@ -52,6 +52,12 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
switch (smc_fid) { switch (smc_fid) {
case TEGRA_SIP_NEW_VIDEOMEM_REGION: case TEGRA_SIP_NEW_VIDEOMEM_REGION:
/* Check whether Video memory resize is enabled */
if (mmio_read_32(TEGRA_MC_BASE + MC_VIDEO_PROTECT_REG_CTRL)
!= MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED) {
ERROR("Video Memory Resize isn't enabled! \n");
SMC_RET1(handle, (uint64_t)-ENOTSUP);
}
/* /*
* Check if Video Memory overlaps TZDRAM (contains bl31/bl32) * Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
......
...@@ -32,38 +32,13 @@ static uint64_t video_mem_size_mb; ...@@ -32,38 +32,13 @@ static uint64_t video_mem_size_mb;
*/ */
void tegra_memctrl_setup(void) void tegra_memctrl_setup(void)
{ {
uint32_t val;
const uint32_t *mc_streamid_override_regs;
uint32_t num_streamid_override_regs;
const mc_streamid_security_cfg_t *mc_streamid_sec_cfgs;
uint32_t num_streamid_sec_cfgs;
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
uint32_t i;
INFO("Tegra Memory Controller (v2)\n"); INFO("Tegra Memory Controller (v2)\n");
/* Program the SMMU pagesize */ /* Initialize the System memory management unit */
tegra_smmu_init(); tegra_smmu_init();
/* Get the settings from the platform */ /* allow platforms to program custom memory controller settings */
assert(plat_mc_settings != NULL); plat_memctrl_setup();
mc_streamid_override_regs = plat_mc_settings->streamid_override_cfg;
num_streamid_override_regs = plat_mc_settings->num_streamid_override_cfgs;
mc_streamid_sec_cfgs = plat_mc_settings->streamid_security_cfg;
num_streamid_sec_cfgs = plat_mc_settings->num_streamid_security_cfgs;
/* Program all the Stream ID overrides */
for (i = 0; i < num_streamid_override_regs; i++)
tegra_mc_streamid_write_32(mc_streamid_override_regs[i],
MC_STREAM_ID_MAX);
/* Program the security config settings for all Stream IDs */
for (i = 0; i < num_streamid_sec_cfgs; i++) {
val = mc_streamid_sec_cfgs[i].override_enable << 16 |
mc_streamid_sec_cfgs[i].override_client_inputs << 8 |
mc_streamid_sec_cfgs[i].override_client_ns_flag << 0;
tegra_mc_streamid_write_32(mc_streamid_sec_cfgs[i].offset, val);
}
/* /*
* All requests at boot time, and certain requests during * All requests at boot time, and certain requests during
...@@ -80,21 +55,6 @@ void tegra_memctrl_setup(void) ...@@ -80,21 +55,6 @@ void tegra_memctrl_setup(void)
*/ */
tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG, tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG,
MC_SMMU_BYPASS_CONFIG_SETTINGS); MC_SMMU_BYPASS_CONFIG_SETTINGS);
/*
* Re-configure MSS to allow ROC to deal with ordering of the
* Memory Controller traffic. This is needed as the Memory Controller
* boots with MSS having all control, but ROC provides a performance
* boost as compared to MSS.
*/
if (plat_mc_settings->reconfig_mss_clients != NULL) {
plat_mc_settings->reconfig_mss_clients();
}
/* Program overrides for MC transactions */
if (plat_mc_settings->set_txn_overrides != NULL) {
plat_mc_settings->set_txn_overrides();
}
} }
/* /*
...@@ -102,32 +62,23 @@ void tegra_memctrl_setup(void) ...@@ -102,32 +62,23 @@ void tegra_memctrl_setup(void)
*/ */
void tegra_memctrl_restore_settings(void) void tegra_memctrl_restore_settings(void)
{ {
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings(); /* restore platform's memory controller settings */
plat_memctrl_restore();
assert(plat_mc_settings != NULL);
/*
* Re-configure MSS to allow ROC to deal with ordering of the
* Memory Controller traffic. This is needed as the Memory Controller
* resets during System Suspend with MSS having all control, but ROC
* provides a performance boost as compared to MSS.
*/
if (plat_mc_settings->reconfig_mss_clients != NULL) {
plat_mc_settings->reconfig_mss_clients();
}
/* Program overrides for MC transactions */
if (plat_mc_settings->set_txn_overrides != NULL) {
plat_mc_settings->set_txn_overrides();
}
/* video memory carveout region */ /* video memory carveout region */
if (video_mem_base != 0ULL) { if (video_mem_base != 0ULL) {
tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO,
(uint32_t)video_mem_base); (uint32_t)video_mem_base);
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_BASE_LO)
== (uint32_t)video_mem_base);
tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
(uint32_t)(video_mem_base >> 32)); (uint32_t)(video_mem_base >> 32));
tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size_mb); assert(tegra_mc_read_32(MC_VIDEO_PROTECT_BASE_HI)
== (uint32_t)(video_mem_base >> 32));
tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB,
(uint32_t)video_mem_size_mb);
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_SIZE_MB)
== (uint32_t)video_mem_size_mb);
/* /*
* MCE propagates the VideoMem configuration values across the * MCE propagates the VideoMem configuration values across the
...@@ -167,7 +118,6 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes) ...@@ -167,7 +118,6 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
*/ */
void tegra_mc_save_context(uint64_t mc_ctx_addr) void tegra_mc_save_context(uint64_t mc_ctx_addr)
{ {
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
uint32_t i, num_entries = 0; uint32_t i, num_entries = 0;
mc_regs_t *mc_ctx_regs; mc_regs_t *mc_ctx_regs;
const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
...@@ -177,7 +127,7 @@ void tegra_mc_save_context(uint64_t mc_ctx_addr) ...@@ -177,7 +127,7 @@ void tegra_mc_save_context(uint64_t mc_ctx_addr)
assert((mc_ctx_addr >= tzdram_base) && (mc_ctx_addr <= tzdram_end)); assert((mc_ctx_addr >= tzdram_base) && (mc_ctx_addr <= tzdram_end));
/* get MC context table */ /* get MC context table */
mc_ctx_regs = plat_mc_settings->get_mc_system_suspend_ctx(); mc_ctx_regs = plat_memctrl_get_sys_suspend_ctx();
assert(mc_ctx_regs != NULL); assert(mc_ctx_regs != NULL);
/* /*
...@@ -210,8 +160,12 @@ void tegra_mc_save_context(uint64_t mc_ctx_addr) ...@@ -210,8 +160,12 @@ void tegra_mc_save_context(uint64_t mc_ctx_addr)
/* save the MC table address */ /* save the MC table address */
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_LO, mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_LO,
(uint32_t)mc_ctx_addr); (uint32_t)mc_ctx_addr);
assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_LO)
== (uint32_t)mc_ctx_addr);
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_HI, mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_HI,
(uint32_t)(mc_ctx_addr >> 32)); (uint32_t)(mc_ctx_addr >> 32));
assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_HI)
== (uint32_t)(mc_ctx_addr >> 32));
} }
static void tegra_lock_videomem_nonoverlap(uint64_t phys_base, static void tegra_lock_videomem_nonoverlap(uint64_t phys_base,
...@@ -361,6 +315,14 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) ...@@ -361,6 +315,14 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
(uint32_t)(phys_base >> 32)); (uint32_t)(phys_base >> 32));
tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20); tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20);
/* Redundancy check for Video Protect setting */
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_BASE_LO)
== (uint32_t)phys_base);
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_BASE_HI)
== (uint32_t)(phys_base >> 32));
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_SIZE_MB)
== (size_in_bytes >> 20));
/* /*
* MCE propagates the VideoMem configuration values across the * MCE propagates the VideoMem configuration values across the
* CCPLEX. * CCPLEX.
......
/* /*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -7,58 +8,9 @@ ...@@ -7,58 +8,9 @@
#ifndef MEMCTRL_V2_H #ifndef MEMCTRL_V2_H
#define MEMCTRL_V2_H #define MEMCTRL_V2_H
#include <tegra_def.h> #include <arch.h>
#ifndef __ASSEMBLER__
#include <lib/mmio.h>
#include <stdint.h>
/*******************************************************************************
* Structure to hold the transaction override settings to use to override
* client inputs
******************************************************************************/
typedef struct mc_txn_override_cfg {
uint32_t offset;
uint8_t cgid_tag;
} mc_txn_override_cfg_t;
#define mc_make_txn_override_cfg(off, val) \
{ \
.offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \
.cgid_tag = MC_TXN_OVERRIDE_ ## val \
}
/*******************************************************************************
* Structure to hold the Stream ID to use to override client inputs
******************************************************************************/
typedef struct mc_streamid_override_cfg {
uint32_t offset;
uint8_t stream_id;
} mc_streamid_override_cfg_t;
/******************************************************************************* #include <tegra_def.h>
* Structure to hold the Stream ID Security Configuration settings
******************************************************************************/
typedef struct mc_streamid_security_cfg {
char *name;
uint32_t offset;
int override_enable;
int override_client_inputs;
int override_client_ns_flag;
} mc_streamid_security_cfg_t;
#define OVERRIDE_DISABLE 1U
#define OVERRIDE_ENABLE 0U
#define CLIENT_FLAG_SECURE 0U
#define CLIENT_FLAG_NON_SECURE 1U
#define CLIENT_INPUTS_OVERRIDE 1U
#define CLIENT_INPUTS_NO_OVERRIDE 0U
/*******************************************************************************
* StreamID to indicate no SMMU translations (requests to be steered on the
* SMMU bypass path)
******************************************************************************/
#define MC_STREAM_ID_MAX 0x7FU
/******************************************************************************* /*******************************************************************************
* Memory Controller SMMU Bypass config register * Memory Controller SMMU Bypass config register
...@@ -74,33 +26,15 @@ typedef struct mc_streamid_security_cfg { ...@@ -74,33 +26,15 @@ typedef struct mc_streamid_security_cfg {
#define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \ #define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID) MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
#define mc_make_sec_cfg(off, ns, ovrrd, access) \ #ifndef __ASSEMBLY__
{ \
.name = # off, \ #include <assert.h>
.offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \
MC_STREAMID_OVERRIDE_CFG_ ## off), \
.override_client_ns_flag = CLIENT_FLAG_ ## ns, \
.override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \
.override_enable = OVERRIDE_ ## access \
}
typedef struct mc_regs { typedef struct mc_regs {
uint32_t reg; uint32_t reg;
uint32_t val; uint32_t val;
} mc_regs_t; } mc_regs_t;
#define mc_make_sid_override_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \
.val = 0x00000000U, \
}
#define mc_make_sid_security_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(MC_STREAMID_OVERRIDE_CFG_ ## name), \
.val = 0x00000000U, \
}
#define mc_smmu_bypass_cfg \ #define mc_smmu_bypass_cfg \
{ \ { \
.reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \ .reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \
...@@ -119,20 +53,11 @@ typedef struct mc_regs { ...@@ -119,20 +53,11 @@ typedef struct mc_regs {
.val = 0xFFFFFFFFU, \ .val = 0xFFFFFFFFU, \
} }
/******************************************************************************* #endif /* __ASSEMBLY__ */
* Structure to hold Memory Controller's Configuration settings
******************************************************************************/ #ifndef __ASSEMBLY__
typedef struct tegra_mc_settings {
const uint32_t *streamid_override_cfg; #include <lib/mmio.h>
uint32_t num_streamid_override_cfgs;
const mc_streamid_security_cfg_t *streamid_security_cfg;
uint32_t num_streamid_security_cfgs;
const mc_txn_override_cfg_t *txn_override_cfg;
uint32_t num_txn_override_cfgs;
void (*reconfig_mss_clients)(void);
void (*set_txn_overrides)(void);
mc_regs_t* (*get_mc_system_suspend_ctx)(void);
} tegra_mc_settings_t;
static inline uint32_t tegra_mc_read_32(uint32_t off) static inline uint32_t tegra_mc_read_32(uint32_t off)
{ {
...@@ -153,55 +78,14 @@ static inline uint32_t tegra_mc_streamid_read_32(uint32_t off) ...@@ -153,55 +78,14 @@ static inline uint32_t tegra_mc_streamid_read_32(uint32_t off)
static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val) static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val)
{ {
mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val); mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val);
assert(mmio_read_32(TEGRA_MC_STREAMID_BASE + off) == val);
} }
#endif #endif
#define mc_set_pcfifo_unordered_boot_so_mss(id, client) \ void plat_memctrl_setup(void);
((uint32_t)~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)
#define mc_set_pcfifo_ordered_boot_so_mss(id, client) \
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_ORDERED
#define mc_set_tsa_passthrough(client) \
{ \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
(TSA_CONFIG_STATIC0_CSW_##client##_RESET & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
}
#define mc_set_tsa_w_passthrough(client) \ void plat_memctrl_restore(void);
{ \ mc_regs_t *plat_memctrl_get_sys_suspend_ctx(void);
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
(TSA_CONFIG_STATIC0_CSW_RESET_W & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
}
#define mc_set_tsa_r_passthrough(client) \
{ \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSR_##client, \
(TSA_CONFIG_STATIC0_CSR_RESET_R & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
}
#define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \
{ \
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
MC_TXN_OVERRIDE_##normal_axi_id | \
MC_TXN_OVERRIDE_CONFIG_COH_PATH_##so_dev_override##_SO_DEV | \
MC_TXN_OVERRIDE_CONFIG_COH_PATH_##normal_override##_NORMAL | \
MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \
}
/*******************************************************************************
* Handler to read memory configuration settings
*
* Implemented by SoCs under tegra/soc/txxx
******************************************************************************/
tegra_mc_settings_t *tegra_get_mc_settings(void);
/******************************************************************************* /*******************************************************************************
* Handler to save MC settings before "System Suspend" to TZDRAM * Handler to save MC settings before "System Suspend" to TZDRAM
......
...@@ -104,6 +104,8 @@ ...@@ -104,6 +104,8 @@
#define MC_VIDEO_PROTECT_BASE_HI U(0x978) #define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO U(0x648) #define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
/******************************************************************************* /*******************************************************************************
* Tegra TZRAM constants * Tegra TZRAM constants
......
...@@ -163,6 +163,8 @@ ...@@ -163,6 +163,8 @@
#define MC_VIDEO_PROTECT_BASE_HI U(0x978) #define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO U(0x648) #define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64C) #define MC_VIDEO_PROTECT_SIZE_MB U(0x64C)
#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
/* /*
* Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
......
/* /*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -282,4 +282,117 @@ ...@@ -282,4 +282,117 @@
#define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 24) #define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 24)
#define MC_CLIENT_HOTRESET_STATUS1 0x974U #define MC_CLIENT_HOTRESET_STATUS1 0x974U
#ifndef __ASSEMBLY__
/*******************************************************************************
* Structure to hold the transaction override settings to use to override
* client inputs
******************************************************************************/
typedef struct mc_txn_override_cfg {
uint32_t offset;
uint8_t cgid_tag;
} mc_txn_override_cfg_t;
#define mc_make_txn_override_cfg(off, val) \
{ \
.offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \
.cgid_tag = MC_TXN_OVERRIDE_ ## val \
}
/*******************************************************************************
* Structure to hold the Stream ID to use to override client inputs
******************************************************************************/
typedef struct mc_streamid_override_cfg {
uint32_t offset;
uint8_t stream_id;
} mc_streamid_override_cfg_t;
/*******************************************************************************
* Structure to hold the Stream ID Security Configuration settings
******************************************************************************/
typedef struct mc_streamid_security_cfg {
char *name;
uint32_t offset;
uint32_t override_enable;
uint32_t override_client_inputs;
uint32_t override_client_ns_flag;
} mc_streamid_security_cfg_t;
#define OVERRIDE_DISABLE 1U
#define OVERRIDE_ENABLE 0U
#define CLIENT_FLAG_SECURE 0U
#define CLIENT_FLAG_NON_SECURE 1U
#define CLIENT_INPUTS_OVERRIDE 1U
#define CLIENT_INPUTS_NO_OVERRIDE 0U
/*******************************************************************************
* StreamID to indicate no SMMU translations (requests to be steered on the
* SMMU bypass path)
******************************************************************************/
#define MC_STREAM_ID_MAX 0x7FU
#define mc_make_sec_cfg(off, ns, ovrrd, access) \
{ \
.name = # off, \
.offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \
MC_STREAMID_OVERRIDE_CFG_ ## off), \
.override_client_ns_flag = CLIENT_FLAG_ ## ns, \
.override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \
.override_enable = OVERRIDE_ ## access \
}
#define mc_make_sid_override_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \
.val = 0x00000000U, \
}
#define mc_make_sid_security_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(MC_STREAMID_OVERRIDE_CFG_ ## name), \
.val = 0x00000000U, \
}
#define mc_set_pcfifo_unordered_boot_so_mss(id, client) \
((uint32_t)~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)
#define mc_set_pcfifo_ordered_boot_so_mss(id, client) \
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_ORDERED
#define mc_set_tsa_passthrough(client) \
do { \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
(TSA_CONFIG_STATIC0_CSW_##client##_RESET & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
} while (0)
#define mc_set_tsa_w_passthrough(client) \
do { \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
(TSA_CONFIG_STATIC0_CSW_RESET_W & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
} while (0)
#define mc_set_tsa_r_passthrough(client) \
{ \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSR_##client, \
(TSA_CONFIG_STATIC0_CSR_RESET_R & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
} while (0)
#define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \
do { \
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
MC_TXN_OVERRIDE_##normal_axi_id | \
MC_TXN_OVERRIDE_CONFIG_COH_PATH_##so_dev_override##_SO_DEV | \
MC_TXN_OVERRIDE_CONFIG_COH_PATH_##normal_override##_NORMAL | \
MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \
} while (0)
#endif /* __ASSEMBLY__ */
#endif /* TEGRA_MC_DEF_H */ #endif /* TEGRA_MC_DEF_H */
...@@ -105,6 +105,8 @@ ...@@ -105,6 +105,8 @@
#define MC_VIDEO_PROTECT_BASE_HI U(0x978) #define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO U(0x648) #define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
/* /*
* Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
...@@ -294,4 +296,26 @@ ...@@ -294,4 +296,26 @@
#define TEGRA_SID_XUSB_VF2 U(0x5f) #define TEGRA_SID_XUSB_VF2 U(0x5f)
#define TEGRA_SID_XUSB_VF3 U(0x60) #define TEGRA_SID_XUSB_VF3 U(0x60)
/*******************************************************************************
* SCR addresses and expected settings
******************************************************************************/
#define SCRATCH_RSV68_SCR U(0x0C398110)
#define SCRATCH_RSV68_SCR_VAL U(0x38000101)
#define SCRATCH_RSV71_SCR U(0x0C39811C)
#define SCRATCH_RSV71_SCR_VAL U(0x38000101)
#define SCRATCH_RSV72_SCR U(0x0C398120)
#define SCRATCH_RSV72_SCR_VAL U(0x38000101)
#define SCRATCH_RSV75_SCR U(0x0C39812C)
#define SCRATCH_RSV75_SCR_VAL U(0x3A000005)
#define SCRATCH_RSV81_SCR U(0x0C398144)
#define SCRATCH_RSV81_SCR_VAL U(0x3A000105)
#define SCRATCH_RSV97_SCR U(0x0C398184)
#define SCRATCH_RSV97_SCR_VAL U(0x38000101)
#define SCRATCH_RSV99_SCR U(0x0C39818C)
#define SCRATCH_RSV99_SCR_VAL U(0x38000101)
#define SCRATCH_RSV109_SCR U(0x0C3981B4)
#define SCRATCH_RSV109_SCR_VAL U(0x38000101)
#define MISCREG_SCR_SCRTZWELCK U(0x00109000)
#define MISCREG_SCR_SCRTZWELCK_VAL U(0x30000100)
#endif /* TEGRA_DEF_H */ #endif /* TEGRA_DEF_H */
This diff is collapsed.
...@@ -240,6 +240,8 @@ ...@@ -240,6 +240,8 @@
#define MC_VIDEO_PROTECT_BASE_HI U(0x978) #define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO U(0x648) #define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
/* SMMU configuration registers*/ /* SMMU configuration registers*/
#define MC_SMMU_PPCS_ASID_0 0x270U #define MC_SMMU_PPCS_ASID_0 0x270U
......
...@@ -68,6 +68,11 @@ struct tegra_bl31_params { ...@@ -68,6 +68,11 @@ struct tegra_bl31_params {
image_info_t *bl33_image_info; image_info_t *bl33_image_info;
}; };
/*******************************************************************************
* To suppress Coverity MISRA C-2012 Rule 2.2 violations
*******************************************************************************/
#define UNUSED_FUNC_NOP() asm("nop")
/* Declarations for plat_psci_handlers.c */ /* Declarations for plat_psci_handlers.c */
int32_t tegra_soc_validate_power_state(uint32_t power_state, int32_t tegra_soc_validate_power_state(uint32_t power_state,
psci_power_state_t *req_state); psci_power_state_t *req_state);
...@@ -146,7 +151,7 @@ int plat_sip_handler(uint32_t smc_fid, ...@@ -146,7 +151,7 @@ int plat_sip_handler(uint32_t smc_fid,
#if RAS_EXTENSION #if RAS_EXTENSION
void tegra194_ras_enable(void); void tegra194_ras_enable(void);
void tegra194_ras_corrected_err_clear(void); void tegra194_ras_corrected_err_clear(uint64_t *cookie);
#endif #endif
#endif /* TEGRA_PRIVATE_H */ #endif /* TEGRA_PRIVATE_H */
...@@ -23,7 +23,8 @@ $(eval $(call add_define,MAX_MMAP_REGIONS)) ...@@ -23,7 +23,8 @@ $(eval $(call add_define,MAX_MMAP_REGIONS))
# platform files # platform files
PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t132 PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t132
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ BL31_SOURCES += ${TEGRA_GICv2_SOURCES} \
drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/denver.S \ lib/cpus/aarch64/denver.S \
${TEGRA_DRIVERS}/flowctrl/flowctrl.c \ ${TEGRA_DRIVERS}/flowctrl/flowctrl.c \
${TEGRA_DRIVERS}/memctrl/memctrl_v1.c \ ${TEGRA_DRIVERS}/memctrl/memctrl_v1.c \
......
...@@ -402,16 +402,8 @@ static void tegra186_memctrl_reconfig_mss_clients(void) ...@@ -402,16 +402,8 @@ static void tegra186_memctrl_reconfig_mss_clients(void)
static void tegra186_memctrl_set_overrides(void) static void tegra186_memctrl_set_overrides(void)
{ {
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
const mc_txn_override_cfg_t *mc_txn_override_cfgs;
uint32_t num_txn_override_cfgs;
uint32_t i, val; uint32_t i, val;
/* Get the settings from the platform */
assert(plat_mc_settings != NULL);
mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg;
num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs;
/* /*
* Set the MC_TXN_OVERRIDE registers for write clients. * Set the MC_TXN_OVERRIDE registers for write clients.
*/ */
...@@ -443,11 +435,11 @@ static void tegra186_memctrl_set_overrides(void) ...@@ -443,11 +435,11 @@ static void tegra186_memctrl_set_overrides(void)
/* /*
* Settings for Tegra186 silicon rev. A02 and onwards. * Settings for Tegra186 silicon rev. A02 and onwards.
*/ */
for (i = 0; i < num_txn_override_cfgs; i++) { for (i = 0; i < ARRAY_SIZE(tegra186_txn_override_cfgs); i++) {
val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset); val = tegra_mc_read_32(tegra186_txn_override_cfgs[i].offset);
val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK; val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(mc_txn_override_cfgs[i].offset, tegra_mc_write_32(tegra186_txn_override_cfgs[i].offset,
val | mc_txn_override_cfgs[i].cgid_tag); val | tegra186_txn_override_cfgs[i].cgid_tag);
} }
} }
} }
...@@ -609,7 +601,7 @@ static __attribute__((aligned(16))) mc_regs_t tegra186_mc_context[] = { ...@@ -609,7 +601,7 @@ static __attribute__((aligned(16))) mc_regs_t tegra186_mc_context[] = {
/******************************************************************************* /*******************************************************************************
* Handler to return the pointer to the MC's context struct * Handler to return the pointer to the MC's context struct
******************************************************************************/ ******************************************************************************/
static mc_regs_t *tegra186_get_mc_system_suspend_ctx(void) mc_regs_t *plat_memctrl_get_sys_suspend_ctx(void)
{ {
/* index of _END_OF_TABLE_ */ /* index of _END_OF_TABLE_ */
tegra186_mc_context[0].val = (uint32_t)(ARRAY_SIZE(tegra186_mc_context)) - 1U; tegra186_mc_context[0].val = (uint32_t)(ARRAY_SIZE(tegra186_mc_context)) - 1U;
...@@ -617,27 +609,52 @@ static mc_regs_t *tegra186_get_mc_system_suspend_ctx(void) ...@@ -617,27 +609,52 @@ static mc_regs_t *tegra186_get_mc_system_suspend_ctx(void)
return tegra186_mc_context; return tegra186_mc_context;
} }
/******************************************************************************* void plat_memctrl_setup(void)
* Struct to hold the memory controller settings {
******************************************************************************/ uint32_t val;
static tegra_mc_settings_t tegra186_mc_settings = { unsigned int i;
.streamid_override_cfg = tegra186_streamid_override_regs,
.num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_streamid_override_regs), /* Program all the Stream ID overrides */
.streamid_security_cfg = tegra186_streamid_sec_cfgs, for (i = 0U; i < ARRAY_SIZE(tegra186_streamid_override_regs); i++) {
.num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra186_streamid_sec_cfgs), tegra_mc_streamid_write_32(tegra186_streamid_override_regs[i],
.txn_override_cfg = tegra186_txn_override_cfgs, MC_STREAM_ID_MAX);
.num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_txn_override_cfgs), }
.reconfig_mss_clients = tegra186_memctrl_reconfig_mss_clients,
.set_txn_overrides = tegra186_memctrl_set_overrides, /* Program the security config settings for all Stream IDs */
.get_mc_system_suspend_ctx = tegra186_get_mc_system_suspend_ctx, for (i = 0U; i < ARRAY_SIZE(tegra186_streamid_sec_cfgs); i++) {
}; val = (tegra186_streamid_sec_cfgs[i].override_enable << 16) |
(tegra186_streamid_sec_cfgs[i].override_client_inputs << 8) |
(tegra186_streamid_sec_cfgs[i].override_client_ns_flag << 0);
tegra_mc_streamid_write_32(tegra186_streamid_sec_cfgs[i].offset, val);
}
/*
* Re-configure MSS to allow ROC to deal with ordering of the
* Memory Controller traffic. This is needed as the Memory Controller
* boots with MSS having all control, but ROC provides a performance
* boost as compared to MSS.
*/
tegra186_memctrl_reconfig_mss_clients();
/* Program overrides for MC transactions */
tegra186_memctrl_set_overrides();
}
/******************************************************************************* /*******************************************************************************
* Handler to return the pointer to the memory controller's settings struct * Handler to restore platform specific settings to the memory controller
******************************************************************************/ ******************************************************************************/
tegra_mc_settings_t *tegra_get_mc_settings(void) void plat_memctrl_restore(void)
{ {
return &tegra186_mc_settings; /*
* Re-configure MSS to allow ROC to deal with ordering of the
* Memory Controller traffic. This is needed as the Memory Controller
* boots with MSS having all control, but ROC provides a performance
* boost as compared to MSS.
*/
tegra186_memctrl_reconfig_mss_clients();
/* Program overrides for MC transactions */
tegra186_memctrl_set_overrides();
} }
/******************************************************************************* /*******************************************************************************
......
...@@ -40,7 +40,8 @@ $(eval $(call add_define,MAX_MMAP_REGIONS)) ...@@ -40,7 +40,8 @@ $(eval $(call add_define,MAX_MMAP_REGIONS))
PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t186 \ PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t186 \
-I${SOC_DIR}/drivers/include -I${SOC_DIR}/drivers/include
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ BL31_SOURCES += ${TEGRA_GICv2_SOURCES} \
drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/denver.S \ lib/cpus/aarch64/denver.S \
lib/cpus/aarch64/cortex_a57.S \ lib/cpus/aarch64/cortex_a57.S \
${TEGRA_DRIVERS}/bpmp_ipc/intf.c \ ${TEGRA_DRIVERS}/bpmp_ipc/intf.c \
......
...@@ -56,6 +56,7 @@ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx); ...@@ -56,6 +56,7 @@ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time); int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
int32_t nvg_roc_clean_cache_trbits(void); int32_t nvg_roc_clean_cache_trbits(void);
void nvg_enable_strict_checking_mode(void); void nvg_enable_strict_checking_mode(void);
void nvg_verify_strict_checking_mode(void);
void nvg_system_shutdown(void); void nvg_system_shutdown(void);
void nvg_system_reboot(void); void nvg_system_reboot(void);
void nvg_clear_hsm_corr_status(void); void nvg_clear_hsm_corr_status(void);
...@@ -70,6 +71,7 @@ uint64_t nvg_cache_inval_all(void); ...@@ -70,6 +71,7 @@ uint64_t nvg_cache_inval_all(void);
/* MCE helper functions */ /* MCE helper functions */
void mce_enable_strict_checking(void); void mce_enable_strict_checking(void);
void mce_verify_strict_checking(void);
void mce_system_shutdown(void); void mce_system_shutdown(void);
void mce_system_reboot(void); void mce_system_reboot(void);
void mce_clear_hsm_corr_status(void); void mce_clear_hsm_corr_status(void);
......
...@@ -217,6 +217,15 @@ void mce_enable_strict_checking(void) ...@@ -217,6 +217,15 @@ void mce_enable_strict_checking(void)
nvg_enable_strict_checking_mode(); nvg_enable_strict_checking_mode();
} }
} }
void mce_verify_strict_checking(void)
{
bool is_silicon = tegra_platform_is_silicon();
bool is_fpga = tegra_platform_is_fpga();
if (is_silicon || is_fpga) {
nvg_verify_strict_checking_mode();
}
}
#endif #endif
/******************************************************************************* /*******************************************************************************
......
...@@ -4,12 +4,15 @@ ...@@ -4,12 +4,15 @@
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <assert.h>
#include <errno.h>
#include <arch.h> #include <arch.h>
#include <arch_helpers.h> #include <arch_helpers.h>
#include <common/debug.h> #include <common/debug.h>
#include <denver.h> #include <denver.h>
#include <errno.h>
#include <lib/mmio.h> #include <lib/mmio.h>
#include <mce_private.h> #include <mce_private.h>
#include <platform_def.h> #include <platform_def.h>
#include <t194_nvg.h> #include <t194_nvg.h>
...@@ -211,6 +214,15 @@ void nvg_enable_strict_checking_mode(void) ...@@ -211,6 +214,15 @@ void nvg_enable_strict_checking_mode(void)
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params); nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params);
} }
void nvg_verify_strict_checking_mode(void)
{
uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET |
STRICT_CHECKING_LOCKED_SET);
nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_SECURITY_CONFIG);
assert(params == (uint64_t)nvg_get_result());
}
#endif #endif
/* /*
......
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