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Commit 86a3b266 authored by davidcunado-arm's avatar davidcunado-arm Committed by GitHub
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Merge pull request #849 from vwadekar/tegra-changes-from-downstream-v2 

Tegra changes from downstream v2
parents 87bf3c62 26c0d9b2
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include/lib/cpus/aarch64/denver.h
View file @ 86a3b266
/* /*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -44,4 +44,11 @@ ...@@ -44,4 +44,11 @@
/* CPU state ids - implementation defined */ /* CPU state ids - implementation defined */
#define DENVER_CPU_STATE_POWER_DOWN 0x3 #define DENVER_CPU_STATE_POWER_DOWN 0x3
#ifndef __ASSEMBLY__
/* Disable Dynamic Code Optimisation */
void denver_disable_dco(void);
#endif
#endif /* __DENVER_H__ */ #endif /* __DENVER_H__ */
lib/cpus/aarch64/denver.S
View file @ 86a3b266
/* /*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -35,6 +35,8 @@ ...@@ -35,6 +35,8 @@
#include <cpu_macros.S> #include <cpu_macros.S>
#include <plat_macros.S> #include <plat_macros.S>
.global denver_disable_dco
/* --------------------------------------------- /* ---------------------------------------------
* Disable debug interfaces * Disable debug interfaces
* --------------------------------------------- * ---------------------------------------------
...@@ -111,22 +113,6 @@ func denver_core_pwr_dwn ...@@ -111,22 +113,6 @@ func denver_core_pwr_dwn
mov x19, x30 mov x19, x30
/* ----------------------------------------------------
* We enter the 'core power gated with ARM state not
* retained' power state during CPU power down. We let
* DCO know that we expect to enter this power state
* by writing to the ACTLR_EL1 register.
* ----------------------------------------------------
*/
mov x0, #DENVER_CPU_STATE_POWER_DOWN
msr actlr_el1, x0
/* ---------------------------------------------
* Force DCO to be quiescent
* ---------------------------------------------
*/
bl denver_disable_dco
/* --------------------------------------------- /* ---------------------------------------------
* Force the debug interfaces to be quiescent * Force the debug interfaces to be quiescent
* --------------------------------------------- * ---------------------------------------------
......
plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
View file @ 86a3b266
...@@ -89,6 +89,14 @@ void tegra_memctrl_setup(void) ...@@ -89,6 +89,14 @@ void tegra_memctrl_setup(void)
tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size); tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size);
} }
/*
* Restore Memory Controller settings after "System Suspend"
*/
void tegra_memctrl_restore_settings(void)
{
tegra_memctrl_setup();
}
/* /*
* Secure the BL31 DRAM aperture. * Secure the BL31 DRAM aperture.
* *
...@@ -107,6 +115,20 @@ void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) ...@@ -107,6 +115,20 @@ void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20);
} }
/*
* Secure the BL31 TZRAM aperture.
*
* phys_base = physical base of TZRAM aperture
* size_in_bytes = size of aperture in bytes
*/
void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
{
/*
* The v1 hardware controller does not have any registers
* for setting up the on-chip TZRAM.
*/
}
static void tegra_clear_videomem(uintptr_t non_overlap_area_start, static void tegra_clear_videomem(uintptr_t non_overlap_area_start,
unsigned long long non_overlap_area_size) unsigned long long non_overlap_area_size)
{ {
......
plat/nvidia/tegra/common/tegra_bl31_setup.c
View file @ 86a3b266
/* /*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -44,6 +44,7 @@ ...@@ -44,6 +44,7 @@
#include <platform.h> #include <platform.h>
#include <platform_def.h> #include <platform_def.h>
#include <stddef.h> #include <stddef.h>
#include <tegra_def.h>
#include <tegra_private.h> #include <tegra_private.h>
/******************************************************************************* /*******************************************************************************
...@@ -183,6 +184,12 @@ void bl31_platform_setup(void) ...@@ -183,6 +184,12 @@ void bl31_platform_setup(void)
tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
plat_bl31_params_from_bl2.tzdram_size); plat_bl31_params_from_bl2.tzdram_size);
/*
* Set up the TZRAM memory aperture to allow only secure world
* access
*/
tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
/* Set the next EL to be AArch64 */ /* Set the next EL to be AArch64 */
tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; tmp_reg = SCR_RES1_BITS | SCR_RW_BIT;
write_scr(tmp_reg); write_scr(tmp_reg);
...@@ -193,6 +200,16 @@ void bl31_platform_setup(void) ...@@ -193,6 +200,16 @@ void bl31_platform_setup(void)
INFO("BL3-1: Tegra platform setup complete\n"); INFO("BL3-1: Tegra platform setup complete\n");
} }
/*******************************************************************************
* Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit
******************************************************************************/
void bl31_plat_runtime_setup(void)
{
/* Initialize the runtime console */
console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
TEGRA_CONSOLE_BAUDRATE);
}
/******************************************************************************* /*******************************************************************************
* Perform the very early platform specific architectural setup here. At the * Perform the very early platform specific architectural setup here. At the
* moment this only intializes the mmu in a quick and dirty way. * moment this only intializes the mmu in a quick and dirty way.
...@@ -208,6 +225,7 @@ void bl31_plat_arch_setup(void) ...@@ -208,6 +225,7 @@ void bl31_plat_arch_setup(void)
#if USE_COHERENT_MEM #if USE_COHERENT_MEM
unsigned long coh_start, coh_size; unsigned long coh_start, coh_size;
#endif #endif
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
/* add memory regions */ /* add memory regions */
mmap_add_region(total_base, total_base, mmap_add_region(total_base, total_base,
...@@ -217,6 +235,14 @@ void bl31_plat_arch_setup(void) ...@@ -217,6 +235,14 @@ void bl31_plat_arch_setup(void)
ro_size, ro_size,
MT_MEMORY | MT_RO | MT_SECURE); MT_MEMORY | MT_RO | MT_SECURE);
/* map TZDRAM used by BL31 as coherent memory */
if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
mmap_add_region(params_from_bl2->tzdram_base,
params_from_bl2->tzdram_base,
BL31_SIZE,
MT_DEVICE | MT_RW | MT_SECURE);
}
#if USE_COHERENT_MEM #if USE_COHERENT_MEM
coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
......
plat/nvidia/tegra/common/tegra_common.mk
View file @ 86a3b266
...@@ -59,4 +59,5 @@ BL31_SOURCES += drivers/arm/gic/gic_v2.c \ ...@@ -59,4 +59,5 @@ BL31_SOURCES += drivers/arm/gic/gic_v2.c \
${COMMON_DIR}/tegra_delay_timer.c \ ${COMMON_DIR}/tegra_delay_timer.c \
${COMMON_DIR}/tegra_gic.c \ ${COMMON_DIR}/tegra_gic.c \
${COMMON_DIR}/tegra_pm.c \ ${COMMON_DIR}/tegra_pm.c \
${COMMON_DIR}/tegra_sip_calls.c \
${COMMON_DIR}/tegra_topology.c ${COMMON_DIR}/tegra_topology.c
plat/nvidia/tegra/common/tegra_pm.c
View file @ 86a3b266
/* /*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -54,7 +54,9 @@ extern uint64_t tegra_sec_entry_point; ...@@ -54,7 +54,9 @@ extern uint64_t tegra_sec_entry_point;
#pragma weak tegra_soc_pwr_domain_on #pragma weak tegra_soc_pwr_domain_on
#pragma weak tegra_soc_pwr_domain_off #pragma weak tegra_soc_pwr_domain_off
#pragma weak tegra_soc_pwr_domain_on_finish #pragma weak tegra_soc_pwr_domain_on_finish
#pragma weak tegra_soc_pwr_domain_power_down_wfi
#pragma weak tegra_soc_prepare_system_reset #pragma weak tegra_soc_prepare_system_reset
#pragma weak tegra_soc_prepare_system_off
int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
{ {
...@@ -76,11 +78,22 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) ...@@ -76,11 +78,22 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
return PSCI_E_SUCCESS; return PSCI_E_SUCCESS;
} }
int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
{
return PSCI_E_SUCCESS;
}
int tegra_soc_prepare_system_reset(void) int tegra_soc_prepare_system_reset(void)
{ {
return PSCI_E_SUCCESS; return PSCI_E_SUCCESS;
} }
__dead2 void tegra_soc_prepare_system_off(void)
{
ERROR("Tegra System Off: operation not handled.\n");
panic();
}
/******************************************************************************* /*******************************************************************************
* This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND` * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND`
* call to get the `power_state` parameter. This allows the platform to encode * call to get the `power_state` parameter. This allows the platform to encode
...@@ -129,7 +142,7 @@ void tegra_pwr_domain_off(const psci_power_state_t *target_state) ...@@ -129,7 +142,7 @@ void tegra_pwr_domain_off(const psci_power_state_t *target_state)
} }
/******************************************************************************* /*******************************************************************************
* Handler called when called when a power domain is about to be suspended. The * Handler called when a power domain is about to be suspended. The
* target_state encodes the power state that each level should transition to. * target_state encodes the power state that each level should transition to.
******************************************************************************/ ******************************************************************************/
void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) void tegra_pwr_domain_suspend(const psci_power_state_t *target_state)
...@@ -140,6 +153,24 @@ void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) ...@@ -140,6 +153,24 @@ void tegra_pwr_domain_suspend(const psci_power_state_t *target_state)
tegra_gic_cpuif_deactivate(); tegra_gic_cpuif_deactivate();
} }
/*******************************************************************************
* Handler called at the end of the power domain suspend sequence. The
* target_state encodes the power state that each level should transition to.
******************************************************************************/
__dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t
*target_state)
{
/* call the chip's power down handler */
tegra_soc_pwr_domain_power_down_wfi(target_state);
/* enter power down state */
wfi();
/* we can never reach here */
ERROR("%s: operation not handled.\n", __func__);
panic();
}
/******************************************************************************* /*******************************************************************************
* Handler called when a power domain has just been powered on after * Handler called when a power domain has just been powered on after
* being turned off earlier. The target_state encodes the low power state that * being turned off earlier. The target_state encodes the low power state that
...@@ -161,14 +192,10 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) ...@@ -161,14 +192,10 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
PSTATE_ID_SOC_POWERDN) { PSTATE_ID_SOC_POWERDN) {
/* /*
* Lock scratch registers which hold the CPU vectors. * Restore Memory Controller settings as it loses state
*/ * during system suspend.
tegra_pmc_lock_cpu_vectors();
/*
* SMMU configuration.
*/ */
tegra_memctrl_setup(); tegra_memctrl_restore_settings();
/* /*
* Security configuration to allow DRAM/device access. * Security configuration to allow DRAM/device access.
...@@ -199,8 +226,9 @@ void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state) ...@@ -199,8 +226,9 @@ void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
******************************************************************************/ ******************************************************************************/
__dead2 void tegra_system_off(void) __dead2 void tegra_system_off(void)
{ {
ERROR("Tegra System Off: operation not handled.\n"); INFO("Powering down system...\n");
panic();
tegra_soc_prepare_system_off();
} }
/******************************************************************************* /*******************************************************************************
...@@ -208,6 +236,8 @@ __dead2 void tegra_system_off(void) ...@@ -208,6 +236,8 @@ __dead2 void tegra_system_off(void)
******************************************************************************/ ******************************************************************************/
__dead2 void tegra_system_reset(void) __dead2 void tegra_system_reset(void)
{ {
INFO("Restarting system...\n");
/* per-SoC system reset handler */ /* per-SoC system reset handler */
tegra_soc_prepare_system_reset(); tegra_soc_prepare_system_reset();
...@@ -223,13 +253,8 @@ __dead2 void tegra_system_reset(void) ...@@ -223,13 +253,8 @@ __dead2 void tegra_system_reset(void)
int32_t tegra_validate_power_state(unsigned int power_state, int32_t tegra_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state) psci_power_state_t *req_state)
{ {
int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
assert(req_state); assert(req_state);
if (pwr_lvl > PLAT_MAX_PWR_LVL)
return PSCI_E_INVALID_PARAMS;
return tegra_soc_validate_power_state(power_state, req_state); return tegra_soc_validate_power_state(power_state, req_state);
} }
...@@ -258,6 +283,7 @@ static const plat_psci_ops_t tegra_plat_psci_ops = { ...@@ -258,6 +283,7 @@ static const plat_psci_ops_t tegra_plat_psci_ops = {
.pwr_domain_suspend = tegra_pwr_domain_suspend, .pwr_domain_suspend = tegra_pwr_domain_suspend,
.pwr_domain_on_finish = tegra_pwr_domain_on_finish, .pwr_domain_on_finish = tegra_pwr_domain_on_finish,
.pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish, .pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish,
.pwr_domain_pwr_down_wfi = tegra_pwr_domain_power_down_wfi,
.system_off = tegra_system_off, .system_off = tegra_system_off,
.system_reset = tegra_system_reset, .system_reset = tegra_system_reset,
.validate_power_state = tegra_validate_power_state, .validate_power_state = tegra_validate_power_state,
......
plat/nvidia/tegra/soc/t210/plat_sip_calls.c → plat/nvidia/tegra/common/tegra_sip_calls.c
View file @ 86a3b266
...@@ -32,7 +32,6 @@ ...@@ -32,7 +32,6 @@
#include <arch_helpers.h> #include <arch_helpers.h>
#include <assert.h> #include <assert.h>
#include <bl_common.h> #include <bl_common.h>
#include <context_mgmt.h>
#include <debug.h> #include <debug.h>
#include <errno.h> #include <errno.h>
#include <memctrl.h> #include <memctrl.h>
...@@ -40,14 +39,30 @@ ...@@ -40,14 +39,30 @@
#include <tegra_private.h> #include <tegra_private.h>
/******************************************************************************* /*******************************************************************************
* Tegra210 SiP SMCs * Common Tegra SiP SMCs
******************************************************************************/ ******************************************************************************/
#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 #define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
/*******************************************************************************
* SoC specific SiP handler
******************************************************************************/
#pragma weak plat_sip_handler
int plat_sip_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
uint64_t x4,
void *cookie,
void *handle,
uint64_t flags)
{
return -ENOTSUP;
}
/******************************************************************************* /*******************************************************************************
* This function is responsible for handling all SiP calls from the NS world * This function is responsible for handling all SiP calls from the NS world
******************************************************************************/ ******************************************************************************/
uint64_t tegra210_sip_handler(uint32_t smc_fid, uint64_t tegra_sip_handler(uint32_t smc_fid,
uint64_t x1, uint64_t x1,
uint64_t x2, uint64_t x2,
uint64_t x3, uint64_t x3,
...@@ -64,6 +79,11 @@ uint64_t tegra210_sip_handler(uint32_t smc_fid, ...@@ -64,6 +79,11 @@ uint64_t tegra210_sip_handler(uint32_t smc_fid,
if (!ns) if (!ns)
SMC_RET1(handle, SMC_UNK); SMC_RET1(handle, SMC_UNK);
/* Check if this is a SoC specific SiP */
err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
if (err == 0)
SMC_RET1(handle, err);
switch (smc_fid) { switch (smc_fid) {
case TEGRA_SIP_NEW_VIDEOMEM_REGION: case TEGRA_SIP_NEW_VIDEOMEM_REGION:
...@@ -104,11 +124,11 @@ uint64_t tegra210_sip_handler(uint32_t smc_fid, ...@@ -104,11 +124,11 @@ uint64_t tegra210_sip_handler(uint32_t smc_fid,
/* Define a runtime service descriptor for fast SMC calls */ /* Define a runtime service descriptor for fast SMC calls */
DECLARE_RT_SVC( DECLARE_RT_SVC(
tegra210_sip_fast, tegra_sip_fast,
OEN_SIP_START, OEN_SIP_START,
OEN_SIP_END, OEN_SIP_END,
SMC_TYPE_FAST, SMC_TYPE_FAST,
NULL, NULL,
tegra210_sip_handler tegra_sip_handler
); );
plat/nvidia/tegra/include/drivers/memctrl.h
View file @ 86a3b266
/* /*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -32,7 +32,9 @@ ...@@ -32,7 +32,9 @@
#define __MEMCTRL_H__ #define __MEMCTRL_H__
void tegra_memctrl_setup(void); void tegra_memctrl_setup(void);
void tegra_memctrl_restore_settings(void);
void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes); void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes);
void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes);
void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes); void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes);
#endif /* __MEMCTRL_H__ */ #endif /* __MEMCTRL_H__ */
plat/nvidia/tegra/include/drivers/memctrl_v1.h
View file @ 86a3b266
/* /*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
......
plat/nvidia/tegra/include/platform_def.h
View file @ 86a3b266
...@@ -52,12 +52,6 @@ ...@@ -52,12 +52,6 @@
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
PLATFORM_CLUSTER_COUNT + 1) PLATFORM_CLUSTER_COUNT + 1)
/*******************************************************************************
* Platform power states
******************************************************************************/
#define PLAT_MAX_RET_STATE 1
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1)
/******************************************************************************* /*******************************************************************************
* Platform console related constants * Platform console related constants
******************************************************************************/ ******************************************************************************/
...@@ -74,7 +68,7 @@ ...@@ -74,7 +68,7 @@
/******************************************************************************* /*******************************************************************************
* BL31 specific defines. * BL31 specific defines.
******************************************************************************/ ******************************************************************************/
#define BL31_SIZE 0x20000 #define BL31_SIZE 0x40000
#define BL31_BASE TZDRAM_BASE #define BL31_BASE TZDRAM_BASE
#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
#define BL32_BASE (TZDRAM_BASE + BL31_SIZE) #define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
......
plat/nvidia/tegra/include/t132/tegra_def.h
View file @ 86a3b266
/* /*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -39,6 +39,15 @@ ...@@ -39,6 +39,15 @@
******************************************************************************/ ******************************************************************************/
#define PSTATE_ID_SOC_POWERDN 0xD #define PSTATE_ID_SOC_POWERDN 0xD
/*******************************************************************************
* Platform power states (used by PSCI framework)
*
* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
******************************************************************************/
#define PLAT_MAX_RET_STATE 1
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1)
/******************************************************************************* /*******************************************************************************
* GIC memory map * GIC memory map
******************************************************************************/ ******************************************************************************/
...@@ -89,4 +98,10 @@ ...@@ -89,4 +98,10 @@
******************************************************************************/ ******************************************************************************/
#define TEGRA_MC_BASE 0x70019000 #define TEGRA_MC_BASE 0x70019000
/*******************************************************************************
* Tegra TZRAM constants
******************************************************************************/
#define TEGRA_TZRAM_BASE 0x7C010000
#define TEGRA_TZRAM_SIZE 0x10000
#endif /* __TEGRA_DEF_H__ */ #endif /* __TEGRA_DEF_H__ */
plat/nvidia/tegra/include/t210/tegra_def.h
View file @ 86a3b266
/* /*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -47,6 +47,15 @@ ...@@ -47,6 +47,15 @@
******************************************************************************/ ******************************************************************************/
#define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN
/*******************************************************************************
* Platform power states (used by PSCI framework)
*
* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
******************************************************************************/
#define PLAT_MAX_RET_STATE 1
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1)
/******************************************************************************* /*******************************************************************************
* GIC memory map * GIC memory map
******************************************************************************/ ******************************************************************************/
...@@ -114,4 +123,10 @@ ...@@ -114,4 +123,10 @@
******************************************************************************/ ******************************************************************************/
#define TEGRA_MC_BASE 0x70019000 #define TEGRA_MC_BASE 0x70019000
/*******************************************************************************
* Tegra TZRAM constants
******************************************************************************/
#define TEGRA_TZRAM_BASE 0x7C010000
#define TEGRA_TZRAM_SIZE 0x10000
#endif /* __TEGRA_DEF_H__ */ #endif /* __TEGRA_DEF_H__ */
plat/nvidia/tegra/platform.mk
View file @ 86a3b266
# #
# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. # Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
# #
# Redistribution and use in source and binary forms, with or without # Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met: # modification, are permitted provided that the following conditions are met:
...@@ -30,6 +30,9 @@ ...@@ -30,6 +30,9 @@
SOC_DIR := plat/nvidia/tegra/soc/${TARGET_SOC} SOC_DIR := plat/nvidia/tegra/soc/${TARGET_SOC}
# Enable PSCI v1.0 extended state ID format
PSCI_EXTENDED_STATE_ID := 1
# Disable the PSCI platform compatibility layer # Disable the PSCI platform compatibility layer
ENABLE_PLAT_COMPAT := 0 ENABLE_PLAT_COMPAT := 0
......
plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
View file @ 86a3b266
/* /*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -59,36 +59,15 @@ static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; ...@@ -59,36 +59,15 @@ static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
int32_t tegra_soc_validate_power_state(unsigned int power_state, int32_t tegra_soc_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state) psci_power_state_t *req_state)
{ {
int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
int state_id = psci_get_pstate_id(power_state); int state_id = psci_get_pstate_id(power_state);
int cpu = read_mpidr() & MPIDR_CPU_MASK; int cpu = read_mpidr() & MPIDR_CPU_MASK;
if (pwr_lvl > PLAT_MAX_PWR_LVL)
return PSCI_E_INVALID_PARAMS;
/* Sanity check the requested afflvl */
if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) {
/*
* It's possible to enter standby only on affinity level 0 i.e.
* a cpu on Tegra. Ignore any other affinity level.
*/
if (pwr_lvl != MPIDR_AFFLVL0)
return PSCI_E_INVALID_PARAMS;
/* power domain in standby state */
req_state->pwr_domain_state[pwr_lvl] = PLAT_MAX_RET_STATE;
return PSCI_E_SUCCESS;
}
/* /*
* Sanity check the requested state id, power level and CPU number. * Sanity check the requested state id, power level and CPU number.
* Currently T132 only supports SYSTEM_SUSPEND on last standing CPU * Currently T132 only supports SYSTEM_SUSPEND on last standing CPU
* i.e. CPU 0 * i.e. CPU 0
*/ */
if ((pwr_lvl != PLAT_MAX_PWR_LVL) || if ((state_id != PSTATE_ID_SOC_POWERDN) || (cpu != 0)) {
(state_id != PSTATE_ID_SOC_POWERDN) ||
(cpu != 0)) {
ERROR("unsupported state id @ power level\n"); ERROR("unsupported state id @ power level\n");
return PSCI_E_INVALID_PARAMS; return PSCI_E_INVALID_PARAMS;
} }
...@@ -128,9 +107,26 @@ int tegra_soc_pwr_domain_on(u_register_t mpidr) ...@@ -128,9 +107,26 @@ int tegra_soc_pwr_domain_on(u_register_t mpidr)
return PSCI_E_SUCCESS; return PSCI_E_SUCCESS;
} }
int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
/*
* Lock scratch registers which hold the CPU vectors
*/
tegra_pmc_lock_cpu_vectors();
return PSCI_E_SUCCESS;
}
int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
{ {
tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
/* Disable DCO operations */
denver_disable_dco();
/* Power down the CPU */
write_actlr_el1(DENVER_CPU_STATE_POWER_DOWN);
return PSCI_E_SUCCESS; return PSCI_E_SUCCESS;
} }
...@@ -149,7 +145,10 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) ...@@ -149,7 +145,10 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
/* Program FC to enter suspend state */ /* Program FC to enter suspend state */
tegra_fc_cpu_powerdn(read_mpidr()); tegra_fc_cpu_powerdn(read_mpidr());
/* Suspend DCO operations */ /* Disable DCO operations */
denver_disable_dco();
/* Program the suspend state ID */
write_actlr_el1(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]); write_actlr_el1(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]);
return PSCI_E_SUCCESS; return PSCI_E_SUCCESS;
......
plat/nvidia/tegra/soc/t132/plat_sip_calls.c
View file @ 86a3b266
...@@ -35,8 +35,6 @@ ...@@ -35,8 +35,6 @@
#include <context_mgmt.h> #include <context_mgmt.h>
#include <debug.h> #include <debug.h>
#include <errno.h> #include <errno.h>
#include <memctrl.h>
#include <runtime_svc.h>
#include <tegra_private.h> #include <tegra_private.h>
#define NS_SWITCH_AARCH32 1 #define NS_SWITCH_AARCH32 1
...@@ -45,7 +43,6 @@ ...@@ -45,7 +43,6 @@
/******************************************************************************* /*******************************************************************************
* Tegra132 SiP SMCs * Tegra132 SiP SMCs
******************************************************************************/ ******************************************************************************/
#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
#define TEGRA_SIP_AARCH_SWITCH 0x82000004 #define TEGRA_SIP_AARCH_SWITCH 0x82000004
/******************************************************************************* /*******************************************************************************
...@@ -56,9 +53,9 @@ ...@@ -56,9 +53,9 @@
#define SPSR64 SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS) #define SPSR64 SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)
/******************************************************************************* /*******************************************************************************
* This function is responsible for handling all SiP calls from the NS world * This function is responsible for handling all T132 SiP calls
******************************************************************************/ ******************************************************************************/
uint64_t tegra132_sip_handler(uint32_t smc_fid, int plat_sip_handler(uint32_t smc_fid,
uint64_t x1, uint64_t x1,
uint64_t x2, uint64_t x2,
uint64_t x3, uint64_t x3,
...@@ -67,44 +64,8 @@ uint64_t tegra132_sip_handler(uint32_t smc_fid, ...@@ -67,44 +64,8 @@ uint64_t tegra132_sip_handler(uint32_t smc_fid,
void *handle, void *handle,
uint64_t flags) uint64_t flags)
{ {
uint32_t ns;
int err;
/* Determine which security state this SMC originated from */
ns = is_caller_non_secure(flags);
if (!ns)
SMC_RET1(handle, SMC_UNK);
switch (smc_fid) { switch (smc_fid) {
case TEGRA_SIP_NEW_VIDEOMEM_REGION:
/* clean up the high bits */
x1 = (uint32_t)x1;
x2 = (uint32_t)x2;
/*
* Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
* or falls outside of the valid DRAM range
*/
err = bl31_check_ns_address(x1, x2);
if (err)
SMC_RET1(handle, err);
/*
* Check if Video Memory is aligned to 1MB.
*/
if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) {
ERROR("Unaligned Video Memory base address!\n");
SMC_RET1(handle, -ENOTSUP);
}
/* new video memory carveout settings */
tegra_memctrl_videomem_setup(x1, x2);
SMC_RET1(handle, 0);
break;
case TEGRA_SIP_AARCH_SWITCH: case TEGRA_SIP_AARCH_SWITCH:
/* clean up the high bits */ /* clean up the high bits */
...@@ -113,7 +74,7 @@ uint64_t tegra132_sip_handler(uint32_t smc_fid, ...@@ -113,7 +74,7 @@ uint64_t tegra132_sip_handler(uint32_t smc_fid,
if (!x1 || x2 > NS_SWITCH_AARCH32) { if (!x1 || x2 > NS_SWITCH_AARCH32) {
ERROR("%s: invalid parameters\n", __func__); ERROR("%s: invalid parameters\n", __func__);
SMC_RET1(handle, SMC_UNK); return -EINVAL;
} }
/* x1 = ns entry point */ /* x1 = ns entry point */
...@@ -125,24 +86,12 @@ uint64_t tegra132_sip_handler(uint32_t smc_fid, ...@@ -125,24 +86,12 @@ uint64_t tegra132_sip_handler(uint32_t smc_fid,
INFO("CPU switched to AARCH%s mode\n", INFO("CPU switched to AARCH%s mode\n",
(x2 == NS_SWITCH_AARCH32) ? "32" : "64"); (x2 == NS_SWITCH_AARCH32) ? "32" : "64");
SMC_RET1(handle, 0); return 0;
break;
default: default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
break; break;
} }
SMC_RET1(handle, SMC_UNK); return -ENOTSUP;
} }
/* Define a runtime service descriptor for fast SMC calls */
DECLARE_RT_SVC(
tegra132_sip_fast,
OEN_SIP_START,
OEN_SIP_END,
SMC_TYPE_FAST,
NULL,
tegra132_sip_handler
);
plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
View file @ 86a3b266
/* /*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -58,39 +58,14 @@ static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; ...@@ -58,39 +58,14 @@ static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
int32_t tegra_soc_validate_power_state(unsigned int power_state, int32_t tegra_soc_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state) psci_power_state_t *req_state)
{ {
int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
int state_id = psci_get_pstate_id(power_state); int state_id = psci_get_pstate_id(power_state);
if (pwr_lvl > PLAT_MAX_PWR_LVL) {
ERROR("%s: unsupported power_state (0x%x)\n", __func__,
power_state);
return PSCI_E_INVALID_PARAMS;
}
/* Sanity check the requested afflvl */
if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) {
/*
* It's possible to enter standby only on affinity level 0 i.e.
* a cpu on Tegra. Ignore any other affinity level.
*/
if (pwr_lvl != MPIDR_AFFLVL0)
return PSCI_E_INVALID_PARAMS;
/* power domain in standby state */
req_state->pwr_domain_state[pwr_lvl] = PLAT_MAX_RET_STATE;
return PSCI_E_SUCCESS;
}
/* Sanity check the requested state id */ /* Sanity check the requested state id */
switch (state_id) { switch (state_id) {
case PSTATE_ID_CORE_POWERDN: case PSTATE_ID_CORE_POWERDN:
/* /*
* Core powerdown request only for afflvl 0 * Core powerdown request only for afflvl 0
*/ */
if (pwr_lvl != MPIDR_AFFLVL0)
goto error;
req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff;
break; break;
...@@ -100,9 +75,6 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, ...@@ -100,9 +75,6 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
/* /*
* Cluster powerdown/idle request only for afflvl 1 * Cluster powerdown/idle request only for afflvl 1
*/ */
if (pwr_lvl != MPIDR_AFFLVL1)
goto error;
req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id;
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
...@@ -112,9 +84,6 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, ...@@ -112,9 +84,6 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
/* /*
* System powerdown request only for afflvl 2 * System powerdown request only for afflvl 2
*/ */
if (pwr_lvl != PLAT_MAX_PWR_LVL)
goto error;
for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
...@@ -129,10 +98,6 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, ...@@ -129,10 +98,6 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
} }
return PSCI_E_SUCCESS; return PSCI_E_SUCCESS;
error:
ERROR("%s: unsupported state id (%d)\n", __func__, state_id);
return PSCI_E_INVALID_PARAMS;
} }
int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
...@@ -189,6 +154,11 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) ...@@ -189,6 +154,11 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
PLAT_SYS_SUSPEND_STATE_ID) { PLAT_SYS_SUSPEND_STATE_ID) {
/*
* Lock scratch registers which hold the CPU vectors
*/
tegra_pmc_lock_cpu_vectors();
/* /*
* Enable WRAP to INCR burst type conversions for * Enable WRAP to INCR burst type conversions for
* incoming requests on the AXI slave ports. * incoming requests on the AXI slave ports.
......
plat/nvidia/tegra/soc/t210/platform_t210.mk
View file @ 86a3b266
...@@ -51,7 +51,6 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ ...@@ -51,7 +51,6 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \ ${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \
${SOC_DIR}/plat_psci_handlers.c \ ${SOC_DIR}/plat_psci_handlers.c \
${SOC_DIR}/plat_sip_calls.c \
${SOC_DIR}/plat_setup.c \ ${SOC_DIR}/plat_setup.c \
${SOC_DIR}/plat_secondary.c ${SOC_DIR}/plat_secondary.c
......
services/spd/trusty/trusty.c
View file @ 86a3b266
...@@ -395,7 +395,7 @@ DECLARE_RT_SVC( ...@@ -395,7 +395,7 @@ DECLARE_RT_SVC(
DECLARE_RT_SVC( DECLARE_RT_SVC(
trusty_std, trusty_std,
OEN_TOS_START, OEN_TAP_START,
SMC_ENTITY_SECURE_MONITOR, SMC_ENTITY_SECURE_MONITOR,
SMC_TYPE_STD, SMC_TYPE_STD,
NULL, NULL,
......
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