diff --git a/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c b/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
index 4b044b7dbdcf55d09dcc90724bca3755388a8fd8..eda2c60f1f50940724c32cff5f82a289eb02611b 100644
--- a/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
+++ b/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
@@ -118,17 +118,16 @@ void qos_init_e3_v10(void)
 		    SL_INIT_SSLOTCLK_E3);
 	io_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_E3);
 
-	{
-		uint32_t i;
-
-		for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
-			io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
-			io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
-		}
-		for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
-			io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
-			io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
-		}
+	/* QOSBW SRAM setting */
+	uint32_t i;
+
+	for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+		io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+		io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+	}
+	for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+		io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+		io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
 	}
 
 	/* RT bus Leaf setting */