Merge changes from topic "tegra-downstream-02092020" into integration

* changes:
  Tegra: spe: uninit console on a timeout
  Tegra: handler to check support for System Suspend
  Tegra: bpmp_ipc: improve cyclomatic complexity
  Tegra: platform handler to relocate BL32 image
  Tegra: common: improve cyclomatic complexity
  Tegra210: secure PMC hardware block
  Tegra: delay_timer: support for physical secure timer
  include: move MHZ_TICKS_PER_SEC to utils_def.h
  Tegra194: memctrl: lock mc stream id security config
  Tegra210: resume PMC hardware block for all platforms
  Tegra: macro for legacy WDT FIQ handling
  Tegra186: enable higher performance non-cacheable load forwarding
  Tegra210: enable higher performance non-cacheable load forwarding
  cpus: higher performance non-cacheable load forwarding

plat/nvidia/tegra/soc/t210/plat_psci_handlers.c

@@ -394,6 +394,15 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
 			 */
 			tegra_reset_all_dma_masters();
 
+			/*
+			 * Mark PMC as accessible to the non-secure world
+			 * to allow the COP to execute System Suspend
+			 * sequence
+			 */
+			val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
+			val &= ~PMC_SECURITY_EN_BIT;
+			mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
+
 			/* clean up IRAM of any cruft */
 			zeromem((void *)(uintptr_t)TEGRA_IRAM_BASE,
 					TEGRA_IRAM_A_SIZE);
@@ -480,12 +489,14 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
 			tegra_bpmp_resume();
 		}
 
-		/* sc7entry-fw is part of TZDRAM area */
 		if (plat_params->sc7entry_fw_base != 0U) {
+			/* sc7entry-fw is part of TZDRAM area */
 			offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
 			tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
 				plat_params->tzdram_size + offset);
+		}
 
+		if (!tegra_chipid_is_t210_b01()) {
 			/* restrict PMC access to secure world */
 			val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
 			val |= PMC_SECURITY_EN_BIT;
@@ -533,10 +544,11 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
 	tegra_fc_lock_active_cluster();
 
 	/*
-         * Resume PMC hardware block for Tegra210 platforms supporting sc7entry-fw
+	 * Resume PMC hardware block for Tegra210 platforms
 	 */
-	if (!tegra_chipid_is_t210_b01() && (plat_params->sc7entry_fw_base != 0U))
+	if (!tegra_chipid_is_t210_b01()) {
 		tegra_pmc_resume();
+	}
 
 	return PSCI_E_SUCCESS;
 }

plat/nvidia/tegra/soc/t210/plat_setup.c

@@ -236,6 +236,13 @@ void plat_late_platform_setup(void)
 		val |= PMC_SECURITY_EN_BIT;
 		mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
 	}
+
+	if (!tegra_chipid_is_t210_b01()) {
+		/* restrict PMC access to secure world */
+		val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
+		val |= PMC_SECURITY_EN_BIT;
+		mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
+	}
 }
 
 /*******************************************************************************
@@ -255,3 +262,21 @@ void plat_gic_setup(void)
 	 */
 	tegra_fc_enable_fiq_to_ccplex_routing();
 }
+/*******************************************************************************
+ * Handler to indicate support for System Suspend
+ ******************************************************************************/
+bool plat_supports_system_suspend(void)
+{
+	const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
+
+	/*
+	 * sc7entry-fw is only supported by Tegra210 SoCs.
+	 */
+	if (!tegra_chipid_is_t210_b01() && (plat_params->sc7entry_fw_base != 0U)) {
+		return true;
+	} else if (tegra_chipid_is_t210_b01()) {
+		return true;
+	} else {
+		return false;
+	}
+}

plat/nvidia/tegra/soc/t210/platform_t210.mk

@@ -57,3 +57,6 @@ ERRATA_A53_855873		:=	1
 
 # Skip L1 $ flush when powering down Cortex-A57 CPUs
 SKIP_A57_L1_FLUSH_PWR_DWN	:=	1
+
+# Enable higher performance Non-cacheable load forwarding
+A57_ENABLE_NONCACHEABLE_LOAD_FWD	:=	1