From 87b5c17f915e3eccb4711e2adcf4e22cbb8af101 Mon Sep 17 00:00:00 2001 From: Lin Huang <hl@rock-chips.com> Date: Fri, 30 Dec 2016 13:53:25 +0800 Subject: [PATCH] rockchip: rk3399: fix PMU_CRU_GATEDIS_CON0 setting error As rk3399 TRM1.1 document show, when set PMU_CRU_GATEDIS_CON0/1 register, it need set the write_mask bit (bit16 ~ bit31), but as we test, it not need it. So need to correct the setting way, otherwise it will set wrong value to this register. Signed-off-by: Lin Huang <hl@rock-chips.com> --- plat/rockchip/rk3399/drivers/pmu/m0_ctl.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c index 66f3a19c8..47bd3e3d2 100644 --- a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c +++ b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c @@ -52,9 +52,8 @@ void m0_init(void) BITS_WITH_WMASK((M0_BINCODE_BASE >> 28) & 0xf, 0xf, 0)); - /* gating disable for M0 */ - mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, - BITS_WITH_WMASK(0x3, 0x3, 0)); + /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */ + mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02); /* * To switch the parent to xin24M and div == 1, -- GitLab