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Commit 91ecca23 authored by Olivier Deprez's avatar Olivier Deprez Committed by TrustedFirmware Code Review
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Merge changes from topic "spm-devel" into integration 

* changes:
  spm-mm: Rename aarch64 assembly files
  spm-mm: Rename source files
  spm-mm: Rename spm_shim_private.h
  spm-mm: Rename spm_private.h
  spm-mm: Rename component makefile
  spm-mm: Remove mm_svc.h header
  spm-mm: Refactor spm_svc.h and its contents
  spm-mm: Refactor secure_partition.h and its contents
  spm: Remove SPM Alpha 1 prototype and support files
  Remove dependency between SPM_MM and ENABLE_SPM build flags
parents b8e17967 99c69109
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services/std_svc/spm/README.rst deleted 100644 → 0
View file @ b8e17967
This is a prototype loosely based on the SPCI Alpha and SPRT pre-alpha
specifications. Any interface / platform API introduced for this is subject to
change as it evolves.
services/std_svc/spm/spci.c deleted 100644 → 0
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services/std_svc/spm/spm.mk deleted 100644 → 0
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#
# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
ifneq (${SPD},none)
$(error "Error: SPD and SPM are incompatible build options.")
endif
ifneq (${ARCH},aarch64)
$(error "Error: SPM is only supported on aarch64.")
endif
include lib/sprt/sprt_host.mk
SPM_SOURCES := $(addprefix services/std_svc/spm/, \
${ARCH}/spm_helpers.S \
${ARCH}/spm_shim_exceptions.S \
spci.c \
spm_buffers.c \
spm_main.c \
spm_setup.c \
spm_xlat.c \
sprt.c) \
${SPRT_LIB_SOURCES}
INCLUDES += ${SPRT_LIB_INCLUDES}
# Let the top-level Makefile know that we intend to include a BL32 image
NEED_BL32 := yes
services/std_svc/spm/spm_buffers.c deleted 100644 → 0
View file @ b8e17967
/*
* Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <lib/spinlock.h>
#include <lib/utils_def.h>
#include <platform_def.h>
#include "./spm_private.h"
/*******************************************************************************
* Secure Service response global array. All the responses to the requests done
* to the Secure Partition are stored here. They are removed from the array as
* soon as their value is read.
******************************************************************************/
struct sprt_response {
int is_valid;
uint32_t token;
uint16_t client_id, handle;
u_register_t x1, x2, x3;
};
static struct sprt_response responses[PLAT_SPM_RESPONSES_MAX];
static spinlock_t responses_lock;
/* Add response to the global response buffer. Returns 0 on success else -1. */
int spm_response_add(uint16_t client_id, uint16_t handle, uint32_t token,
u_register_t x1, u_register_t x2, u_register_t x3)
{
spin_lock(&responses_lock);
/* Make sure that there isn't any other response with the same token. */
for (unsigned int i = 0U; i < ARRAY_SIZE(responses); i++) {
struct sprt_response *resp = &(responses[i]);
if ((resp->is_valid == 1) && (resp->token == token)) {
spin_unlock(&responses_lock);
return -1;
}
}
for (unsigned int i = 0U; i < ARRAY_SIZE(responses); i++) {
struct sprt_response *resp = &(responses[i]);
if (resp->is_valid == 0) {
resp->token = token;
resp->client_id = client_id;
resp->handle = handle;
resp->x1 = x1;
resp->x2 = x2;
resp->x3 = x3;
dmbish();
resp->is_valid = 1;
spin_unlock(&responses_lock);
return 0;
}
}
spin_unlock(&responses_lock);
return -1;
}
/*
* Returns a response from the requests array and removes it from it. Returns 0
* on success, -1 if it wasn't found.
*/
int spm_response_get(uint16_t client_id, uint16_t handle, uint32_t token,
u_register_t *x1, u_register_t *x2, u_register_t *x3)
{
spin_lock(&responses_lock);
for (unsigned int i = 0U; i < ARRAY_SIZE(responses); i++) {
struct sprt_response *resp = &(responses[i]);
/* Ignore invalid entries */
if (resp->is_valid == 0) {
continue;
}
/* Make sure that all the information matches the stored one */
if ((resp->token != token) || (resp->client_id != client_id) ||
(resp->handle != handle)) {
continue;
}
*x1 = resp->x1;
*x2 = resp->x2;
*x3 = resp->x3;
dmbish();
resp->is_valid = 0;
spin_unlock(&responses_lock);
return 0;
}
spin_unlock(&responses_lock);
return -1;
}
services/std_svc/spm/spm_main.c deleted 100644 → 0
View file @ b8e17967
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <errno.h>
#include <string.h>
#include <arch_helpers.h>
#include <bl31/bl31.h>
#include <bl31/ehf.h>
#include <bl31/interrupt_mgmt.h>
#include <common/debug.h>
#include <common/runtime_svc.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/smccc.h>
#include <lib/spinlock.h>
#include <lib/utils.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <services/spm_svc.h>
#include <services/sprt_svc.h>
#include <smccc_helpers.h>
#include "spm_private.h"
/*******************************************************************************
* Secure Partition context information.
******************************************************************************/
sp_context_t sp_ctx_array[PLAT_SPM_MAX_PARTITIONS];
/* Last Secure Partition last used by the CPU */
sp_context_t *cpu_sp_ctx[PLATFORM_CORE_COUNT];
void spm_cpu_set_sp_ctx(unsigned int linear_id, sp_context_t *sp_ctx)
{
assert(linear_id < PLATFORM_CORE_COUNT);
cpu_sp_ctx[linear_id] = sp_ctx;
}
sp_context_t *spm_cpu_get_sp_ctx(unsigned int linear_id)
{
assert(linear_id < PLATFORM_CORE_COUNT);
return cpu_sp_ctx[linear_id];
}
/*******************************************************************************
* Functions to keep track of how many requests a Secure Partition has received
* and hasn't finished.
******************************************************************************/
void spm_sp_request_increase(sp_context_t *sp_ctx)
{
spin_lock(&(sp_ctx->request_count_lock));
sp_ctx->request_count++;
spin_unlock(&(sp_ctx->request_count_lock));
}
void spm_sp_request_decrease(sp_context_t *sp_ctx)
{
spin_lock(&(sp_ctx->request_count_lock));
sp_ctx->request_count--;
spin_unlock(&(sp_ctx->request_count_lock));
}
/* Returns 0 if it was originally 0, -1 otherwise. */
int spm_sp_request_increase_if_zero(sp_context_t *sp_ctx)
{
int ret = -1;
spin_lock(&(sp_ctx->request_count_lock));
if (sp_ctx->request_count == 0U) {
sp_ctx->request_count++;
ret = 0U;
}
spin_unlock(&(sp_ctx->request_count_lock));
return ret;
}
/*******************************************************************************
* This function returns a pointer to the context of the Secure Partition that
* handles the service specified by an UUID. It returns NULL if the UUID wasn't
* found.
******************************************************************************/
sp_context_t *spm_sp_get_by_uuid(const uint32_t (*svc_uuid)[4])
{
unsigned int i;
for (i = 0U; i < PLAT_SPM_MAX_PARTITIONS; i++) {
sp_context_t *sp_ctx = &sp_ctx_array[i];
if (sp_ctx->is_present == 0) {
continue;
}
struct sp_rd_sect_service *rdsvc;
for (rdsvc = sp_ctx->rd.service; rdsvc != NULL;
rdsvc = rdsvc->next) {
uint32_t *rd_uuid = (uint32_t *)(rdsvc->uuid);
if (memcmp(rd_uuid, svc_uuid, sizeof(*svc_uuid)) == 0) {
return sp_ctx;
}
}
}
return NULL;
}
/*******************************************************************************
* Set state of a Secure Partition context.
******************************************************************************/
void sp_state_set(sp_context_t *sp_ptr, sp_state_t state)
{
spin_lock(&(sp_ptr->state_lock));
sp_ptr->state = state;
spin_unlock(&(sp_ptr->state_lock));
}
/*******************************************************************************
* Wait until the state of a Secure Partition is the specified one and change it
* to the desired state.
******************************************************************************/
void sp_state_wait_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to)
{
int success = 0;
while (success == 0) {
spin_lock(&(sp_ptr->state_lock));
if (sp_ptr->state == from) {
sp_ptr->state = to;
success = 1;
}
spin_unlock(&(sp_ptr->state_lock));
}
}
/*******************************************************************************
* Check if the state of a Secure Partition is the specified one and, if so,
* change it to the desired state. Returns 0 on success, -1 on error.
******************************************************************************/
int sp_state_try_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to)
{
int ret = -1;
spin_lock(&(sp_ptr->state_lock));
if (sp_ptr->state == from) {
sp_ptr->state = to;
ret = 0;
}
spin_unlock(&(sp_ptr->state_lock));
return ret;
}
/*******************************************************************************
* This function takes an SP context pointer and performs a synchronous entry
* into it.
******************************************************************************/
uint64_t spm_sp_synchronous_entry(sp_context_t *sp_ctx, int can_preempt)
{
uint64_t rc;
unsigned int linear_id = plat_my_core_pos();
assert(sp_ctx != NULL);
/* Assign the context of the SP to this CPU */
spm_cpu_set_sp_ctx(linear_id, sp_ctx);
cm_set_context(&(sp_ctx->cpu_ctx), SECURE);
/* Restore the context assigned above */
cm_el1_sysregs_context_restore(SECURE);
cm_set_next_eret_context(SECURE);
/* Invalidate TLBs at EL1. */
tlbivmalle1();
dsbish();
if (can_preempt == 1) {
enable_intr_rm_local(INTR_TYPE_NS, SECURE);
} else {
disable_intr_rm_local(INTR_TYPE_NS, SECURE);
}
/* Enter Secure Partition */
rc = spm_secure_partition_enter(&sp_ctx->c_rt_ctx);
/* Save secure state */
cm_el1_sysregs_context_save(SECURE);
return rc;
}
/*******************************************************************************
* This function returns to the place where spm_sp_synchronous_entry() was
* called originally.
******************************************************************************/
__dead2 void spm_sp_synchronous_exit(uint64_t rc)
{
/* Get context of the SP in use by this CPU. */
unsigned int linear_id = plat_my_core_pos();
sp_context_t *ctx = spm_cpu_get_sp_ctx(linear_id);
/*
* The SPM must have initiated the original request through a
* synchronous entry into the secure partition. Jump back to the
* original C runtime context with the value of rc in x0;
*/
spm_secure_partition_exit(ctx->c_rt_ctx, rc);
panic();
}
/*******************************************************************************
* This function is the handler registered for Non secure interrupts by the SPM.
* It validates the interrupt and upon success arranges entry into the normal
* world for handling the interrupt.
******************************************************************************/
static uint64_t spm_ns_interrupt_handler(uint32_t id, uint32_t flags,
void *handle, void *cookie)
{
/* Check the security state when the exception was generated */
assert(get_interrupt_src_ss(flags) == SECURE);
spm_sp_synchronous_exit(SPM_SECURE_PARTITION_PREEMPTED);
}
/*******************************************************************************
* Jump to each Secure Partition for the first time.
******************************************************************************/
static int32_t spm_init(void)
{
uint64_t rc = 0;
sp_context_t *ctx;
for (unsigned int i = 0U; i < PLAT_SPM_MAX_PARTITIONS; i++) {
ctx = &sp_ctx_array[i];
if (ctx->is_present == 0) {
continue;
}
INFO("Secure Partition %u init...\n", i);
ctx->state = SP_STATE_RESET;
rc = spm_sp_synchronous_entry(ctx, 0);
if (rc != SPRT_YIELD_AARCH64) {
ERROR("Unexpected return value 0x%llx\n", rc);
panic();
}
ctx->state = SP_STATE_IDLE;
INFO("Secure Partition %u initialized.\n", i);
}
return rc;
}
/*******************************************************************************
* Initialize contexts of all Secure Partitions.
******************************************************************************/
int32_t spm_setup(void)
{
int rc;
sp_context_t *ctx;
void *sp_base, *rd_base;
size_t sp_size, rd_size;
uint64_t flags = 0U;
/* Disable MMU at EL1 (initialized by BL2) */
disable_mmu_icache_el1();
/*
* Non-blocking services can be interrupted by Non-secure interrupts.
* Register an interrupt handler for NS interrupts when generated while
* the CPU is in secure state. They are routed to EL3.
*/
set_interrupt_rm_flag(flags, SECURE);
uint64_t rc_int = register_interrupt_type_handler(INTR_TYPE_NS,
spm_ns_interrupt_handler, flags);
if (rc_int) {
ERROR("SPM: Failed to register NS interrupt handler with rc = %llx\n",
rc_int);
panic();
}
/* Setup shim layer */
spm_exceptions_xlat_init_context();
/*
* Setup all Secure Partitions.
*/
unsigned int i = 0U;
while (1) {
rc = plat_spm_sp_get_next_address(&sp_base, &sp_size,
&rd_base, &rd_size);
if (rc < 0) {
/* Reached the end of the package. */
break;
}
if (i >= PLAT_SPM_MAX_PARTITIONS) {
ERROR("Too many partitions in the package.\n");
panic();
}
ctx = &sp_ctx_array[i];
assert(ctx->is_present == 0);
/* Initialize context of the SP */
INFO("Secure Partition %u context setup start...\n", i);
/* Save location of the image in physical memory */
ctx->image_base = (uintptr_t)sp_base;
ctx->image_size = sp_size;
rc = plat_spm_sp_rd_load(&ctx->rd, rd_base, rd_size);
if (rc < 0) {
ERROR("Error while loading RD blob.\n");
panic();
}
spm_sp_setup(ctx);
ctx->is_present = 1;
INFO("Secure Partition %u setup done.\n", i);
i++;
}
if (i == 0U) {
ERROR("No present partitions in the package.\n");
panic();
}
/* Register init function for deferred init. */
bl31_register_bl32_init(&spm_init);
return 0;
}
services/std_svc/spm/spm_private.h deleted 100644 → 0
View file @ b8e17967
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPM_PRIVATE_H
#define SPM_PRIVATE_H
#include <context.h>
/*******************************************************************************
* Constants that allow assembler code to preserve callee-saved registers of the
* C runtime context while performing a security state switch.
******************************************************************************/
#define SP_C_RT_CTX_X19 0x0
#define SP_C_RT_CTX_X20 0x8
#define SP_C_RT_CTX_X21 0x10
#define SP_C_RT_CTX_X22 0x18
#define SP_C_RT_CTX_X23 0x20
#define SP_C_RT_CTX_X24 0x28
#define SP_C_RT_CTX_X25 0x30
#define SP_C_RT_CTX_X26 0x38
#define SP_C_RT_CTX_X27 0x40
#define SP_C_RT_CTX_X28 0x48
#define SP_C_RT_CTX_X29 0x50
#define SP_C_RT_CTX_X30 0x58
#define SP_C_RT_CTX_SIZE 0x60
#define SP_C_RT_CTX_ENTRIES (SP_C_RT_CTX_SIZE >> DWORD_SHIFT)
/* Value returned by spm_sp_synchronous_entry() when a partition is preempted */
#define SPM_SECURE_PARTITION_PREEMPTED U(0x1234)
#ifndef __ASSEMBLER__
#include <stdint.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <lib/spinlock.h>
#include <services/sp_res_desc.h>
typedef enum sp_state {
SP_STATE_RESET = 0,
SP_STATE_IDLE,
SP_STATE_BUSY
} sp_state_t;
typedef struct sp_context {
/* 1 if the partition is present, 0 otherwise */
int is_present;
/* Location of the image in physical memory */
unsigned long long image_base;
size_t image_size;
uint64_t c_rt_ctx;
cpu_context_t cpu_ctx;
struct sp_res_desc rd;
/* Translation tables context */
xlat_ctx_t *xlat_ctx_handle;
spinlock_t xlat_ctx_lock;
sp_state_t state;
spinlock_t state_lock;
unsigned int request_count;
spinlock_t request_count_lock;
/* Base and size of the shared SPM<->SP buffer */
uintptr_t spm_sp_buffer_base;
size_t spm_sp_buffer_size;
spinlock_t spm_sp_buffer_lock;
} sp_context_t;
/* Functions used to enter/exit a Secure Partition synchronously */
uint64_t spm_sp_synchronous_entry(sp_context_t *sp_ctx, int can_preempt);
__dead2 void spm_sp_synchronous_exit(uint64_t rc);
/* Assembly helpers */
uint64_t spm_secure_partition_enter(uint64_t *c_rt_ctx);
void __dead2 spm_secure_partition_exit(uint64_t c_rt_ctx, uint64_t ret);
/* Secure Partition setup */
void spm_sp_setup(sp_context_t *sp_ctx);
/* Secure Partition state management helpers */
void sp_state_set(sp_context_t *sp_ptr, sp_state_t state);
void sp_state_wait_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to);
int sp_state_try_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to);
/* Functions to keep track of the number of active requests per SP */
void spm_sp_request_increase(sp_context_t *sp_ctx);
void spm_sp_request_decrease(sp_context_t *sp_ctx);
int spm_sp_request_increase_if_zero(sp_context_t *sp_ctx);
/* Functions related to the shim layer translation tables */
void spm_exceptions_xlat_init_context(void);
uint64_t *spm_exceptions_xlat_get_base_table(void);
/* Functions related to the translation tables management */
void spm_sp_xlat_context_alloc(sp_context_t *sp_ctx);
void sp_map_memory_regions(sp_context_t *sp_ctx);
/* Functions to handle Secure Partition contexts */
void spm_cpu_set_sp_ctx(unsigned int linear_id, sp_context_t *sp_ctx);
sp_context_t *spm_cpu_get_sp_ctx(unsigned int linear_id);
sp_context_t *spm_sp_get_by_uuid(const uint32_t (*svc_uuid)[4]);
/* Functions to manipulate response and requests buffers */
int spm_response_add(uint16_t client_id, uint16_t handle, uint32_t token,
u_register_t x1, u_register_t x2, u_register_t x3);
int spm_response_get(uint16_t client_id, uint16_t handle, uint32_t token,
u_register_t *x1, u_register_t *x2, u_register_t *x3);
#endif /* __ASSEMBLER__ */
#endif /* SPM_PRIVATE_H */
services/std_svc/spm/spm_setup.c deleted 100644 → 0
View file @ b8e17967
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <string.h>
#include <platform_def.h>
#include <arch.h>
#include <arch_helpers.h>
#include <context.h>
#include <common/debug.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/common_def.h>
#include <plat/common/platform.h>
#include <services/sp_res_desc.h>
#include <sprt_host.h>
#include "spm_private.h"
#include "spm_shim_private.h"
/* Setup context of the Secure Partition */
void spm_sp_setup(sp_context_t *sp_ctx)
{
cpu_context_t *ctx = &(sp_ctx->cpu_ctx);
/*
* Initialize CPU context
* ----------------------
*/
entry_point_info_t ep_info = {0};
SET_PARAM_HEAD(&ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE);
/* Setup entrypoint and SPSR */
ep_info.pc = sp_ctx->rd.attribute.entrypoint;
ep_info.spsr = SPSR_64(MODE_EL0, MODE_SP_EL0, DISABLE_ALL_EXCEPTIONS);
/*
* X0: Unused (MBZ).
* X1: Unused (MBZ).
* X2: cookie value (Implementation Defined)
* X3: cookie value (Implementation Defined)
* X4 to X7 = 0
*/
ep_info.args.arg0 = 0;
ep_info.args.arg1 = 0;
ep_info.args.arg2 = PLAT_SPM_COOKIE_0;
ep_info.args.arg3 = PLAT_SPM_COOKIE_1;
cm_setup_context(ctx, &ep_info);
/*
* Setup translation tables
* ------------------------
*/
/* Assign translation tables context. */
spm_sp_xlat_context_alloc(sp_ctx);
sp_map_memory_regions(sp_ctx);
/*
* MMU-related registers
* ---------------------
*/
xlat_ctx_t *xlat_ctx = sp_ctx->xlat_ctx_handle;
uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
setup_mmu_cfg((uint64_t *)&mmu_cfg_params, 0, xlat_ctx->base_table,
xlat_ctx->pa_max_address, xlat_ctx->va_max_address,
EL1_EL0_REGIME);
write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1,
mmu_cfg_params[MMU_CFG_MAIR]);
/* Enable translations using TTBR1_EL1 */
int t1sz = 64 - __builtin_ctzll(SPM_SHIM_XLAT_VIRT_ADDR_SPACE_SIZE);
mmu_cfg_params[MMU_CFG_TCR] &= ~TCR_EPD1_BIT;
mmu_cfg_params[MMU_CFG_TCR] |=
((uint64_t)t1sz << TCR_T1SZ_SHIFT) |
TCR_SH1_INNER_SHAREABLE |
TCR_RGN1_OUTER_WBA | TCR_RGN1_INNER_WBA |
TCR_TG1_4K;
write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1,
mmu_cfg_params[MMU_CFG_TCR]);
write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1,
mmu_cfg_params[MMU_CFG_TTBR0]);
write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR1_EL1,
(uint64_t)spm_exceptions_xlat_get_base_table());
/* Setup SCTLR_EL1 */
u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1);
sctlr_el1 |=
/*SCTLR_EL1_RES1 |*/
/* Don't trap DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU */
SCTLR_UCI_BIT |
/* RW regions at xlat regime EL1&0 are forced to be XN. */
SCTLR_WXN_BIT |
/* Don't trap to EL1 execution of WFI or WFE at EL0. */
SCTLR_NTWI_BIT | SCTLR_NTWE_BIT |
/* Don't trap to EL1 accesses to CTR_EL0 from EL0. */
SCTLR_UCT_BIT |
/* Don't trap to EL1 execution of DZ ZVA at EL0. */
SCTLR_DZE_BIT |
/* Enable SP Alignment check for EL0 */
SCTLR_SA0_BIT |
/* Allow cacheable data and instr. accesses to normal memory. */
SCTLR_C_BIT | SCTLR_I_BIT |
/* Alignment fault checking enabled when at EL1 and EL0. */
SCTLR_A_BIT |
/* Enable MMU. */
SCTLR_M_BIT
;
sctlr_el1 &= ~(
/* Explicit data accesses at EL0 are little-endian. */
SCTLR_E0E_BIT |
/* Accesses to DAIF from EL0 are trapped to EL1. */
SCTLR_UMA_BIT
);
write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1);
/*
* Setup other system registers
* ----------------------------
*/
/*
* Shim exception vector base address. It is mapped at the start of the
* address space accessed by TTBR1_EL1, which means that the base
* address of the exception vectors depends on the size of the address
* space specified in TCR_EL1.T1SZ.
*/
write_ctx_reg(get_sysregs_ctx(ctx), CTX_VBAR_EL1,
UINT64_MAX - (SPM_SHIM_XLAT_VIRT_ADDR_SPACE_SIZE - 1ULL));
/*
* FPEN: Allow the Secure Partition to access FP/SIMD registers.
* Note that SPM will not do any saving/restoring of these registers on
* behalf of the SP. This falls under the SP's responsibility.
* TTA: Enable access to trace registers.
* ZEN (v8.2): Trap SVE instructions and access to SVE registers.
*/
write_ctx_reg(get_sysregs_ctx(ctx), CTX_CPACR_EL1,
CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE));
/*
* Prepare shared buffers
* ----------------------
*/
/* Initialize SPRT queues */
sprt_initialize_queues((void *)sp_ctx->spm_sp_buffer_base,
sp_ctx->spm_sp_buffer_size);
}
services/std_svc/spm/spm_shim_private.h deleted 100644 → 0
View file @ b8e17967
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPM_SHIM_PRIVATE_H
#define SPM_SHIM_PRIVATE_H
#include <stdint.h>
#include <lib/utils_def.h>
/* Assembly source */
IMPORT_SYM(uintptr_t, spm_shim_exceptions_ptr, SPM_SHIM_EXCEPTIONS_PTR);
/* Linker symbols */
IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_START__, SPM_SHIM_EXCEPTIONS_START);
IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_END__, SPM_SHIM_EXCEPTIONS_END);
/* Definitions */
#define SPM_SHIM_EXCEPTIONS_SIZE \
(SPM_SHIM_EXCEPTIONS_END - SPM_SHIM_EXCEPTIONS_START)
/*
* Use the smallest virtual address space size allowed in ARMv8.0 for
* compatibility.
*/
#define SPM_SHIM_XLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 25)
#define SPM_SHIM_MMAP_REGIONS 1
#define SPM_SHIM_XLAT_TABLES 1
#endif /* SPM_SHIM_PRIVATE_H */
services/std_svc/spm/spm_xlat.c deleted 100644 → 0
View file @ b8e17967
/*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <arch_features.h>
#include <arch_helpers.h>
#include <assert.h>
#include <errno.h>
#include <string.h>
#include <platform_def.h>
#include <lib/object_pool.h>
#include <lib/utils.h>
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <services/sp_res_desc.h>
#include "spm_private.h"
#include "spm_shim_private.h"
/*******************************************************************************
* Instantiation of translation table context
******************************************************************************/
/* Place translation tables by default along with the ones used by BL31. */
#ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME
#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "xlat_table"
#endif
/*
* Allocate elements of the translation contexts for the Secure Partitions.
*/
/* Allocate an array of mmap_region per partition. */
static struct mmap_region sp_mmap_regions[PLAT_SP_IMAGE_MMAP_REGIONS + 1]
[PLAT_SPM_MAX_PARTITIONS];
static OBJECT_POOL(sp_mmap_regions_pool, sp_mmap_regions,
sizeof(mmap_region_t) * (PLAT_SP_IMAGE_MMAP_REGIONS + 1),
PLAT_SPM_MAX_PARTITIONS);
/* Allocate individual translation tables. */
static uint64_t sp_xlat_tables[XLAT_TABLE_ENTRIES]
[(PLAT_SP_IMAGE_MAX_XLAT_TABLES + 1) * PLAT_SPM_MAX_PARTITIONS]
__aligned(XLAT_TABLE_SIZE) __section(PLAT_SP_IMAGE_XLAT_SECTION_NAME);
static OBJECT_POOL(sp_xlat_tables_pool, sp_xlat_tables,
XLAT_TABLE_ENTRIES * sizeof(uint64_t),
(PLAT_SP_IMAGE_MAX_XLAT_TABLES + 1) * PLAT_SPM_MAX_PARTITIONS);
/* Allocate arrays. */
static int sp_xlat_mapped_regions[PLAT_SP_IMAGE_MAX_XLAT_TABLES]
[PLAT_SPM_MAX_PARTITIONS];
static OBJECT_POOL(sp_xlat_mapped_regions_pool, sp_xlat_mapped_regions,
sizeof(int) * PLAT_SP_IMAGE_MAX_XLAT_TABLES, PLAT_SPM_MAX_PARTITIONS);
/* Allocate individual contexts. */
static xlat_ctx_t sp_xlat_ctx[PLAT_SPM_MAX_PARTITIONS];
static OBJECT_POOL(sp_xlat_ctx_pool, sp_xlat_ctx, sizeof(xlat_ctx_t),
PLAT_SPM_MAX_PARTITIONS);
/* Get handle of Secure Partition translation context */
void spm_sp_xlat_context_alloc(sp_context_t *sp_ctx)
{
/* Allocate xlat context elements */
xlat_ctx_t *ctx = pool_alloc(&sp_xlat_ctx_pool);
struct mmap_region *mmap = pool_alloc(&sp_mmap_regions_pool);
uint64_t *base_table = pool_alloc(&sp_xlat_tables_pool);
uint64_t **tables = pool_alloc_n(&sp_xlat_tables_pool,
PLAT_SP_IMAGE_MAX_XLAT_TABLES);
int *mapped_regions = pool_alloc(&sp_xlat_mapped_regions_pool);
/* Calculate the size of the virtual address space needed */
uintptr_t va_size = 0U;
struct sp_rd_sect_mem_region *rdmem;
for (rdmem = sp_ctx->rd.mem_region; rdmem != NULL; rdmem = rdmem->next) {
uintptr_t end_va = (uintptr_t)rdmem->base +
(uintptr_t)rdmem->size;
if (end_va > va_size)
va_size = end_va;
}
if (va_size == 0U) {
ERROR("No regions in resource description.\n");
panic();
}
/*
* Get the power of two that is greater or equal to the top VA. The
* values of base and size in the resource description are 32-bit wide
* so the values will never overflow when using a uintptr_t.
*/
if (!IS_POWER_OF_TWO(va_size)) {
va_size = 1ULL <<
((sizeof(va_size) * 8) - __builtin_clzll(va_size));
}
if (va_size > PLAT_VIRT_ADDR_SPACE_SIZE) {
ERROR("Resource description requested too much virtual memory.\n");
panic();
}
uintptr_t min_va_size;
/* The following sizes are only valid for 4KB pages */
assert(PAGE_SIZE == (4U * 1024U));
if (is_armv8_4_ttst_present()) {
VERBOSE("Using ARMv8.4-TTST\n");
min_va_size = 1ULL << (64 - TCR_TxSZ_MAX_TTST);
} else {
min_va_size = 1ULL << (64 - TCR_TxSZ_MAX);
}
if (va_size < min_va_size) {
va_size = min_va_size;
}
/* Initialize xlat context */
xlat_setup_dynamic_ctx(ctx, PLAT_PHY_ADDR_SPACE_SIZE - 1ULL,
va_size - 1ULL, mmap,
PLAT_SP_IMAGE_MMAP_REGIONS, tables,
PLAT_SP_IMAGE_MAX_XLAT_TABLES, base_table,
EL1_EL0_REGIME, mapped_regions);
sp_ctx->xlat_ctx_handle = ctx;
};
/*******************************************************************************
* Translation table context used for S-EL1 exception vectors
******************************************************************************/
REGISTER_XLAT_CONTEXT2(spm_sel1, SPM_SHIM_MMAP_REGIONS, SPM_SHIM_XLAT_TABLES,
SPM_SHIM_XLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE,
EL1_EL0_REGIME, PLAT_SP_IMAGE_XLAT_SECTION_NAME);
void spm_exceptions_xlat_init_context(void)
{
/* This region contains the exception vectors used at S-EL1. */
mmap_region_t sel1_exception_vectors =
MAP_REGION(SPM_SHIM_EXCEPTIONS_PTR,
0x0UL,
SPM_SHIM_EXCEPTIONS_SIZE,
MT_CODE | MT_SECURE | MT_PRIVILEGED);
mmap_add_region_ctx(&spm_sel1_xlat_ctx,
&sel1_exception_vectors);
init_xlat_tables_ctx(&spm_sel1_xlat_ctx);
}
uint64_t *spm_exceptions_xlat_get_base_table(void)
{
return spm_sel1_xlat_ctx.base_table;
}
/*******************************************************************************
* Functions to allocate memory for regions.
******************************************************************************/
/*
* The region with base PLAT_SPM_HEAP_BASE and size PLAT_SPM_HEAP_SIZE is
* reserved for SPM to use as heap to allocate memory regions of Secure
* Partitions. This is only done at boot.
*/
static OBJECT_POOL(spm_heap_mem, (void *)PLAT_SPM_HEAP_BASE, 1U,
PLAT_SPM_HEAP_SIZE);
static uintptr_t spm_alloc_heap(size_t size)
{
return (uintptr_t)pool_alloc_n(&spm_heap_mem, size);
}
/*******************************************************************************
* Functions to map memory regions described in the resource description.
******************************************************************************/
static unsigned int rdmem_attr_to_mmap_attr(uint32_t attr)
{
unsigned int index = attr & RD_MEM_MASK;
const unsigned int mmap_attr_arr[8] = {
MT_DEVICE | MT_RW | MT_SECURE, /* RD_MEM_DEVICE */
MT_CODE | MT_SECURE, /* RD_MEM_NORMAL_CODE */
MT_MEMORY | MT_RW | MT_SECURE, /* RD_MEM_NORMAL_DATA */
MT_MEMORY | MT_RW | MT_SECURE, /* RD_MEM_NORMAL_BSS */
MT_RO_DATA | MT_SECURE, /* RD_MEM_NORMAL_RODATA */
MT_MEMORY | MT_RW | MT_SECURE, /* RD_MEM_NORMAL_SPM_SP_SHARED_MEM */
MT_MEMORY | MT_RW | MT_SECURE, /* RD_MEM_NORMAL_CLIENT_SHARED_MEM */
MT_MEMORY | MT_RW | MT_SECURE /* RD_MEM_NORMAL_MISCELLANEOUS */
};
if (index >= ARRAY_SIZE(mmap_attr_arr)) {
ERROR("Unsupported RD memory attributes 0x%x\n", attr);
panic();
}
return mmap_attr_arr[index];
}
/*
* The data provided in the resource description structure is not directly
* compatible with a mmap_region structure. This function handles the conversion
* and maps it.
*/
static void map_rdmem(sp_context_t *sp_ctx, struct sp_rd_sect_mem_region *rdmem)
{
int rc;
mmap_region_t mmap;
/* Location of the SP image */
uintptr_t sp_size = sp_ctx->image_size;
uintptr_t sp_base_va = sp_ctx->rd.attribute.load_address;
unsigned long long sp_base_pa = sp_ctx->image_base;
/* Location of the memory region to map */
size_t rd_size = rdmem->size;
uintptr_t rd_base_va = rdmem->base;
unsigned long long rd_base_pa;
unsigned int memtype = rdmem->attr & RD_MEM_MASK;
if (rd_size == 0U) {
VERBOSE("Memory region '%s' is empty. Ignored.\n", rdmem->name);
return;
}
VERBOSE("Adding memory region '%s'\n", rdmem->name);
mmap.granularity = REGION_DEFAULT_GRANULARITY;
/* Check if the RD region is inside of the SP image or not */
int is_outside = (rd_base_va + rd_size <= sp_base_va) ||
(sp_base_va + sp_size <= rd_base_va);
/* Set to 1 if it is needed to zero this region */
int zero_region = 0;
switch (memtype) {
case RD_MEM_DEVICE:
/* Device regions are mapped 1:1 */
rd_base_pa = rd_base_va;
break;
case RD_MEM_NORMAL_CODE:
case RD_MEM_NORMAL_RODATA:
{
if (is_outside == 1) {
ERROR("Code and rodata sections must be fully contained in the image.");
panic();
}
/* Get offset into the image */
rd_base_pa = sp_base_pa + rd_base_va - sp_base_va;
break;
}
case RD_MEM_NORMAL_DATA:
{
if (is_outside == 1) {
ERROR("Data sections must be fully contained in the image.");
panic();
}
rd_base_pa = spm_alloc_heap(rd_size);
/* Get offset into the image */
void *img_pa = (void *)(sp_base_pa + rd_base_va - sp_base_va);
VERBOSE(" Copying data from %p to 0x%llx\n", img_pa, rd_base_pa);
/* Map destination */
rc = mmap_add_dynamic_region(rd_base_pa, rd_base_pa,
rd_size, MT_MEMORY | MT_RW | MT_SECURE);
if (rc != 0) {
ERROR("Unable to map data region at EL3: %d\n", rc);
panic();
}
/* Copy original data to destination */
memcpy((void *)rd_base_pa, img_pa, rd_size);
/* Unmap destination region */
rc = mmap_remove_dynamic_region(rd_base_pa, rd_size);
if (rc != 0) {
ERROR("Unable to remove data region at EL3: %d\n", rc);
panic();
}
break;
}
case RD_MEM_NORMAL_MISCELLANEOUS:
/* Allow SPM to change the attributes of the region. */
mmap.granularity = PAGE_SIZE;
rd_base_pa = spm_alloc_heap(rd_size);
zero_region = 1;
break;
case RD_MEM_NORMAL_SPM_SP_SHARED_MEM:
if ((sp_ctx->spm_sp_buffer_base != 0) ||
(sp_ctx->spm_sp_buffer_size != 0)) {
ERROR("A partition must have only one SPM<->SP buffer.\n");
panic();
}
rd_base_pa = spm_alloc_heap(rd_size);
zero_region = 1;
/* Save location of this buffer, it is needed by SPM */
sp_ctx->spm_sp_buffer_base = rd_base_pa;
sp_ctx->spm_sp_buffer_size = rd_size;
break;
case RD_MEM_NORMAL_CLIENT_SHARED_MEM:
/* Fallthrough */
case RD_MEM_NORMAL_BSS:
rd_base_pa = spm_alloc_heap(rd_size);
zero_region = 1;
break;
default:
panic();
}
mmap.base_pa = rd_base_pa;
mmap.base_va = rd_base_va;
mmap.size = rd_size;
/* Only S-EL0 mappings supported for now */
mmap.attr = rdmem_attr_to_mmap_attr(rdmem->attr) | MT_USER;
VERBOSE(" VA: 0x%lx PA: 0x%llx (0x%lx, attr: 0x%x)\n",
mmap.base_va, mmap.base_pa, mmap.size, mmap.attr);
/* Map region in the context of the Secure Partition */
mmap_add_region_ctx(sp_ctx->xlat_ctx_handle, &mmap);
if (zero_region == 1) {
VERBOSE(" Zeroing region...\n");
rc = mmap_add_dynamic_region(mmap.base_pa, mmap.base_pa,
mmap.size, MT_MEMORY | MT_RW | MT_SECURE);
if (rc != 0) {
ERROR("Unable to map memory at EL3 to zero: %d\n",
rc);
panic();
}
zeromem((void *)mmap.base_pa, mmap.size);
/*
* Unmap destination region unless it is the SPM<->SP buffer,
* which must be used by SPM.
*/
if (memtype != RD_MEM_NORMAL_SPM_SP_SHARED_MEM) {
rc = mmap_remove_dynamic_region(rd_base_pa, rd_size);
if (rc != 0) {
ERROR("Unable to remove region at EL3: %d\n", rc);
panic();
}
}
}
}
void sp_map_memory_regions(sp_context_t *sp_ctx)
{
struct sp_rd_sect_mem_region *rdmem;
for (rdmem = sp_ctx->rd.mem_region; rdmem != NULL; rdmem = rdmem->next) {
map_rdmem(sp_ctx, rdmem);
}
init_xlat_tables_ctx(sp_ctx->xlat_ctx_handle);
}
services/std_svc/spm/sprt.c deleted 100644 → 0
View file @ b8e17967
/*
* Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <errno.h>
#include <limits.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <common/runtime_svc.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/smccc.h>
#include <lib/utils.h>
#include <plat/common/platform.h>
#include <services/sprt_svc.h>
#include <smccc_helpers.h>
#include "spm_private.h"
/*******************************************************************************
* Functions to manipulate memory regions
******************************************************************************/
/*
* Attributes are encoded using a different format in the SMC interface than in
* the Trusted Firmware, where the mmap_attr_t enum type is used. This function
* converts an attributes value from the SMC format to the mmap_attr_t format by
* setting MT_RW/MT_RO, MT_USER/MT_PRIVILEGED and MT_EXECUTE/MT_EXECUTE_NEVER.
* The other fields are left as 0 because they are ignored by the function
* xlat_change_mem_attributes_ctx().
*/
static unsigned int smc_attr_to_mmap_attr(unsigned int attributes)
{
unsigned int perm = attributes & SPRT_MEMORY_PERM_ATTR_MASK;
if (perm == SPRT_MEMORY_PERM_ATTR_RW) {
return MT_RW | MT_EXECUTE_NEVER | MT_USER;
} else if (perm == SPRT_MEMORY_PERM_ATTR_RO) {
return MT_RO | MT_EXECUTE_NEVER | MT_USER;
} else if (perm == SPRT_MEMORY_PERM_ATTR_RO_EXEC) {
return MT_RO | MT_USER;
} else {
return UINT_MAX;
}
}
/*
* This function converts attributes from the Trusted Firmware format into the
* SMC interface format.
*/
static unsigned int mmap_attr_to_smc_attr(unsigned int attr)
{
unsigned int perm;
/* No access from EL0. */
if ((attr & MT_USER) == 0U)
return UINT_MAX;
if ((attr & MT_RW) != 0) {
assert(MT_TYPE(attr) != MT_DEVICE);
perm = SPRT_MEMORY_PERM_ATTR_RW;
} else {
if ((attr & MT_EXECUTE_NEVER) != 0U) {
perm = SPRT_MEMORY_PERM_ATTR_RO;
} else {
perm = SPRT_MEMORY_PERM_ATTR_RO_EXEC;
}
}
return perm << SPRT_MEMORY_PERM_ATTR_SHIFT;
}
static int32_t sprt_memory_perm_attr_get(sp_context_t *sp_ctx, uintptr_t base_va)
{
uint32_t attributes;
spin_lock(&(sp_ctx->xlat_ctx_lock));
int ret = xlat_get_mem_attributes_ctx(sp_ctx->xlat_ctx_handle,
base_va, &attributes);
spin_unlock(&(sp_ctx->xlat_ctx_lock));
/* Convert error codes of xlat_get_mem_attributes_ctx() into SPM. */
assert((ret == 0) || (ret == -EINVAL));
if (ret != 0)
return SPRT_INVALID_PARAMETER;
unsigned int perm = mmap_attr_to_smc_attr(attributes);
if (perm == UINT_MAX)
return SPRT_INVALID_PARAMETER;
return SPRT_SUCCESS | perm;
}
static int32_t sprt_memory_perm_attr_set(sp_context_t *sp_ctx,
u_register_t page_address, u_register_t pages_count,
u_register_t smc_attributes)
{
int ret;
uintptr_t base_va = (uintptr_t) page_address;
size_t size = pages_count * PAGE_SIZE;
VERBOSE(" Start address : 0x%lx\n", base_va);
VERBOSE(" Number of pages: %i (%zi bytes)\n", (int) pages_count, size);
VERBOSE(" Attributes : 0x%lx\n", smc_attributes);
uint32_t mmap_attr = smc_attr_to_mmap_attr(smc_attributes);
if (mmap_attr == UINT_MAX) {
WARN("%s: Invalid memory attributes: 0x%lx\n", __func__,
smc_attributes);
return SPRT_INVALID_PARAMETER;
}
/*
* Perform some checks before actually trying to change the memory
* attributes.
*/
spin_lock(&(sp_ctx->xlat_ctx_lock));
uint32_t attributes;
ret = xlat_get_mem_attributes_ctx(sp_ctx->xlat_ctx_handle,
base_va, &attributes);
if (ret != 0) {
spin_unlock(&(sp_ctx->xlat_ctx_lock));
return SPRT_INVALID_PARAMETER;
}
if ((attributes & MT_USER) == 0U) {
/* Prohibit changing attributes of S-EL1 regions */
spin_unlock(&(sp_ctx->xlat_ctx_lock));
return SPRT_INVALID_PARAMETER;
}
ret = xlat_change_mem_attributes_ctx(sp_ctx->xlat_ctx_handle,
base_va, size, mmap_attr);
spin_unlock(&(sp_ctx->xlat_ctx_lock));
/* Convert error codes of xlat_change_mem_attributes_ctx() into SPM. */
assert((ret == 0) || (ret == -EINVAL));
return (ret == 0) ? SPRT_SUCCESS : SPRT_INVALID_PARAMETER;
}
/*******************************************************************************
* This function handles all SMCs in the range reserved for SPRT.
******************************************************************************/
static uintptr_t sprt_smc_handler(uint32_t smc_fid, u_register_t x1,
u_register_t x2, u_register_t x3,
u_register_t x4, void *cookie, void *handle,
u_register_t flags)
{
/* SPRT only supported from the Secure world */
if (is_caller_non_secure(flags) == SMC_FROM_NON_SECURE) {
SMC_RET1(handle, SMC_UNK);
}
assert(handle == cm_get_context(SECURE));
/*
* Only S-EL0 partitions are supported for now. Make the next ERET into
* the partition jump directly to S-EL0 instead of S-EL1.
*/
cm_set_elr_spsr_el3(SECURE, read_elr_el1(), read_spsr_el1());
switch (smc_fid) {
case SPRT_VERSION:
SMC_RET1(handle, SPRT_VERSION_COMPILED);
case SPRT_PUT_RESPONSE_AARCH64:
spm_sp_synchronous_exit(SPRT_PUT_RESPONSE_AARCH64);
case SPRT_YIELD_AARCH64:
spm_sp_synchronous_exit(SPRT_YIELD_AARCH64);
case SPRT_MEMORY_PERM_ATTR_GET_AARCH64:
{
/* Get context of the SP in use by this CPU. */
unsigned int linear_id = plat_my_core_pos();
sp_context_t *sp_ctx = spm_cpu_get_sp_ctx(linear_id);
SMC_RET1(handle, sprt_memory_perm_attr_get(sp_ctx, x1));
}
case SPRT_MEMORY_PERM_ATTR_SET_AARCH64:
{
/* Get context of the SP in use by this CPU. */
unsigned int linear_id = plat_my_core_pos();
sp_context_t *sp_ctx = spm_cpu_get_sp_ctx(linear_id);
SMC_RET1(handle, sprt_memory_perm_attr_set(sp_ctx, x1, x2, x3));
}
default:
break;
}
WARN("SPRT: Unsupported call 0x%08x\n", smc_fid);
SMC_RET1(handle, SPRT_NOT_SUPPORTED);
}
DECLARE_RT_SVC(
sprt_handler,
OEN_SPRT_START,
OEN_SPRT_END,
SMC_TYPE_FAST,
NULL,
sprt_smc_handler
);
services/std_svc/spm_mm/aarch64/spm_helpers.S deleted 100644 → 0
View file @ b8e17967
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm_macros.S>
#include "../spm_private.h"
.global spm_secure_partition_enter
.global spm_secure_partition_exit
/* ---------------------------------------------------------------------
* This function is called with SP_EL0 as stack. Here we stash our EL3
* callee-saved registers on to the stack as a part of saving the C
* runtime and enter the secure payload.
* 'x0' contains a pointer to the memory where the address of the C
* runtime context is to be saved.
* ---------------------------------------------------------------------
*/
func spm_secure_partition_enter
/* Make space for the registers that we're going to save */
mov x3, sp
str x3, [x0, #0]
sub sp, sp, #SP_C_RT_CTX_SIZE
/* Save callee-saved registers on to the stack */
stp x19, x20, [sp, #SP_C_RT_CTX_X19]
stp x21, x22, [sp, #SP_C_RT_CTX_X21]
stp x23, x24, [sp, #SP_C_RT_CTX_X23]
stp x25, x26, [sp, #SP_C_RT_CTX_X25]
stp x27, x28, [sp, #SP_C_RT_CTX_X27]
stp x29, x30, [sp, #SP_C_RT_CTX_X29]
/* ---------------------------------------------------------------------
* Everything is setup now. el3_exit() will use the secure context to
* restore to the general purpose and EL3 system registers to ERET
* into the secure payload.
* ---------------------------------------------------------------------
*/
b el3_exit
endfunc spm_secure_partition_enter
/* ---------------------------------------------------------------------
* This function is called with 'x0' pointing to a C runtime context
* saved in spm_secure_partition_enter().
* It restores the saved registers and jumps to that runtime with 'x0'
* as the new SP register. This destroys the C runtime context that had
* been built on the stack below the saved context by the caller. Later
* the second parameter 'x1' is passed as a return value to the caller.
* ---------------------------------------------------------------------
*/
func spm_secure_partition_exit
/* Restore the previous stack */
mov sp, x0
/* Restore callee-saved registers on to the stack */
ldp x19, x20, [x0, #(SP_C_RT_CTX_X19 - SP_C_RT_CTX_SIZE)]
ldp x21, x22, [x0, #(SP_C_RT_CTX_X21 - SP_C_RT_CTX_SIZE)]
ldp x23, x24, [x0, #(SP_C_RT_CTX_X23 - SP_C_RT_CTX_SIZE)]
ldp x25, x26, [x0, #(SP_C_RT_CTX_X25 - SP_C_RT_CTX_SIZE)]
ldp x27, x28, [x0, #(SP_C_RT_CTX_X27 - SP_C_RT_CTX_SIZE)]
ldp x29, x30, [x0, #(SP_C_RT_CTX_X29 - SP_C_RT_CTX_SIZE)]
/* ---------------------------------------------------------------------
* This should take us back to the instruction after the call to the
* last spm_secure_partition_enter().* Place the second parameter to x0
* so that the caller will see it as a return value from the original
* entry call.
* ---------------------------------------------------------------------
*/
mov x0, x1
ret
endfunc spm_secure_partition_exit
services/std_svc/spm/aarch64/spm_helpers.S → services/std_svc/spm_mm/aarch64/spm_mm_helpers.S
View file @ 91ecca23
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm_macros.S>
#include "../spm_private.h"
#include "../spm_mm_private.h"
.global spm_secure_partition_enter
.global spm_secure_partition_exit
......
services/std_svc/spm_mm/aarch64/spm_shim_exceptions.S deleted 100644 → 0
View file @ b8e17967
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
#include <context.h>
/* -----------------------------------------------------------------------------
* Very simple stackless exception handlers used by the spm shim layer.
* -----------------------------------------------------------------------------
*/
.globl spm_shim_exceptions_ptr
vector_base spm_shim_exceptions_ptr, .spm_shim_exceptions
/* -----------------------------------------------------
* Current EL with SP0 : 0x0 - 0x200
* -----------------------------------------------------
*/
vector_entry SynchronousExceptionSP0, .spm_shim_exceptions
b .
end_vector_entry SynchronousExceptionSP0
vector_entry IrqSP0, .spm_shim_exceptions
b .
end_vector_entry IrqSP0
vector_entry FiqSP0, .spm_shim_exceptions
b .
end_vector_entry FiqSP0
vector_entry SErrorSP0, .spm_shim_exceptions
b .
end_vector_entry SErrorSP0
/* -----------------------------------------------------
* Current EL with SPx: 0x200 - 0x400
* -----------------------------------------------------
*/
vector_entry SynchronousExceptionSPx, .spm_shim_exceptions
b .
end_vector_entry SynchronousExceptionSPx
vector_entry IrqSPx, .spm_shim_exceptions
b .
end_vector_entry IrqSPx
vector_entry FiqSPx, .spm_shim_exceptions
b .
end_vector_entry FiqSPx
vector_entry SErrorSPx, .spm_shim_exceptions
b .
end_vector_entry SErrorSPx
/* -----------------------------------------------------
* Lower EL using AArch64 : 0x400 - 0x600. No exceptions
* are handled since secure_partition does not implement
* a lower EL
* -----------------------------------------------------
*/
vector_entry SynchronousExceptionA64, .spm_shim_exceptions
msr tpidr_el1, x30
mrs x30, esr_el1
ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
cmp x30, #EC_AARCH64_SVC
b.eq do_smc
cmp x30, #EC_AARCH32_SVC
b.eq do_smc
cmp x30, #EC_AARCH64_SYS
b.eq handle_sys_trap
/* Fail in all the other cases */
b panic
/* ---------------------------------------------
* Tell SPM that we are done initialising
* ---------------------------------------------
*/
do_smc:
mrs x30, tpidr_el1
smc #0
eret
/* AArch64 system instructions trap are handled as a panic for now */
handle_sys_trap:
panic:
b panic
end_vector_entry SynchronousExceptionA64
vector_entry IrqA64, .spm_shim_exceptions
b .
end_vector_entry IrqA64
vector_entry FiqA64, .spm_shim_exceptions
b .
end_vector_entry FiqA64
vector_entry SErrorA64, .spm_shim_exceptions
b .
end_vector_entry SErrorA64
/* -----------------------------------------------------
* Lower EL using AArch32 : 0x600 - 0x800
* -----------------------------------------------------
*/
vector_entry SynchronousExceptionA32, .spm_shim_exceptions
b .
end_vector_entry SynchronousExceptionA32
vector_entry IrqA32, .spm_shim_exceptions
b .
end_vector_entry IrqA32
vector_entry FiqA32, .spm_shim_exceptions
b .
end_vector_entry FiqA32
vector_entry SErrorA32, .spm_shim_exceptions
b .
end_vector_entry SErrorA32
services/std_svc/spm_mm/spm.mk → services/std_svc/spm_mm/spm_mm.mk
View file @ 91ecca23
#
# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
ifneq (${SPD},none)
$(error "Error: SPD and SPM are incompatible build options.")
$(error "Error: SPD and SPM_MM are incompatible build options.")
endif
ifneq (${ARCH},aarch64)
$(error "Error: SPM is only supported on aarch64.")
$(error "Error: SPM_MM is only supported on aarch64.")
endif
SPM_SOURCES := $(addprefix services/std_svc/spm_mm/, \
${ARCH}/spm_helpers.S \
${ARCH}/spm_shim_exceptions.S \
spm_main.c \
spm_setup.c \
spm_xlat.c)
${ARCH}/spm_mm_helpers.S \
${ARCH}/spm_mm_shim_exceptions.S \
spm_mm_main.c \
spm_mm_setup.c \
spm_mm_xlat.c)
# Let the top-level Makefile know that we intend to include a BL32 image
......
services/std_svc/spm_mm/spm_main.c → services/std_svc/spm_mm/spm_mm_main.c
View file @ 91ecca23
......@@ -18,12 +18,11 @@
#include <lib/utils.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <services/mm_svc.h>
#include <services/secure_partition.h>
#include <services/spm_svc.h>
#include <services/spm_mm_partition.h>
#include <services/spm_mm_svc.h>
#include <smccc_helpers.h>
#include "spm_private.h"
#include "spm_mm_private.h"
/*******************************************************************************
* Secure Partition context information.
......@@ -157,7 +156,7 @@ static int32_t spm_init(void)
/*******************************************************************************
* Initialize contexts of all Secure Partitions.
******************************************************************************/
int32_t spm_setup(void)
int32_t spm_mm_setup(void)
{
sp_context_t *ctx;
......@@ -185,7 +184,7 @@ int32_t spm_setup(void)
/*******************************************************************************
* Function to perform a call to a Secure Partition.
******************************************************************************/
uint64_t spm_sp_call(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3)
uint64_t spm_mm_sp_call(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3)
{
uint64_t rc;
sp_context_t *sp_ptr = &sp_ctx;
......@@ -223,12 +222,12 @@ static uint64_t mm_communicate(uint32_t smc_fid, uint64_t mm_cookie,
/* Cookie. Reserved for future use. It must be zero. */
if (mm_cookie != 0U) {
ERROR("MM_COMMUNICATE: cookie is not zero\n");
SMC_RET1(handle, SPM_INVALID_PARAMETER);
SMC_RET1(handle, SPM_MM_INVALID_PARAMETER);
}
if (comm_buffer_address == 0U) {
ERROR("MM_COMMUNICATE: comm_buffer_address is zero\n");
SMC_RET1(handle, SPM_INVALID_PARAMETER);
SMC_RET1(handle, SPM_MM_INVALID_PARAMETER);
}
if (comm_size_address != 0U) {
......@@ -251,7 +250,7 @@ static uint64_t mm_communicate(uint32_t smc_fid, uint64_t mm_cookie,
/* Save the Normal world context */
cm_el1_sysregs_context_save(NON_SECURE);
rc = spm_sp_call(smc_fid, comm_buffer_address, comm_size_address,
rc = spm_mm_sp_call(smc_fid, comm_buffer_address, comm_size_address,
plat_my_core_pos());
/* Restore non-secure state */
......@@ -270,7 +269,7 @@ static uint64_t mm_communicate(uint32_t smc_fid, uint64_t mm_cookie,
/*******************************************************************************
* Secure Partition Manager SMC handler.
******************************************************************************/
uint64_t spm_smc_handler(uint32_t smc_fid,
uint64_t spm_mm_smc_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
......@@ -295,29 +294,29 @@ uint64_t spm_smc_handler(uint32_t smc_fid,
switch (smc_fid) {
case SPM_VERSION_AARCH32:
SMC_RET1(handle, SPM_VERSION_COMPILED);
case SPM_MM_VERSION_AARCH32:
SMC_RET1(handle, SPM_MM_VERSION_COMPILED);
case SP_EVENT_COMPLETE_AARCH64:
case MM_SP_EVENT_COMPLETE_AARCH64:
spm_sp_synchronous_exit(x1);
case SP_MEMORY_ATTRIBUTES_GET_AARCH64:
INFO("Received SP_MEMORY_ATTRIBUTES_GET_AARCH64 SMC\n");
case MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64:
INFO("Received MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 SMC\n");
if (sp_ctx.state != SP_STATE_RESET) {
WARN("SP_MEMORY_ATTRIBUTES_GET_AARCH64 is available at boot time only\n");
SMC_RET1(handle, SPM_NOT_SUPPORTED);
WARN("MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 is available at boot time only\n");
SMC_RET1(handle, SPM_MM_NOT_SUPPORTED);
}
SMC_RET1(handle,
spm_memory_attributes_get_smc_handler(
&sp_ctx, x1));
case SP_MEMORY_ATTRIBUTES_SET_AARCH64:
INFO("Received SP_MEMORY_ATTRIBUTES_SET_AARCH64 SMC\n");
case MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64:
INFO("Received MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64 SMC\n");
if (sp_ctx.state != SP_STATE_RESET) {
WARN("SP_MEMORY_ATTRIBUTES_SET_AARCH64 is available at boot time only\n");
SMC_RET1(handle, SPM_NOT_SUPPORTED);
WARN("MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64 is available at boot time only\n");
SMC_RET1(handle, SPM_MM_NOT_SUPPORTED);
}
SMC_RET1(handle,
spm_memory_attributes_set_smc_handler(
......@@ -340,10 +339,10 @@ uint64_t spm_smc_handler(uint32_t smc_fid,
case MM_COMMUNICATE_AARCH64:
return mm_communicate(smc_fid, x1, x2, x3, handle);
case SP_MEMORY_ATTRIBUTES_GET_AARCH64:
case SP_MEMORY_ATTRIBUTES_SET_AARCH64:
case MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64:
case MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64:
/* SMC interfaces reserved for secure callers. */
SMC_RET1(handle, SPM_NOT_SUPPORTED);
SMC_RET1(handle, SPM_MM_NOT_SUPPORTED);
default:
break;
......
services/std_svc/spm_mm/spm_private.h → services/std_svc/spm_mm/spm_mm_private.h
View file @ 91ecca23
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPM_PRIVATE_H
#define SPM_PRIVATE_H
#ifndef SPM_MM_PRIVATE_H
#define SPM_MM_PRIVATE_H
#include <context.h>
......@@ -68,4 +68,4 @@ int spm_memory_attributes_set_smc_handler(sp_context_t *sp_ctx,
#endif /* __ASSEMBLER__ */
#endif /* SPM_PRIVATE_H */
#endif /* SPM_MM_PRIVATE_H */
services/std_svc/spm_mm/spm_setup.c → services/std_svc/spm_mm/spm_mm_setup.c
View file @ 91ecca23
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -16,10 +16,10 @@
#include <platform_def.h>
#include <plat/common/common_def.h>
#include <plat/common/platform.h>
#include <services/secure_partition.h>
#include <services/spm_mm_partition.h>
#include "spm_private.h"
#include "spm_shim_private.h"
#include "spm_mm_private.h"
#include "spm_mm_shim_private.h"
/* Setup context of the Secure Partition */
void spm_sp_setup(sp_context_t *sp_ctx)
......@@ -192,22 +192,22 @@ void spm_sp_setup(sp_context_t *sp_ctx)
void *shared_buf_ptr = (void *) PLAT_SPM_BUF_BASE;
/* Copy the boot information into the shared buffer with the SP. */
assert((uintptr_t)shared_buf_ptr + sizeof(secure_partition_boot_info_t)
assert((uintptr_t)shared_buf_ptr + sizeof(spm_mm_boot_info_t)
<= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE));
assert(PLAT_SPM_BUF_BASE <= (UINTPTR_MAX - PLAT_SPM_BUF_SIZE + 1));
const secure_partition_boot_info_t *sp_boot_info =
const spm_mm_boot_info_t *sp_boot_info =
plat_get_secure_partition_boot_info(NULL);
assert(sp_boot_info != NULL);
memcpy((void *) shared_buf_ptr, (const void *) sp_boot_info,
sizeof(secure_partition_boot_info_t));
sizeof(spm_mm_boot_info_t));
/* Pointer to the MP information from the platform port. */
secure_partition_mp_info_t *sp_mp_info =
((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info;
spm_mm_mp_info_t *sp_mp_info =
((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info;
assert(sp_mp_info != NULL);
......@@ -215,15 +215,15 @@ void spm_sp_setup(sp_context_t *sp_ctx)
* Point the shared buffer MP information pointer to where the info will
* be populated, just after the boot info.
*/
((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info =
(secure_partition_mp_info_t *) ((uintptr_t)shared_buf_ptr
+ sizeof(secure_partition_boot_info_t));
((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info =
(spm_mm_mp_info_t *) ((uintptr_t)shared_buf_ptr
+ sizeof(spm_mm_boot_info_t));
/*
* Update the shared buffer pointer to where the MP information for the
* payload will be populated
*/
shared_buf_ptr = ((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info;
shared_buf_ptr = ((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info;
/*
* Copy the cpu information into the shared buffer area after the boot
......@@ -242,7 +242,7 @@ void spm_sp_setup(sp_context_t *sp_ctx)
* Calculate the linear indices of cores in boot information for the
* secure partition and flag the primary CPU
*/
sp_mp_info = (secure_partition_mp_info_t *) shared_buf_ptr;
sp_mp_info = (spm_mm_mp_info_t *) shared_buf_ptr;
for (unsigned int index = 0; index < sp_boot_info->num_cpus; index++) {
u_register_t mpidr = sp_mp_info[index].mpidr;
......
services/std_svc/spm_mm/spm_shim_private.h → services/std_svc/spm_mm/spm_mm_shim_private.h
View file @ 91ecca23
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPM_SHIM_PRIVATE_H
#define SPM_SHIM_PRIVATE_H
#ifndef SPM_MM_SHIM_PRIVATE_H
#define SPM_MM_SHIM_PRIVATE_H
#include <stdint.h>
......@@ -23,4 +23,4 @@ IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_END__, SPM_SHIM_EXCEPTIONS_END);
#define SPM_SHIM_EXCEPTIONS_SIZE \
(SPM_SHIM_EXCEPTIONS_END - SPM_SHIM_EXCEPTIONS_START)
#endif /* SPM_SHIM_PRIVATE_H */
#endif /* SPM_MM_SHIM_PRIVATE_H */
services/std_svc/spm_mm/spm_xlat.c → services/std_svc/spm_mm/spm_mm_xlat.c
View file @ 91ecca23
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -11,11 +11,11 @@
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <platform_def.h>
#include <plat/common/platform.h>
#include <services/secure_partition.h>
#include <services/spm_svc.h>
#include <services/spm_mm_partition.h>
#include <services/spm_mm_svc.h>
#include "spm_private.h"
#include "spm_shim_private.h"
#include "spm_mm_private.h"
#include "spm_mm_shim_private.h"
/* Place translation tables by default along with the ones used by BL31. */
#ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME
......@@ -50,21 +50,21 @@ static unsigned int smc_attr_to_mmap_attr(unsigned int attributes)
{
unsigned int tf_attr = 0U;
unsigned int access = (attributes & SP_MEMORY_ATTRIBUTES_ACCESS_MASK)
>> SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT;
unsigned int access = (attributes & MM_SP_MEMORY_ATTRIBUTES_ACCESS_MASK)
>> MM_SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT;
if (access == SP_MEMORY_ATTRIBUTES_ACCESS_RW) {
if (access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_RW) {
tf_attr |= MT_RW | MT_USER;
} else if (access == SP_MEMORY_ATTRIBUTES_ACCESS_RO) {
} else if (access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_RO) {
tf_attr |= MT_RO | MT_USER;
} else {
/* Other values are reserved. */
assert(access == SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS);
assert(access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS);
/* The only requirement is that there's no access from EL0 */
tf_attr |= MT_RO | MT_PRIVILEGED;
}
if ((attributes & SP_MEMORY_ATTRIBUTES_NON_EXEC) == 0) {
if ((attributes & MM_SP_MEMORY_ATTRIBUTES_NON_EXEC) == 0) {
tf_attr |= MT_EXECUTE;
} else {
tf_attr |= MT_EXECUTE_NEVER;
......@@ -85,21 +85,21 @@ static unsigned int smc_mmap_to_smc_attr(unsigned int attr)
if ((attr & MT_USER) == 0) {
/* No access from EL0. */
data_access = SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS;
data_access = MM_SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS;
} else {
if ((attr & MT_RW) != 0) {
assert(MT_TYPE(attr) != MT_DEVICE);
data_access = SP_MEMORY_ATTRIBUTES_ACCESS_RW;
data_access = MM_SP_MEMORY_ATTRIBUTES_ACCESS_RW;
} else {
data_access = SP_MEMORY_ATTRIBUTES_ACCESS_RO;
data_access = MM_SP_MEMORY_ATTRIBUTES_ACCESS_RO;
}
}
smc_attr |= (data_access & SP_MEMORY_ATTRIBUTES_ACCESS_MASK)
<< SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT;
smc_attr |= (data_access & MM_SP_MEMORY_ATTRIBUTES_ACCESS_MASK)
<< MM_SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT;
if ((attr & MT_EXECUTE_NEVER) != 0U) {
smc_attr |= SP_MEMORY_ATTRIBUTES_NON_EXEC;
smc_attr |= MM_SP_MEMORY_ATTRIBUTES_NON_EXEC;
}
return smc_attr;
......@@ -123,7 +123,7 @@ int32_t spm_memory_attributes_get_smc_handler(sp_context_t *sp_ctx,
if (rc == 0) {
return (int32_t) smc_mmap_to_smc_attr(attributes);
} else {
return SPM_INVALID_PARAMETER;
return SPM_MM_INVALID_PARAMETER;
}
}
......@@ -151,5 +151,5 @@ int spm_memory_attributes_set_smc_handler(sp_context_t *sp_ctx,
/* Convert error codes of xlat_change_mem_attributes_ctx() into SPM. */
assert((ret == 0) || (ret == -EINVAL));
return (ret == 0) ? SPM_SUCCESS : SPM_INVALID_PARAMETER;
return (ret == 0) ? SPM_MM_SUCCESS : SPM_MM_INVALID_PARAMETER;
}
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