From 91ffc1deffa2c1c64efe4dfaf27b78f2621a8b0b Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Thu, 24 Sep 2020 16:01:12 +0200 Subject: [PATCH] fix(plat/st): improve DDR get size function Avoid parsing device tree every time when returning the DDR size. A cache flush on this size is also added because TZC400 configuration is applied at the end of BL2 after MMU and data cache being turned off. Configuration needs to retrieve the DDR size to generate the correct region. Access to the size fails because the value is still in the data cache. Flushing the size is mandatory. Change-Id: I3dd1958f37d806f9c15a5d4151968935f6fe642e Signed-off-by: Lionel Debieve Signed-off-by: Yann Gautier --- plat/st/common/stm32mp_dt.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c index 6465c10e8..0b3564692 100644 --- a/plat/st/common/stm32mp_dt.c +++ b/plat/st/common/stm32mp_dt.c @@ -209,15 +209,24 @@ int dt_get_stdout_uart_info(struct dt_node_info *info) ******************************************************************************/ uint32_t dt_get_ddr_size(void) { + static uint32_t size; int node; + if (size != 0U) { + return size; + } + node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT); if (node < 0) { INFO("%s: Cannot read DDR node in DT\n", __func__); return 0; } - return fdt_read_uint32_default(fdt, node, "st,mem-size", 0); + size = fdt_read_uint32_default(fdt, node, "st,mem-size", 0U); + + flush_dcache_range((uintptr_t)&size, sizeof(uint32_t)); + + return size; } /******************************************************************************* -- GitLab