diff --git a/docs/plat/nvidia-tegra.md b/docs/plat/nvidia-tegra.md index e4f9a05e9155bb3eef1f79dbd4cd21951b299b1f..1ff8c70687a5f52baec1bffa277491be1d573bef 100644 --- a/docs/plat/nvidia-tegra.md +++ b/docs/plat/nvidia-tegra.md @@ -28,3 +28,10 @@ Preparing the BL31 image to run on Tegra SoCs CROSS_COMPILE=/bin/aarch64-none-elf- make PLAT=tegra \ TARGET_SOC= BL32= \ SPD= all + +Power Management +================ +The PSCI implementation expects each platform to expose the 'power state' +parameter to be used during the 'SYSTEM SUSPEND' call. The state-id field +is implementation defined on Tegra SoCs and is preferably defined by +tegra_def.h. diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c index 243407d16efd569c05b79cdb889a801c6dfd1ac3..bcaaf412bf1c1fe75fa18a8644fac7b819b89dbb 100644 --- a/plat/nvidia/tegra/common/tegra_pm.c +++ b/plat/nvidia/tegra/common/tegra_pm.c @@ -113,6 +113,22 @@ void tegra_affinst_standby(unsigned int power_state) wfi(); } +/******************************************************************************* + * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND` + * call to get the `power_state` parameter. This allows the platform to encode + * the appropriate State-ID field within the `power_state` parameter which can + * be utilized in `affinst_suspend()` to suspend to system affinity level. +******************************************************************************/ +unsigned int tegra_get_sys_suspend_power_state(void) +{ + unsigned int power_state; + + power_state = psci_make_powerstate(PLAT_SYS_SUSPEND_STATE_ID, + PSTATE_TYPE_POWERDOWN, MPIDR_AFFLVL2); + + return power_state; +} + /******************************************************************************* * Handler called to check the validity of the power state parameter. ******************************************************************************/ @@ -310,7 +326,8 @@ static const plat_pm_ops_t tegra_plat_pm_ops = { .affinst_suspend_finish = tegra_affinst_suspend_finish, .system_off = tegra_system_off, .system_reset = tegra_system_reset, - .validate_power_state = tegra_validate_power_state + .validate_power_state = tegra_validate_power_state, + .get_sys_suspend_power_state = tegra_get_sys_suspend_power_state }; /******************************************************************************* diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h index c72d081bae40b2603f6d977296c498d2fbda7a5c..a54de5a1bdc640e72f23afd6d6a1c31378a0ed0b 100644 --- a/plat/nvidia/tegra/include/t210/tegra_def.h +++ b/plat/nvidia/tegra/include/t210/tegra_def.h @@ -33,6 +33,20 @@ #include +/******************************************************************************* + * Power down state IDs + ******************************************************************************/ +#define PSTATE_ID_CORE_POWERDN 7 +#define PSTATE_ID_CLUSTER_IDLE 16 +#define PSTATE_ID_CLUSTER_POWERDN 17 +#define PSTATE_ID_SOC_POWERDN 27 + +/******************************************************************************* + * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` + * call as the `state-id` field in the 'power state' parameter. + ******************************************************************************/ +#define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN + /******************************************************************************* * Implementation defined ACTLR_EL3 bit definitions ******************************************************************************/ diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c index 7ac784b57e414c2adcd4bac4b6ef5c6abd44ae14..f594d2097263af19ec963ea3c65a7efff57f66bc 100644 --- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c @@ -40,12 +40,6 @@ #include #include -/* Power down state IDs */ -#define PSTATE_ID_CORE_POWERDN 7 -#define PSTATE_ID_CLUSTER_IDLE 16 -#define PSTATE_ID_CLUSTER_POWERDN 17 -#define PSTATE_ID_SOC_POWERDN 27 - static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl)