diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index bedf26888419243ab27898cd735bffb227c8dc5e..212bd48e668fd76e08ad98e6df490b03bbbd9163 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -75,6 +75,8 @@
 
 #define MC_SECURITY_CFG_REG_CTRL_0	U(0x154)
 #define  SECURITY_CFG_WRITE_ACCESS_BIT	(U(0x1) << 0)
+#define  SECURITY_CFG_WRITE_ACCESS_ENABLE	U(0x0)
+#define  SECURITY_CFG_WRITE_ACCESS_DISABLE	U(0x1)
 
 /* Video Memory carveout configuration registers */
 #define MC_VIDEO_PROTECT_BASE_HI	U(0x978)
diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
index 75705cff1a1aa86a690ef040a7ff526283d5e7d6..54dbe7cdb470a8e4ec801be302915b5710d7b9c1 100644
--- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
@@ -646,12 +646,14 @@ tegra_mc_settings_t *tegra_get_mc_settings(void)
  ******************************************************************************/
 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
 {
+	uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0);
+
 	/*
-	 * Check if the carveout register is already locked, if locked
-	 * no TZDRAM setup
+	 * Check TZDRAM carveout register access status. Setup TZDRAM fence
+	 * only if access is enabled.
 	 */
-	if ((tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0) &
-		SECURITY_CFG_WRITE_ACCESS_BIT) == SECURITY_CFG_WRITE_ACCESS_BIT) {
+	if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) ==
+	     SECURITY_CFG_WRITE_ACCESS_ENABLE) {
 
 		/*
 		 * Setup the Memory controller to allow only secure accesses to